2 * QEMU generic PPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 /*****************************************************************************/
28 /* PPC time base and decrementer emulation */
32 /* Time base management */
33 int64_t tb_offset; /* Compensation */
34 uint32_t tb_freq; /* TB frequency */
35 /* Decrementer management */
36 uint64_t decr_next; /* Tick for next decr interrupt */
37 struct QEMUTimer *decr_timer;
40 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
42 /* TB time in tb periods */
43 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
44 tb_env->tb_freq, ticks_per_sec);
47 uint32_t cpu_ppc_load_tbl (CPUState *env)
49 ppc_tb_t *tb_env = env->tb_env;
52 tb = cpu_ppc_get_tb(tb_env);
58 if (last_time != now) {
60 printf("%s: tb=0x%016lx %d %08lx\n",
61 __func__, tb, now, tb_env->tb_offset);
66 return tb & 0xFFFFFFFF;
69 uint32_t cpu_ppc_load_tbu (CPUState *env)
71 ppc_tb_t *tb_env = env->tb_env;
74 tb = cpu_ppc_get_tb(tb_env);
76 printf("%s: tb=0x%016lx\n", __func__, tb);
82 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
84 tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
85 - qemu_get_clock(vm_clock);
87 printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
91 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
93 ppc_tb_t *tb_env = env->tb_env;
95 cpu_ppc_store_tb(tb_env,
96 ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
99 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
101 ppc_tb_t *tb_env = env->tb_env;
103 cpu_ppc_store_tb(tb_env,
104 ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
107 uint32_t cpu_ppc_load_decr (CPUState *env)
109 ppc_tb_t *tb_env = env->tb_env;
113 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
115 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
117 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
118 #if defined(DEBUG_TB)
119 printf("%s: 0x%08x\n", __func__, decr);
125 /* When decrementer expires,
126 * all we need to do is generate or queue a CPU exception
128 static inline void cpu_ppc_decr_excp (CPUState *env)
132 printf("raise decrementer exception\n");
134 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
137 static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
138 uint32_t value, int is_excp)
140 ppc_tb_t *tb_env = env->tb_env;
144 printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
146 now = qemu_get_clock(vm_clock);
147 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
149 next += tb_env->decr_next - now;
152 tb_env->decr_next = next;
154 qemu_mod_timer(tb_env->decr_timer, next);
155 /* If we set a negative value and the decrementer was positive,
156 * raise an exception.
158 if ((value & 0x80000000) && !(decr & 0x80000000))
159 cpu_ppc_decr_excp(env);
162 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
164 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
167 static void cpu_ppc_decr_cb (void *opaque)
169 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
172 /* Set up (once) timebase frequency (in Hz) */
173 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
177 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
180 env->tb_env = tb_env;
181 if (tb_env->tb_freq == 0 || 1) {
182 tb_env->tb_freq = freq;
183 /* Create new timer */
185 qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
186 /* There is a bug in Linux 2.4 kernels:
187 * if a decrementer exception is pending when it enables msr_ee,
188 * it's not ready to handle it...
190 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
196 /* Specific helpers for POWER & PowerPC 601 RTC */
197 ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
199 return cpu_ppc_tb_init(env, 7812500);
202 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
203 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
205 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
206 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
208 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
210 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
213 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
215 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
218 /* Embedded PowerPC timers */
219 target_ulong load_40x_pit (CPUState *env)
225 void store_40x_pit (CPUState *env, target_ulong val)
230 void store_booke_tcr (CPUState *env, target_ulong val)
235 void store_booke_tsr (CPUState *env, target_ulong val)
241 /*****************************************************************************/
242 /* Handle system reset (for now, just stop emulation) */
243 void cpu_ppc_reset (CPUState *env)
245 printf("Reset asked... Stop emulation\n");
250 /*****************************************************************************/
252 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
264 printf("Set loglevel to %04x\n", val);
265 cpu_set_log(val | 0x100);
270 /*****************************************************************************/
272 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
274 m48t59_write(nvram, addr, value);
277 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
279 return m48t59_read(nvram, addr);
282 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
284 m48t59_write(nvram, addr, value >> 8);
285 m48t59_write(nvram, addr + 1, value & 0xFF);
288 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
292 tmp = m48t59_read(nvram, addr) << 8;
293 tmp |= m48t59_read(nvram, addr + 1);
297 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
299 m48t59_write(nvram, addr, value >> 24);
300 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
301 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
302 m48t59_write(nvram, addr + 3, value & 0xFF);
305 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
309 tmp = m48t59_read(nvram, addr) << 24;
310 tmp |= m48t59_read(nvram, addr + 1) << 16;
311 tmp |= m48t59_read(nvram, addr + 2) << 8;
312 tmp |= m48t59_read(nvram, addr + 3);
317 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
318 const unsigned char *str, uint32_t max)
322 for (i = 0; i < max && str[i] != '\0'; i++) {
323 m48t59_write(nvram, addr + i, str[i]);
325 m48t59_write(nvram, addr + max - 1, '\0');
328 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
333 for (i = 0; i < max; i++) {
334 dst[i] = NVRAM_get_byte(nvram, addr + i);
342 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
345 uint16_t pd, pd1, pd2;
350 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
351 tmp ^= (pd1 << 3) | (pd1 << 8);
352 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
357 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
360 uint16_t crc = 0xFFFF;
365 for (i = 0; i != count; i++) {
366 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
369 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
375 #define CMDLINE_ADDR 0x017ff000
377 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
378 const unsigned char *arch,
379 uint32_t RAM_size, int boot_device,
380 uint32_t kernel_image, uint32_t kernel_size,
382 uint32_t initrd_image, uint32_t initrd_size,
383 uint32_t NVRAM_image,
384 int width, int height, int depth)
388 /* Set parameters for Open Hack'Ware BIOS */
389 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
390 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
391 NVRAM_set_word(nvram, 0x14, NVRAM_size);
392 NVRAM_set_string(nvram, 0x20, arch, 16);
393 NVRAM_set_lword(nvram, 0x30, RAM_size);
394 NVRAM_set_byte(nvram, 0x34, boot_device);
395 NVRAM_set_lword(nvram, 0x38, kernel_image);
396 NVRAM_set_lword(nvram, 0x3C, kernel_size);
398 /* XXX: put the cmdline in NVRAM too ? */
399 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
400 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
401 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
403 NVRAM_set_lword(nvram, 0x40, 0);
404 NVRAM_set_lword(nvram, 0x44, 0);
406 NVRAM_set_lword(nvram, 0x48, initrd_image);
407 NVRAM_set_lword(nvram, 0x4C, initrd_size);
408 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
410 NVRAM_set_word(nvram, 0x54, width);
411 NVRAM_set_word(nvram, 0x56, height);
412 NVRAM_set_word(nvram, 0x58, depth);
413 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
414 NVRAM_set_word(nvram, 0xFC, crc);