2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 #define BIOS_FILENAME "ppc405_rom.bin"
38 #define BIOS_SIZE (2048 * 1024)
40 #define KERNEL_LOAD_ADDR 0x00000000
41 #define INITRD_LOAD_ADDR 0x01800000
43 #define USE_FLASH_BIOS
45 #define DEBUG_BOARD_INIT
47 /*****************************************************************************/
48 /* PPC405EP reference board (IBM) */
49 /* Standalone board with:
51 * - SDRAM (0x00000000)
52 * - Flash (0xFFF80000)
54 * - NVRAM (0xF0000000)
57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
58 struct ref405ep_fpga_t {
64 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
66 ref405ep_fpga_t *fpga;
86 static void ref405ep_fpga_writeb (void *opaque,
87 target_phys_addr_t addr, uint32_t value)
89 ref405ep_fpga_t *fpga;
105 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
109 ret = ref405ep_fpga_readb(opaque, addr) << 8;
110 ret |= ref405ep_fpga_readb(opaque, addr + 1);
115 static void ref405ep_fpga_writew (void *opaque,
116 target_phys_addr_t addr, uint32_t value)
118 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
119 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
122 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
126 ret = ref405ep_fpga_readb(opaque, addr) << 24;
127 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
128 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
129 ret |= ref405ep_fpga_readb(opaque, addr + 3);
134 static void ref405ep_fpga_writel (void *opaque,
135 target_phys_addr_t addr, uint32_t value)
137 ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
138 ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
139 ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
140 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
143 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
144 &ref405ep_fpga_readb,
145 &ref405ep_fpga_readw,
146 &ref405ep_fpga_readl,
149 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
150 &ref405ep_fpga_writeb,
151 &ref405ep_fpga_writew,
152 &ref405ep_fpga_writel,
155 static void ref405ep_fpga_reset (void *opaque)
157 ref405ep_fpga_t *fpga;
164 static void ref405ep_fpga_init (uint32_t base)
166 ref405ep_fpga_t *fpga;
169 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
172 fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
173 ref405ep_fpga_write, fpga);
174 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
175 ref405ep_fpga_reset(fpga);
176 qemu_register_reset(&ref405ep_fpga_reset, fpga);
180 static void ref405ep_init (int ram_size, int vga_ram_size,
181 const char *boot_device, DisplayState *ds,
182 const char *kernel_filename,
183 const char *kernel_cmdline,
184 const char *initrd_filename,
185 const char *cpu_model)
191 ram_addr_t sram_offset, bios_offset, bdloc;
192 target_phys_addr_t ram_bases[2], ram_sizes[2];
193 target_ulong sram_size, bios_size;
195 //static int phy_addr = 1;
196 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
198 int fl_idx, fl_sectors, len;
199 int ppc_boot_device = boot_device[0];
203 ram_bases[0] = 0x00000000;
204 ram_sizes[0] = 0x08000000;
205 ram_bases[1] = 0x00000000;
206 ram_sizes[1] = 0x00000000;
207 ram_size = 128 * 1024 * 1024;
208 #ifdef DEBUG_BOARD_INIT
209 printf("%s: register cpu\n", __func__);
211 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
212 kernel_filename == NULL ? 0 : 1);
214 #ifdef DEBUG_BOARD_INIT
215 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
217 sram_size = 512 * 1024;
218 cpu_register_physical_memory(0xFFF00000, sram_size,
219 sram_offset | IO_MEM_RAM);
220 /* allocate and load BIOS */
221 #ifdef DEBUG_BOARD_INIT
222 printf("%s: register BIOS\n", __func__);
224 bios_offset = sram_offset + sram_size;
226 #ifdef USE_FLASH_BIOS
227 index = drive_get_index(IF_PFLASH, 0, fl_idx);
229 bios_size = bdrv_getlength(drives_table[index].bdrv);
230 fl_sectors = (bios_size + 65535) >> 16;
231 #ifdef DEBUG_BOARD_INIT
232 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
233 " addr " ADDRX " '%s' %d\n",
234 fl_idx, bios_size, bios_offset, -bios_size,
235 bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
237 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
238 drives_table[index].bdrv, 65536, fl_sectors, 1,
239 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
244 #ifdef DEBUG_BOARD_INIT
245 printf("Load BIOS from file\n");
247 if (bios_name == NULL)
248 bios_name = BIOS_FILENAME;
249 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
250 bios_size = load_image(buf, phys_ram_base + bios_offset);
251 if (bios_size < 0 || bios_size > BIOS_SIZE) {
252 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
255 bios_size = (bios_size + 0xfff) & ~0xfff;
256 cpu_register_physical_memory((uint32_t)(-bios_size),
257 bios_size, bios_offset | IO_MEM_ROM);
259 bios_offset += bios_size;
261 #ifdef DEBUG_BOARD_INIT
262 printf("%s: register FPGA\n", __func__);
264 ref405ep_fpga_init(0xF0300000);
266 #ifdef DEBUG_BOARD_INIT
267 printf("%s: register NVRAM\n", __func__);
269 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
271 linux_boot = (kernel_filename != NULL);
273 #ifdef DEBUG_BOARD_INIT
274 printf("%s: load kernel\n", __func__);
276 memset(&bd, 0, sizeof(bd));
277 bd.bi_memstart = 0x00000000;
278 bd.bi_memsize = ram_size;
279 bd.bi_flashstart = -bios_size;
280 bd.bi_flashsize = -bios_size;
281 bd.bi_flashoffset = 0;
282 bd.bi_sramstart = 0xFFF00000;
283 bd.bi_sramsize = sram_size;
285 bd.bi_intfreq = 133333333;
286 bd.bi_busfreq = 33333333;
287 bd.bi_baudrate = 115200;
288 bd.bi_s_version[0] = 'Q';
289 bd.bi_s_version[1] = 'M';
290 bd.bi_s_version[2] = 'U';
291 bd.bi_s_version[3] = '\0';
292 bd.bi_r_version[0] = 'Q';
293 bd.bi_r_version[1] = 'E';
294 bd.bi_r_version[2] = 'M';
295 bd.bi_r_version[3] = 'U';
296 bd.bi_r_version[4] = '\0';
297 bd.bi_procfreq = 133333333;
298 bd.bi_plb_busfreq = 33333333;
299 bd.bi_pci_busfreq = 33333333;
300 bd.bi_opbfreq = 33333333;
301 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
303 kernel_base = KERNEL_LOAD_ADDR;
304 /* now we can load the kernel */
305 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
306 if (kernel_size < 0) {
307 fprintf(stderr, "qemu: could not load kernel '%s'\n",
311 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
312 " %02x %02x %02x %02x\n", kernel_size, kernel_base,
313 *(char *)(phys_ram_base + kernel_base),
314 *(char *)(phys_ram_base + kernel_base + 1),
315 *(char *)(phys_ram_base + kernel_base + 2),
316 *(char *)(phys_ram_base + kernel_base + 3));
318 if (initrd_filename) {
319 initrd_base = INITRD_LOAD_ADDR;
320 initrd_size = load_image(initrd_filename,
321 phys_ram_base + initrd_base);
322 if (initrd_size < 0) {
323 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
331 env->gpr[4] = initrd_base;
332 env->gpr[5] = initrd_size;
333 ppc_boot_device = 'm';
334 if (kernel_cmdline != NULL) {
335 len = strlen(kernel_cmdline);
336 bdloc -= ((len + 255) & ~255);
337 memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
339 env->gpr[7] = bdloc + len;
344 env->nip = KERNEL_LOAD_ADDR;
352 #ifdef DEBUG_BOARD_INIT
353 printf("%s: Done\n", __func__);
355 printf("bdloc %016lx %s\n",
356 (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
359 QEMUMachine ref405ep_machine = {
365 /*****************************************************************************/
366 /* AMCC Taihu evaluation board */
367 /* - PowerPC 405EP processor
368 * - SDRAM 128 MB at 0x00000000
369 * - Boot flash 2 MB at 0xFFE00000
370 * - Application flash 32 MB at 0xFC000000
373 * - 1 USB 1.1 device 0x50000000
374 * - 1 LCD display 0x50100000
375 * - 1 CPLD 0x50100000
377 * - 1 I2C thermal sensor
379 * - bit-bang SPI port using GPIOs
380 * - 1 EBC interface connector 0 0x50200000
381 * - 1 cardbus controller + expansion slot.
382 * - 1 PCI expansion slot.
384 typedef struct taihu_cpld_t taihu_cpld_t;
385 struct taihu_cpld_t {
391 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
413 static void taihu_cpld_writeb (void *opaque,
414 target_phys_addr_t addr, uint32_t value)
432 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
436 ret = taihu_cpld_readb(opaque, addr) << 8;
437 ret |= taihu_cpld_readb(opaque, addr + 1);
442 static void taihu_cpld_writew (void *opaque,
443 target_phys_addr_t addr, uint32_t value)
445 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
446 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
449 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
453 ret = taihu_cpld_readb(opaque, addr) << 24;
454 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
455 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
456 ret |= taihu_cpld_readb(opaque, addr + 3);
461 static void taihu_cpld_writel (void *opaque,
462 target_phys_addr_t addr, uint32_t value)
464 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
465 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
466 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
467 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
470 static CPUReadMemoryFunc *taihu_cpld_read[] = {
476 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
482 static void taihu_cpld_reset (void *opaque)
491 static void taihu_cpld_init (uint32_t base)
496 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
499 cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
500 taihu_cpld_write, cpld);
501 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
502 taihu_cpld_reset(cpld);
503 qemu_register_reset(&taihu_cpld_reset, cpld);
507 static void taihu_405ep_init(int ram_size, int vga_ram_size,
508 const char *boot_device, DisplayState *ds,
509 const char *kernel_filename,
510 const char *kernel_cmdline,
511 const char *initrd_filename,
512 const char *cpu_model)
517 ram_addr_t bios_offset;
518 target_phys_addr_t ram_bases[2], ram_sizes[2];
519 target_ulong bios_size;
520 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
522 int fl_idx, fl_sectors;
523 int ppc_boot_device = boot_device[0];
526 /* RAM is soldered to the board so the size cannot be changed */
527 ram_bases[0] = 0x00000000;
528 ram_sizes[0] = 0x04000000;
529 ram_bases[1] = 0x04000000;
530 ram_sizes[1] = 0x04000000;
531 #ifdef DEBUG_BOARD_INIT
532 printf("%s: register cpu\n", __func__);
534 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
535 kernel_filename == NULL ? 0 : 1);
536 /* allocate and load BIOS */
537 #ifdef DEBUG_BOARD_INIT
538 printf("%s: register BIOS\n", __func__);
541 #if defined(USE_FLASH_BIOS)
542 index = drive_get_index(IF_PFLASH, 0, fl_idx);
544 bios_size = bdrv_getlength(drives_table[index].bdrv);
545 /* XXX: should check that size is 2MB */
546 // bios_size = 2 * 1024 * 1024;
547 fl_sectors = (bios_size + 65535) >> 16;
548 #ifdef DEBUG_BOARD_INIT
549 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
550 " addr " ADDRX " '%s' %d\n",
551 fl_idx, bios_size, bios_offset, -bios_size,
552 bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
554 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
555 drives_table[index].bdrv, 65536, fl_sectors, 1,
556 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
561 #ifdef DEBUG_BOARD_INIT
562 printf("Load BIOS from file\n");
564 if (bios_name == NULL)
565 bios_name = BIOS_FILENAME;
566 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
567 bios_size = load_image(buf, phys_ram_base + bios_offset);
568 if (bios_size < 0 || bios_size > BIOS_SIZE) {
569 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
572 bios_size = (bios_size + 0xfff) & ~0xfff;
573 cpu_register_physical_memory((uint32_t)(-bios_size),
574 bios_size, bios_offset | IO_MEM_ROM);
576 bios_offset += bios_size;
577 /* Register Linux flash */
578 index = drive_get_index(IF_PFLASH, 0, fl_idx);
580 bios_size = bdrv_getlength(drives_table[index].bdrv);
581 /* XXX: should check that size is 32MB */
582 bios_size = 32 * 1024 * 1024;
583 fl_sectors = (bios_size + 65535) >> 16;
584 #ifdef DEBUG_BOARD_INIT
585 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
586 " addr " ADDRX " '%s'\n",
587 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
588 bdrv_get_device_name(drives_table[index].bdrv));
590 pflash_cfi02_register(0xfc000000, bios_offset,
591 drives_table[index].bdrv, 65536, fl_sectors, 1,
592 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
595 /* Register CLPD & LCD display */
596 #ifdef DEBUG_BOARD_INIT
597 printf("%s: register CPLD\n", __func__);
599 taihu_cpld_init(0x50100000);
601 linux_boot = (kernel_filename != NULL);
603 #ifdef DEBUG_BOARD_INIT
604 printf("%s: load kernel\n", __func__);
606 kernel_base = KERNEL_LOAD_ADDR;
607 /* now we can load the kernel */
608 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
609 if (kernel_size < 0) {
610 fprintf(stderr, "qemu: could not load kernel '%s'\n",
615 if (initrd_filename) {
616 initrd_base = INITRD_LOAD_ADDR;
617 initrd_size = load_image(initrd_filename,
618 phys_ram_base + initrd_base);
619 if (initrd_size < 0) {
621 "qemu: could not load initial ram disk '%s'\n",
629 ppc_boot_device = 'm';
636 #ifdef DEBUG_BOARD_INIT
637 printf("%s: Done\n", __func__);
641 QEMUMachine taihu_machine = {