2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define BIOS_FILENAME "ppc405_rom.bin"
32 #define BIOS_SIZE (2048 * 1024)
34 #define KERNEL_LOAD_ADDR 0x00000000
35 #define INITRD_LOAD_ADDR 0x01800000
37 #define USE_FLASH_BIOS
39 #define DEBUG_BOARD_INIT
41 /*****************************************************************************/
42 /* PPC405EP reference board (IBM) */
43 /* Standalone board with:
45 * - SDRAM (0x00000000)
46 * - Flash (0xFFF80000)
48 * - NVRAM (0xF0000000)
51 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
52 struct ref405ep_fpga_t {
58 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
60 ref405ep_fpga_t *fpga;
80 static void ref405ep_fpga_writeb (void *opaque,
81 target_phys_addr_t addr, uint32_t value)
83 ref405ep_fpga_t *fpga;
99 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
103 ret = ref405ep_fpga_readb(opaque, addr) << 8;
104 ret |= ref405ep_fpga_readb(opaque, addr + 1);
109 static void ref405ep_fpga_writew (void *opaque,
110 target_phys_addr_t addr, uint32_t value)
112 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
113 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
116 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
120 ret = ref405ep_fpga_readb(opaque, addr) << 24;
121 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
122 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
123 ret |= ref405ep_fpga_readb(opaque, addr + 3);
128 static void ref405ep_fpga_writel (void *opaque,
129 target_phys_addr_t addr, uint32_t value)
131 ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
132 ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
133 ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
134 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
137 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
138 &ref405ep_fpga_readb,
139 &ref405ep_fpga_readw,
140 &ref405ep_fpga_readl,
143 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
144 &ref405ep_fpga_writeb,
145 &ref405ep_fpga_writew,
146 &ref405ep_fpga_writel,
149 static void ref405ep_fpga_reset (void *opaque)
151 ref405ep_fpga_t *fpga;
158 static void ref405ep_fpga_init (uint32_t base)
160 ref405ep_fpga_t *fpga;
163 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
166 fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
167 ref405ep_fpga_write, fpga);
168 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
169 ref405ep_fpga_reset(fpga);
170 qemu_register_reset(&ref405ep_fpga_reset, fpga);
174 static void ref405ep_init (int ram_size, int vga_ram_size,
175 const char *boot_device, DisplayState *ds,
176 const char **fd_filename, int snapshot,
177 const char *kernel_filename,
178 const char *kernel_cmdline,
179 const char *initrd_filename,
180 const char *cpu_model)
186 ram_addr_t sram_offset, bios_offset, bdloc;
187 target_phys_addr_t ram_bases[2], ram_sizes[2];
188 target_ulong sram_size, bios_size;
190 //static int phy_addr = 1;
191 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
193 int fl_idx, fl_sectors, len;
194 int ppc_boot_device = boot_device[0];
197 ram_bases[0] = 0x00000000;
198 ram_sizes[0] = 0x08000000;
199 ram_bases[1] = 0x00000000;
200 ram_sizes[1] = 0x00000000;
201 ram_size = 128 * 1024 * 1024;
202 #ifdef DEBUG_BOARD_INIT
203 printf("%s: register cpu\n", __func__);
205 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
206 kernel_filename == NULL ? 0 : 1);
208 #ifdef DEBUG_BOARD_INIT
209 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
211 sram_size = 512 * 1024;
212 cpu_register_physical_memory(0xFFF00000, sram_size,
213 sram_offset | IO_MEM_RAM);
214 /* allocate and load BIOS */
215 #ifdef DEBUG_BOARD_INIT
216 printf("%s: register BIOS\n", __func__);
218 bios_offset = sram_offset + sram_size;
220 #ifdef USE_FLASH_BIOS
221 if (pflash_table[fl_idx] != NULL) {
222 bios_size = bdrv_getlength(pflash_table[fl_idx]);
223 fl_sectors = (bios_size + 65535) >> 16;
224 #ifdef DEBUG_BOARD_INIT
225 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
226 " addr " ADDRX " '%s' %d\n",
227 fl_idx, bios_size, bios_offset, -bios_size,
228 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
230 pflash_register((uint32_t)(-bios_size), bios_offset,
231 pflash_table[fl_idx], 65536, fl_sectors, 2,
232 0x0001, 0x22DA, 0x0000, 0x0000);
237 #ifdef DEBUG_BOARD_INIT
238 printf("Load BIOS from file\n");
240 if (bios_name == NULL)
241 bios_name = BIOS_FILENAME;
242 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
243 bios_size = load_image(buf, phys_ram_base + bios_offset);
244 if (bios_size < 0 || bios_size > BIOS_SIZE) {
245 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
248 bios_size = (bios_size + 0xfff) & ~0xfff;
249 cpu_register_physical_memory((uint32_t)(-bios_size),
250 bios_size, bios_offset | IO_MEM_ROM);
252 bios_offset += bios_size;
254 #ifdef DEBUG_BOARD_INIT
255 printf("%s: register FPGA\n", __func__);
257 ref405ep_fpga_init(0xF0300000);
259 #ifdef DEBUG_BOARD_INIT
260 printf("%s: register NVRAM\n", __func__);
262 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
264 linux_boot = (kernel_filename != NULL);
266 #ifdef DEBUG_BOARD_INIT
267 printf("%s: load kernel\n", __func__);
269 memset(&bd, 0, sizeof(bd));
270 bd.bi_memstart = 0x00000000;
271 bd.bi_memsize = ram_size;
272 bd.bi_flashstart = -bios_size;
273 bd.bi_flashsize = -bios_size;
274 bd.bi_flashoffset = 0;
275 bd.bi_sramstart = 0xFFF00000;
276 bd.bi_sramsize = sram_size;
278 bd.bi_intfreq = 133333333;
279 bd.bi_busfreq = 33333333;
280 bd.bi_baudrate = 115200;
281 bd.bi_s_version[0] = 'Q';
282 bd.bi_s_version[1] = 'M';
283 bd.bi_s_version[2] = 'U';
284 bd.bi_s_version[3] = '\0';
285 bd.bi_r_version[0] = 'Q';
286 bd.bi_r_version[1] = 'E';
287 bd.bi_r_version[2] = 'M';
288 bd.bi_r_version[3] = 'U';
289 bd.bi_r_version[4] = '\0';
290 bd.bi_procfreq = 133333333;
291 bd.bi_plb_busfreq = 33333333;
292 bd.bi_pci_busfreq = 33333333;
293 bd.bi_opbfreq = 33333333;
294 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
296 kernel_base = KERNEL_LOAD_ADDR;
297 /* now we can load the kernel */
298 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
299 if (kernel_size < 0) {
300 fprintf(stderr, "qemu: could not load kernel '%s'\n",
304 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
305 " %02x %02x %02x %02x\n", kernel_size, kernel_base,
306 *(char *)(phys_ram_base + kernel_base),
307 *(char *)(phys_ram_base + kernel_base + 1),
308 *(char *)(phys_ram_base + kernel_base + 2),
309 *(char *)(phys_ram_base + kernel_base + 3));
311 if (initrd_filename) {
312 initrd_base = INITRD_LOAD_ADDR;
313 initrd_size = load_image(initrd_filename,
314 phys_ram_base + initrd_base);
315 if (initrd_size < 0) {
316 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
324 env->gpr[4] = initrd_base;
325 env->gpr[5] = initrd_size;
326 ppc_boot_device = 'm';
327 if (kernel_cmdline != NULL) {
328 len = strlen(kernel_cmdline);
329 bdloc -= ((len + 255) & ~255);
330 memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
332 env->gpr[7] = bdloc + len;
337 env->nip = KERNEL_LOAD_ADDR;
345 #ifdef DEBUG_BOARD_INIT
346 printf("%s: Done\n", __func__);
348 printf("bdloc %016lx %s\n",
349 (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
352 QEMUMachine ref405ep_machine = {
358 /*****************************************************************************/
359 /* AMCC Taihu evaluation board */
360 /* - PowerPC 405EP processor
361 * - SDRAM 128 MB at 0x00000000
362 * - Boot flash 2 MB at 0xFFE00000
363 * - Application flash 32 MB at 0xFC000000
366 * - 1 USB 1.1 device 0x50000000
367 * - 1 LCD display 0x50100000
368 * - 1 CPLD 0x50100000
370 * - 1 I2C thermal sensor
372 * - bit-bang SPI port using GPIOs
373 * - 1 EBC interface connector 0 0x50200000
374 * - 1 cardbus controller + expansion slot.
375 * - 1 PCI expansion slot.
377 typedef struct taihu_cpld_t taihu_cpld_t;
378 struct taihu_cpld_t {
384 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
406 static void taihu_cpld_writeb (void *opaque,
407 target_phys_addr_t addr, uint32_t value)
425 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
429 ret = taihu_cpld_readb(opaque, addr) << 8;
430 ret |= taihu_cpld_readb(opaque, addr + 1);
435 static void taihu_cpld_writew (void *opaque,
436 target_phys_addr_t addr, uint32_t value)
438 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
439 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
442 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
446 ret = taihu_cpld_readb(opaque, addr) << 24;
447 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
448 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
449 ret |= taihu_cpld_readb(opaque, addr + 3);
454 static void taihu_cpld_writel (void *opaque,
455 target_phys_addr_t addr, uint32_t value)
457 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
458 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
459 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
460 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
463 static CPUReadMemoryFunc *taihu_cpld_read[] = {
469 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
475 static void taihu_cpld_reset (void *opaque)
484 static void taihu_cpld_init (uint32_t base)
489 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
492 cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
493 taihu_cpld_write, cpld);
494 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
495 taihu_cpld_reset(cpld);
496 qemu_register_reset(&taihu_cpld_reset, cpld);
500 static void taihu_405ep_init(int ram_size, int vga_ram_size,
501 const char *boot_device, DisplayState *ds,
502 const char **fd_filename, int snapshot,
503 const char *kernel_filename,
504 const char *kernel_cmdline,
505 const char *initrd_filename,
506 const char *cpu_model)
511 ram_addr_t bios_offset;
512 target_phys_addr_t ram_bases[2], ram_sizes[2];
513 target_ulong bios_size;
514 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
516 int fl_idx, fl_sectors;
517 int ppc_boot_device = boot_device[0];
519 /* RAM is soldered to the board so the size cannot be changed */
520 ram_bases[0] = 0x00000000;
521 ram_sizes[0] = 0x04000000;
522 ram_bases[1] = 0x04000000;
523 ram_sizes[1] = 0x04000000;
524 #ifdef DEBUG_BOARD_INIT
525 printf("%s: register cpu\n", __func__);
527 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
528 kernel_filename == NULL ? 0 : 1);
529 /* allocate and load BIOS */
530 #ifdef DEBUG_BOARD_INIT
531 printf("%s: register BIOS\n", __func__);
534 #if defined(USE_FLASH_BIOS)
535 if (pflash_table[fl_idx] != NULL) {
536 bios_size = bdrv_getlength(pflash_table[fl_idx]);
537 /* XXX: should check that size is 2MB */
538 // bios_size = 2 * 1024 * 1024;
539 fl_sectors = (bios_size + 65535) >> 16;
540 #ifdef DEBUG_BOARD_INIT
541 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
542 " addr " ADDRX " '%s' %d\n",
543 fl_idx, bios_size, bios_offset, -bios_size,
544 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
546 pflash_register((uint32_t)(-bios_size), bios_offset,
547 pflash_table[fl_idx], 65536, fl_sectors, 4,
548 0x0001, 0x22DA, 0x0000, 0x0000);
553 #ifdef DEBUG_BOARD_INIT
554 printf("Load BIOS from file\n");
556 if (bios_name == NULL)
557 bios_name = BIOS_FILENAME;
558 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
559 bios_size = load_image(buf, phys_ram_base + bios_offset);
560 if (bios_size < 0 || bios_size > BIOS_SIZE) {
561 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
564 bios_size = (bios_size + 0xfff) & ~0xfff;
565 cpu_register_physical_memory((uint32_t)(-bios_size),
566 bios_size, bios_offset | IO_MEM_ROM);
568 bios_offset += bios_size;
569 /* Register Linux flash */
570 if (pflash_table[fl_idx] != NULL) {
571 bios_size = bdrv_getlength(pflash_table[fl_idx]);
572 /* XXX: should check that size is 32MB */
573 bios_size = 32 * 1024 * 1024;
574 fl_sectors = (bios_size + 65535) >> 16;
575 #ifdef DEBUG_BOARD_INIT
576 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
577 " addr " ADDRX " '%s'\n",
578 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
579 bdrv_get_device_name(pflash_table[fl_idx]));
581 pflash_register(0xfc000000, bios_offset, pflash_table[fl_idx],
582 65536, fl_sectors, 4,
583 0x0001, 0x22DA, 0x0000, 0x0000);
586 /* Register CLPD & LCD display */
587 #ifdef DEBUG_BOARD_INIT
588 printf("%s: register CPLD\n", __func__);
590 taihu_cpld_init(0x50100000);
592 linux_boot = (kernel_filename != NULL);
594 #ifdef DEBUG_BOARD_INIT
595 printf("%s: load kernel\n", __func__);
597 kernel_base = KERNEL_LOAD_ADDR;
598 /* now we can load the kernel */
599 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
600 if (kernel_size < 0) {
601 fprintf(stderr, "qemu: could not load kernel '%s'\n",
606 if (initrd_filename) {
607 initrd_base = INITRD_LOAD_ADDR;
608 initrd_size = load_image(initrd_filename,
609 phys_ram_base + initrd_base);
610 if (initrd_size < 0) {
612 "qemu: could not load initial ram disk '%s'\n",
620 ppc_boot_device = 'm';
627 #ifdef DEBUG_BOARD_INIT
628 printf("%s: Done\n", __func__);
632 QEMUMachine taihu_machine = {