2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 #define BIOS_FILENAME "ppc405_rom.bin"
38 #define BIOS_SIZE (2048 * 1024)
40 #define KERNEL_LOAD_ADDR 0x00000000
41 #define INITRD_LOAD_ADDR 0x01800000
43 #define USE_FLASH_BIOS
45 #define DEBUG_BOARD_INIT
47 /*****************************************************************************/
48 /* PPC405EP reference board (IBM) */
49 /* Standalone board with:
51 * - SDRAM (0x00000000)
52 * - Flash (0xFFF80000)
54 * - NVRAM (0xF0000000)
57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
58 struct ref405ep_fpga_t {
64 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
66 ref405ep_fpga_t *fpga;
86 static void ref405ep_fpga_writeb (void *opaque,
87 target_phys_addr_t addr, uint32_t value)
89 ref405ep_fpga_t *fpga;
105 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
109 ret = ref405ep_fpga_readb(opaque, addr) << 8;
110 ret |= ref405ep_fpga_readb(opaque, addr + 1);
115 static void ref405ep_fpga_writew (void *opaque,
116 target_phys_addr_t addr, uint32_t value)
118 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
119 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
122 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
126 ret = ref405ep_fpga_readb(opaque, addr) << 24;
127 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
128 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
129 ret |= ref405ep_fpga_readb(opaque, addr + 3);
134 static void ref405ep_fpga_writel (void *opaque,
135 target_phys_addr_t addr, uint32_t value)
137 ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
138 ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
139 ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
140 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
143 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
144 &ref405ep_fpga_readb,
145 &ref405ep_fpga_readw,
146 &ref405ep_fpga_readl,
149 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
150 &ref405ep_fpga_writeb,
151 &ref405ep_fpga_writew,
152 &ref405ep_fpga_writel,
155 static void ref405ep_fpga_reset (void *opaque)
157 ref405ep_fpga_t *fpga;
164 static void ref405ep_fpga_init (uint32_t base)
166 ref405ep_fpga_t *fpga;
169 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
172 fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
173 ref405ep_fpga_write, fpga);
174 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
175 ref405ep_fpga_reset(fpga);
176 qemu_register_reset(&ref405ep_fpga_reset, fpga);
180 static void ref405ep_init (int ram_size, int vga_ram_size,
181 const char *boot_device, DisplayState *ds,
182 const char **fd_filename, int snapshot,
183 const char *kernel_filename,
184 const char *kernel_cmdline,
185 const char *initrd_filename,
186 const char *cpu_model)
192 ram_addr_t sram_offset, bios_offset, bdloc;
193 target_phys_addr_t ram_bases[2], ram_sizes[2];
194 target_ulong sram_size, bios_size;
196 //static int phy_addr = 1;
197 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
199 int fl_idx, fl_sectors, len;
200 int ppc_boot_device = boot_device[0];
203 ram_bases[0] = 0x00000000;
204 ram_sizes[0] = 0x08000000;
205 ram_bases[1] = 0x00000000;
206 ram_sizes[1] = 0x00000000;
207 ram_size = 128 * 1024 * 1024;
208 #ifdef DEBUG_BOARD_INIT
209 printf("%s: register cpu\n", __func__);
211 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
212 kernel_filename == NULL ? 0 : 1);
214 #ifdef DEBUG_BOARD_INIT
215 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
217 sram_size = 512 * 1024;
218 cpu_register_physical_memory(0xFFF00000, sram_size,
219 sram_offset | IO_MEM_RAM);
220 /* allocate and load BIOS */
221 #ifdef DEBUG_BOARD_INIT
222 printf("%s: register BIOS\n", __func__);
224 bios_offset = sram_offset + sram_size;
226 #ifdef USE_FLASH_BIOS
227 if (pflash_table[fl_idx] != NULL) {
228 bios_size = bdrv_getlength(pflash_table[fl_idx]);
229 fl_sectors = (bios_size + 65535) >> 16;
230 #ifdef DEBUG_BOARD_INIT
231 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
232 " addr " ADDRX " '%s' %d\n",
233 fl_idx, bios_size, bios_offset, -bios_size,
234 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
236 pflash_register((uint32_t)(-bios_size), bios_offset,
237 pflash_table[fl_idx], 65536, fl_sectors, 2,
238 0x0001, 0x22DA, 0x0000, 0x0000);
243 #ifdef DEBUG_BOARD_INIT
244 printf("Load BIOS from file\n");
246 if (bios_name == NULL)
247 bios_name = BIOS_FILENAME;
248 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
249 bios_size = load_image(buf, phys_ram_base + bios_offset);
250 if (bios_size < 0 || bios_size > BIOS_SIZE) {
251 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
254 bios_size = (bios_size + 0xfff) & ~0xfff;
255 cpu_register_physical_memory((uint32_t)(-bios_size),
256 bios_size, bios_offset | IO_MEM_ROM);
258 bios_offset += bios_size;
260 #ifdef DEBUG_BOARD_INIT
261 printf("%s: register FPGA\n", __func__);
263 ref405ep_fpga_init(0xF0300000);
265 #ifdef DEBUG_BOARD_INIT
266 printf("%s: register NVRAM\n", __func__);
268 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
270 linux_boot = (kernel_filename != NULL);
272 #ifdef DEBUG_BOARD_INIT
273 printf("%s: load kernel\n", __func__);
275 memset(&bd, 0, sizeof(bd));
276 bd.bi_memstart = 0x00000000;
277 bd.bi_memsize = ram_size;
278 bd.bi_flashstart = -bios_size;
279 bd.bi_flashsize = -bios_size;
280 bd.bi_flashoffset = 0;
281 bd.bi_sramstart = 0xFFF00000;
282 bd.bi_sramsize = sram_size;
284 bd.bi_intfreq = 133333333;
285 bd.bi_busfreq = 33333333;
286 bd.bi_baudrate = 115200;
287 bd.bi_s_version[0] = 'Q';
288 bd.bi_s_version[1] = 'M';
289 bd.bi_s_version[2] = 'U';
290 bd.bi_s_version[3] = '\0';
291 bd.bi_r_version[0] = 'Q';
292 bd.bi_r_version[1] = 'E';
293 bd.bi_r_version[2] = 'M';
294 bd.bi_r_version[3] = 'U';
295 bd.bi_r_version[4] = '\0';
296 bd.bi_procfreq = 133333333;
297 bd.bi_plb_busfreq = 33333333;
298 bd.bi_pci_busfreq = 33333333;
299 bd.bi_opbfreq = 33333333;
300 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
302 kernel_base = KERNEL_LOAD_ADDR;
303 /* now we can load the kernel */
304 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
305 if (kernel_size < 0) {
306 fprintf(stderr, "qemu: could not load kernel '%s'\n",
310 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
311 " %02x %02x %02x %02x\n", kernel_size, kernel_base,
312 *(char *)(phys_ram_base + kernel_base),
313 *(char *)(phys_ram_base + kernel_base + 1),
314 *(char *)(phys_ram_base + kernel_base + 2),
315 *(char *)(phys_ram_base + kernel_base + 3));
317 if (initrd_filename) {
318 initrd_base = INITRD_LOAD_ADDR;
319 initrd_size = load_image(initrd_filename,
320 phys_ram_base + initrd_base);
321 if (initrd_size < 0) {
322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
330 env->gpr[4] = initrd_base;
331 env->gpr[5] = initrd_size;
332 ppc_boot_device = 'm';
333 if (kernel_cmdline != NULL) {
334 len = strlen(kernel_cmdline);
335 bdloc -= ((len + 255) & ~255);
336 memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
338 env->gpr[7] = bdloc + len;
343 env->nip = KERNEL_LOAD_ADDR;
351 #ifdef DEBUG_BOARD_INIT
352 printf("%s: Done\n", __func__);
354 printf("bdloc %016lx %s\n",
355 (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
358 QEMUMachine ref405ep_machine = {
364 /*****************************************************************************/
365 /* AMCC Taihu evaluation board */
366 /* - PowerPC 405EP processor
367 * - SDRAM 128 MB at 0x00000000
368 * - Boot flash 2 MB at 0xFFE00000
369 * - Application flash 32 MB at 0xFC000000
372 * - 1 USB 1.1 device 0x50000000
373 * - 1 LCD display 0x50100000
374 * - 1 CPLD 0x50100000
376 * - 1 I2C thermal sensor
378 * - bit-bang SPI port using GPIOs
379 * - 1 EBC interface connector 0 0x50200000
380 * - 1 cardbus controller + expansion slot.
381 * - 1 PCI expansion slot.
383 typedef struct taihu_cpld_t taihu_cpld_t;
384 struct taihu_cpld_t {
390 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
412 static void taihu_cpld_writeb (void *opaque,
413 target_phys_addr_t addr, uint32_t value)
431 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
435 ret = taihu_cpld_readb(opaque, addr) << 8;
436 ret |= taihu_cpld_readb(opaque, addr + 1);
441 static void taihu_cpld_writew (void *opaque,
442 target_phys_addr_t addr, uint32_t value)
444 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
445 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
448 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
452 ret = taihu_cpld_readb(opaque, addr) << 24;
453 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
454 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
455 ret |= taihu_cpld_readb(opaque, addr + 3);
460 static void taihu_cpld_writel (void *opaque,
461 target_phys_addr_t addr, uint32_t value)
463 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
464 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
465 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
466 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
469 static CPUReadMemoryFunc *taihu_cpld_read[] = {
475 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
481 static void taihu_cpld_reset (void *opaque)
490 static void taihu_cpld_init (uint32_t base)
495 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
498 cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
499 taihu_cpld_write, cpld);
500 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
501 taihu_cpld_reset(cpld);
502 qemu_register_reset(&taihu_cpld_reset, cpld);
506 static void taihu_405ep_init(int ram_size, int vga_ram_size,
507 const char *boot_device, DisplayState *ds,
508 const char **fd_filename, int snapshot,
509 const char *kernel_filename,
510 const char *kernel_cmdline,
511 const char *initrd_filename,
512 const char *cpu_model)
517 ram_addr_t bios_offset;
518 target_phys_addr_t ram_bases[2], ram_sizes[2];
519 target_ulong bios_size;
520 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
522 int fl_idx, fl_sectors;
523 int ppc_boot_device = boot_device[0];
525 /* RAM is soldered to the board so the size cannot be changed */
526 ram_bases[0] = 0x00000000;
527 ram_sizes[0] = 0x04000000;
528 ram_bases[1] = 0x04000000;
529 ram_sizes[1] = 0x04000000;
530 #ifdef DEBUG_BOARD_INIT
531 printf("%s: register cpu\n", __func__);
533 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
534 kernel_filename == NULL ? 0 : 1);
535 /* allocate and load BIOS */
536 #ifdef DEBUG_BOARD_INIT
537 printf("%s: register BIOS\n", __func__);
540 #if defined(USE_FLASH_BIOS)
541 if (pflash_table[fl_idx] != NULL) {
542 bios_size = bdrv_getlength(pflash_table[fl_idx]);
543 /* XXX: should check that size is 2MB */
544 // bios_size = 2 * 1024 * 1024;
545 fl_sectors = (bios_size + 65535) >> 16;
546 #ifdef DEBUG_BOARD_INIT
547 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
548 " addr " ADDRX " '%s' %d\n",
549 fl_idx, bios_size, bios_offset, -bios_size,
550 bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
552 pflash_register((uint32_t)(-bios_size), bios_offset,
553 pflash_table[fl_idx], 65536, fl_sectors, 4,
554 0x0001, 0x22DA, 0x0000, 0x0000);
559 #ifdef DEBUG_BOARD_INIT
560 printf("Load BIOS from file\n");
562 if (bios_name == NULL)
563 bios_name = BIOS_FILENAME;
564 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
565 bios_size = load_image(buf, phys_ram_base + bios_offset);
566 if (bios_size < 0 || bios_size > BIOS_SIZE) {
567 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
570 bios_size = (bios_size + 0xfff) & ~0xfff;
571 cpu_register_physical_memory((uint32_t)(-bios_size),
572 bios_size, bios_offset | IO_MEM_ROM);
574 bios_offset += bios_size;
575 /* Register Linux flash */
576 if (pflash_table[fl_idx] != NULL) {
577 bios_size = bdrv_getlength(pflash_table[fl_idx]);
578 /* XXX: should check that size is 32MB */
579 bios_size = 32 * 1024 * 1024;
580 fl_sectors = (bios_size + 65535) >> 16;
581 #ifdef DEBUG_BOARD_INIT
582 printf("Register parallel flash %d size " ADDRX " at offset %08lx "
583 " addr " ADDRX " '%s'\n",
584 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
585 bdrv_get_device_name(pflash_table[fl_idx]));
587 pflash_register(0xfc000000, bios_offset, pflash_table[fl_idx],
588 65536, fl_sectors, 4,
589 0x0001, 0x22DA, 0x0000, 0x0000);
592 /* Register CLPD & LCD display */
593 #ifdef DEBUG_BOARD_INIT
594 printf("%s: register CPLD\n", __func__);
596 taihu_cpld_init(0x50100000);
598 linux_boot = (kernel_filename != NULL);
600 #ifdef DEBUG_BOARD_INIT
601 printf("%s: load kernel\n", __func__);
603 kernel_base = KERNEL_LOAD_ADDR;
604 /* now we can load the kernel */
605 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
606 if (kernel_size < 0) {
607 fprintf(stderr, "qemu: could not load kernel '%s'\n",
612 if (initrd_filename) {
613 initrd_base = INITRD_LOAD_ADDR;
614 initrd_size = load_image(initrd_filename,
615 phys_ram_base + initrd_base);
616 if (initrd_size < 0) {
618 "qemu: could not load initial ram disk '%s'\n",
626 ppc_boot_device = 'm';
633 #ifdef DEBUG_BOARD_INIT
634 printf("%s: Done\n", __func__);
638 QEMUMachine taihu_machine = {