2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 //#define DEBUG_UNASSIGNED
36 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
38 # define LOG_UIC(...) do { } while (0)
41 /*****************************************************************************/
42 /* Generic PowerPC 4xx processor instanciation */
43 CPUState *ppc4xx_init (const char *cpu_model,
44 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
50 env = cpu_init(cpu_model);
52 fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
56 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
57 cpu_clk->opaque = env;
58 /* Set time-base frequency to sysclk */
59 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
61 ppc_dcr_init(env, NULL, NULL);
62 /* Register qemu callbacks */
63 qemu_register_reset(&cpu_ppc_reset, env);
68 /*****************************************************************************/
69 /* Fake device used to map multiple devices in a single memory page */
70 #define MMIO_AREA_BITS 8
71 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
72 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
73 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
74 struct ppc4xx_mmio_t {
75 target_phys_addr_t base;
76 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
77 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
78 void *opaque[MMIO_AREA_NB];
81 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
83 #ifdef DEBUG_UNASSIGNED
87 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
94 static void unassigned_mmio_writeb (void *opaque,
95 target_phys_addr_t addr, uint32_t val)
97 #ifdef DEBUG_UNASSIGNED
101 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
102 addr, val, mmio->base);
106 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
107 unassigned_mmio_readb,
108 unassigned_mmio_readb,
109 unassigned_mmio_readb,
112 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
113 unassigned_mmio_writeb,
114 unassigned_mmio_writeb,
115 unassigned_mmio_writeb,
118 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
119 target_phys_addr_t addr, int len)
121 CPUReadMemoryFunc **mem_read;
125 idx = MMIO_IDX(addr);
126 #if defined(DEBUG_MMIO)
127 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
128 mmio, len, addr, idx);
130 mem_read = mmio->mem_read[idx];
131 ret = (*mem_read[len])(mmio->opaque[idx], addr);
136 static void mmio_writelen (ppc4xx_mmio_t *mmio,
137 target_phys_addr_t addr, uint32_t value, int len)
139 CPUWriteMemoryFunc **mem_write;
142 idx = MMIO_IDX(addr);
143 #if defined(DEBUG_MMIO)
144 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
145 __func__, mmio, len, addr, idx, value);
147 mem_write = mmio->mem_write[idx];
148 (*mem_write[len])(mmio->opaque[idx], addr, value);
151 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
153 #if defined(DEBUG_MMIO)
154 printf("%s: addr " PADDRX "\n", __func__, addr);
157 return mmio_readlen(opaque, addr, 0);
160 static void mmio_writeb (void *opaque,
161 target_phys_addr_t addr, uint32_t value)
163 #if defined(DEBUG_MMIO)
164 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
166 mmio_writelen(opaque, addr, value, 0);
169 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
171 #if defined(DEBUG_MMIO)
172 printf("%s: addr " PADDRX "\n", __func__, addr);
175 return mmio_readlen(opaque, addr, 1);
178 static void mmio_writew (void *opaque,
179 target_phys_addr_t addr, uint32_t value)
181 #if defined(DEBUG_MMIO)
182 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
184 mmio_writelen(opaque, addr, value, 1);
187 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
189 #if defined(DEBUG_MMIO)
190 printf("%s: addr " PADDRX "\n", __func__, addr);
193 return mmio_readlen(opaque, addr, 2);
196 static void mmio_writel (void *opaque,
197 target_phys_addr_t addr, uint32_t value)
199 #if defined(DEBUG_MMIO)
200 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
202 mmio_writelen(opaque, addr, value, 2);
205 static CPUReadMemoryFunc *mmio_read[] = {
211 static CPUWriteMemoryFunc *mmio_write[] = {
217 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
218 target_phys_addr_t offset, uint32_t len,
219 CPUReadMemoryFunc **mem_read,
220 CPUWriteMemoryFunc **mem_write, void *opaque)
222 target_phys_addr_t end;
225 if ((offset + len) > TARGET_PAGE_SIZE)
227 idx = MMIO_IDX(offset);
228 end = offset + len - 1;
229 eidx = MMIO_IDX(end);
230 #if defined(DEBUG_MMIO)
231 printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
232 __func__, offset, len, end, idx, eidx);
234 for (; idx <= eidx; idx++) {
235 mmio->mem_read[idx] = mem_read;
236 mmio->mem_write[idx] = mem_write;
237 mmio->opaque[idx] = opaque;
243 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
248 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
251 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
252 #if defined(DEBUG_MMIO)
253 printf("%s: base " PADDRX " len %08x %d\n", __func__,
254 base, TARGET_PAGE_SIZE, mmio_memory);
256 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
257 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
258 unassigned_mmio_read, unassigned_mmio_write,
265 /*****************************************************************************/
266 /* "Universal" Interrupt controller */
280 #define UIC_MAX_IRQ 32
281 typedef struct ppcuic_t ppcuic_t;
285 uint32_t level; /* Remembers the state of level-triggered interrupts. */
286 uint32_t uicsr; /* Status register */
287 uint32_t uicer; /* Enable register */
288 uint32_t uiccr; /* Critical register */
289 uint32_t uicpr; /* Polarity register */
290 uint32_t uictr; /* Triggering register */
291 uint32_t uicvcr; /* Vector configuration register */
296 static void ppcuic_trigger_irq (ppcuic_t *uic)
299 int start, end, inc, i;
301 /* Trigger interrupt if any is pending */
302 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
303 cr = uic->uicsr & uic->uicer & uic->uiccr;
304 LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
305 " uiccr %08" PRIx32 "\n"
306 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
307 __func__, uic->uicsr, uic->uicer, uic->uiccr,
308 uic->uicsr & uic->uicer, ir, cr);
309 if (ir != 0x0000000) {
310 LOG_UIC("Raise UIC interrupt\n");
311 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
313 LOG_UIC("Lower UIC interrupt\n");
314 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
316 /* Trigger critical interrupt if any is pending and update vector */
317 if (cr != 0x0000000) {
318 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
319 if (uic->use_vectors) {
320 /* Compute critical IRQ vector */
321 if (uic->uicvcr & 1) {
330 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
331 for (i = start; i <= end; i += inc) {
333 uic->uicvr += (i - start) * 512 * inc;
338 LOG_UIC("Raise UIC critical interrupt - "
339 "vector %08" PRIx32 "\n", uic->uicvr);
341 LOG_UIC("Lower UIC critical interrupt\n");
342 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
343 uic->uicvr = 0x00000000;
347 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
353 mask = 1 << (31-irq_num);
354 LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
355 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
356 __func__, irq_num, level,
357 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
358 if (irq_num < 0 || irq_num > 31)
362 /* Update status register */
363 if (uic->uictr & mask) {
364 /* Edge sensitive interrupt */
368 /* Level sensitive interrupt */
377 LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
378 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
379 if (sr != uic->uicsr)
380 ppcuic_trigger_irq(uic);
383 static target_ulong dcr_read_uic (void *opaque, int dcrn)
389 dcrn -= uic->dcr_base;
408 ret = uic->uicsr & uic->uicer;
411 if (!uic->use_vectors)
416 if (!uic->use_vectors)
429 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
434 dcrn -= uic->dcr_base;
435 LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
439 uic->uicsr |= uic->level;
440 ppcuic_trigger_irq(uic);
444 ppcuic_trigger_irq(uic);
448 ppcuic_trigger_irq(uic);
452 ppcuic_trigger_irq(uic);
459 ppcuic_trigger_irq(uic);
466 uic->uicvcr = val & 0xFFFFFFFD;
467 ppcuic_trigger_irq(uic);
472 static void ppcuic_reset (void *opaque)
477 uic->uiccr = 0x00000000;
478 uic->uicer = 0x00000000;
479 uic->uicpr = 0x00000000;
480 uic->uicsr = 0x00000000;
481 uic->uictr = 0x00000000;
482 if (uic->use_vectors) {
483 uic->uicvcr = 0x00000000;
484 uic->uicvr = 0x0000000;
488 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
489 uint32_t dcr_base, int has_ssr, int has_vr)
494 uic = qemu_mallocz(sizeof(ppcuic_t));
496 uic->dcr_base = dcr_base;
499 uic->use_vectors = 1;
500 for (i = 0; i < DCR_UICMAX; i++) {
501 ppc_dcr_register(env, dcr_base + i, uic,
502 &dcr_read_uic, &dcr_write_uic);
504 qemu_register_reset(ppcuic_reset, uic);
508 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
511 /*****************************************************************************/
512 /* SDRAM controller */
513 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
514 struct ppc4xx_sdram_t {
517 target_phys_addr_t ram_bases[4];
518 target_phys_addr_t ram_sizes[4];
534 SDRAM0_CFGADDR = 0x010,
535 SDRAM0_CFGDATA = 0x011,
538 /* XXX: TOFIX: some patches have made this code become inconsistent:
539 * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
542 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
543 target_phys_addr_t ram_size)
548 case (4 * 1024 * 1024):
551 case (8 * 1024 * 1024):
554 case (16 * 1024 * 1024):
557 case (32 * 1024 * 1024):
560 case (64 * 1024 * 1024):
563 case (128 * 1024 * 1024):
566 case (256 * 1024 * 1024):
570 printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
573 bcr |= ram_base & 0xFF800000;
579 static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
581 return bcr & 0xFF800000;
584 static target_ulong sdram_size (uint32_t bcr)
589 sh = (bcr >> 17) & 0x7;
593 size = (4 * 1024 * 1024) << sh;
598 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
600 if (*bcrp & 0x00000001) {
603 printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
604 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
606 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
609 *bcrp = bcr & 0xFFDEE001;
610 if (enabled && (bcr & 0x00000001)) {
612 printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
613 __func__, sdram_base(bcr), sdram_size(bcr));
615 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
616 sdram_base(bcr) | IO_MEM_RAM);
620 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
624 for (i = 0; i < sdram->nbanks; i++) {
625 if (sdram->ram_sizes[i] != 0) {
626 sdram_set_bcr(&sdram->bcr[i],
627 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
630 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
635 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
639 for (i = 0; i < sdram->nbanks; i++) {
641 printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
642 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
644 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
645 sdram_size(sdram->bcr[i]),
650 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
652 ppc4xx_sdram_t *sdram;
661 switch (sdram->addr) {
662 case 0x00: /* SDRAM_BESR0 */
665 case 0x08: /* SDRAM_BESR1 */
668 case 0x10: /* SDRAM_BEAR */
671 case 0x20: /* SDRAM_CFG */
674 case 0x24: /* SDRAM_STATUS */
677 case 0x30: /* SDRAM_RTR */
680 case 0x34: /* SDRAM_PMIT */
683 case 0x40: /* SDRAM_B0CR */
686 case 0x44: /* SDRAM_B1CR */
689 case 0x48: /* SDRAM_B2CR */
692 case 0x4C: /* SDRAM_B3CR */
695 case 0x80: /* SDRAM_TR */
698 case 0x94: /* SDRAM_ECCCFG */
701 case 0x98: /* SDRAM_ECCESR */
710 /* Avoid gcc warning */
718 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
720 ppc4xx_sdram_t *sdram;
728 switch (sdram->addr) {
729 case 0x00: /* SDRAM_BESR0 */
730 sdram->besr0 &= ~val;
732 case 0x08: /* SDRAM_BESR1 */
733 sdram->besr1 &= ~val;
735 case 0x10: /* SDRAM_BEAR */
738 case 0x20: /* SDRAM_CFG */
740 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
742 printf("%s: enable SDRAM controller\n", __func__);
744 /* validate all RAM mappings */
745 sdram_map_bcr(sdram);
746 sdram->status &= ~0x80000000;
747 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
749 printf("%s: disable SDRAM controller\n", __func__);
751 /* invalidate all RAM mappings */
752 sdram_unmap_bcr(sdram);
753 sdram->status |= 0x80000000;
755 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
756 sdram->status |= 0x40000000;
757 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
758 sdram->status &= ~0x40000000;
761 case 0x24: /* SDRAM_STATUS */
762 /* Read-only register */
764 case 0x30: /* SDRAM_RTR */
765 sdram->rtr = val & 0x3FF80000;
767 case 0x34: /* SDRAM_PMIT */
768 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
770 case 0x40: /* SDRAM_B0CR */
771 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
773 case 0x44: /* SDRAM_B1CR */
774 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
776 case 0x48: /* SDRAM_B2CR */
777 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
779 case 0x4C: /* SDRAM_B3CR */
780 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
782 case 0x80: /* SDRAM_TR */
783 sdram->tr = val & 0x018FC01F;
785 case 0x94: /* SDRAM_ECCCFG */
786 sdram->ecccfg = val & 0x00F00000;
788 case 0x98: /* SDRAM_ECCESR */
790 if (sdram->eccesr == 0 && val != 0)
791 qemu_irq_raise(sdram->irq);
792 else if (sdram->eccesr != 0 && val == 0)
793 qemu_irq_lower(sdram->irq);
803 static void sdram_reset (void *opaque)
805 ppc4xx_sdram_t *sdram;
808 sdram->addr = 0x00000000;
809 sdram->bear = 0x00000000;
810 sdram->besr0 = 0x00000000; /* No error */
811 sdram->besr1 = 0x00000000; /* No error */
812 sdram->cfg = 0x00000000;
813 sdram->ecccfg = 0x00000000; /* No ECC */
814 sdram->eccesr = 0x00000000; /* No error */
815 sdram->pmit = 0x07C00000;
816 sdram->rtr = 0x05F00000;
817 sdram->tr = 0x00854009;
818 /* We pre-initialize RAM banks */
819 sdram->status = 0x00000000;
820 sdram->cfg = 0x00800000;
821 sdram_unmap_bcr(sdram);
824 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
825 target_phys_addr_t *ram_bases,
826 target_phys_addr_t *ram_sizes,
829 ppc4xx_sdram_t *sdram;
831 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
834 sdram->nbanks = nbanks;
835 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
836 memcpy(sdram->ram_bases, ram_bases,
837 nbanks * sizeof(target_phys_addr_t));
838 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
839 memcpy(sdram->ram_sizes, ram_sizes,
840 nbanks * sizeof(target_phys_addr_t));
842 qemu_register_reset(&sdram_reset, sdram);
843 ppc_dcr_register(env, SDRAM0_CFGADDR,
844 sdram, &dcr_read_sdram, &dcr_write_sdram);
845 ppc_dcr_register(env, SDRAM0_CFGDATA,
846 sdram, &dcr_read_sdram, &dcr_write_sdram);
848 sdram_map_bcr(sdram);
852 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
854 * sdram_bank_sizes[] must be 0-terminated.
856 * The 4xx SDRAM controller supports a small number of banks, and each bank
857 * must be one of a small set of sizes. The number of banks and the supported
858 * sizes varies by SoC. */
859 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
860 target_phys_addr_t ram_bases[],
861 target_phys_addr_t ram_sizes[],
862 const unsigned int sdram_bank_sizes[])
864 ram_addr_t ram_end = 0;
868 for (i = 0; i < nr_banks; i++) {
869 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
870 unsigned int bank_size = sdram_bank_sizes[j];
872 if (bank_size <= ram_size) {
873 ram_bases[i] = ram_end;
874 ram_sizes[i] = bank_size;
875 ram_end += bank_size;
876 ram_size -= bank_size;
882 /* No need to use the remaining banks. */
888 printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
889 (int)(ram_end >> 20));