2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 //#define DEBUG_UNASSIGNED
36 /*****************************************************************************/
37 /* Generic PowerPC 4xx processor instanciation */
38 CPUState *ppc4xx_init (const char *cpu_model,
39 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
45 env = cpu_init(cpu_model);
47 fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
51 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
52 cpu_clk->opaque = env;
53 /* Set time-base frequency to sysclk */
54 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
56 ppc_dcr_init(env, NULL, NULL);
57 /* Register qemu callbacks */
58 qemu_register_reset(&cpu_ppc_reset, env);
63 /*****************************************************************************/
64 /* Fake device used to map multiple devices in a single memory page */
65 #define MMIO_AREA_BITS 8
66 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
67 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
68 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
69 struct ppc4xx_mmio_t {
70 target_phys_addr_t base;
71 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
72 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
73 void *opaque[MMIO_AREA_NB];
76 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
78 #ifdef DEBUG_UNASSIGNED
82 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
89 static void unassigned_mmio_writeb (void *opaque,
90 target_phys_addr_t addr, uint32_t val)
92 #ifdef DEBUG_UNASSIGNED
96 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
97 addr, val, mmio->base);
101 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
102 unassigned_mmio_readb,
103 unassigned_mmio_readb,
104 unassigned_mmio_readb,
107 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
108 unassigned_mmio_writeb,
109 unassigned_mmio_writeb,
110 unassigned_mmio_writeb,
113 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
114 target_phys_addr_t addr, int len)
116 CPUReadMemoryFunc **mem_read;
120 idx = MMIO_IDX(addr - mmio->base);
121 #if defined(DEBUG_MMIO)
122 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
123 mmio, len, addr, idx);
125 mem_read = mmio->mem_read[idx];
126 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
131 static void mmio_writelen (ppc4xx_mmio_t *mmio,
132 target_phys_addr_t addr, uint32_t value, int len)
134 CPUWriteMemoryFunc **mem_write;
137 idx = MMIO_IDX(addr - mmio->base);
138 #if defined(DEBUG_MMIO)
139 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
140 __func__, mmio, len, addr, idx, value);
142 mem_write = mmio->mem_write[idx];
143 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
146 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
148 #if defined(DEBUG_MMIO)
149 printf("%s: addr " PADDRX "\n", __func__, addr);
152 return mmio_readlen(opaque, addr, 0);
155 static void mmio_writeb (void *opaque,
156 target_phys_addr_t addr, uint32_t value)
158 #if defined(DEBUG_MMIO)
159 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
161 mmio_writelen(opaque, addr, value, 0);
164 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
166 #if defined(DEBUG_MMIO)
167 printf("%s: addr " PADDRX "\n", __func__, addr);
170 return mmio_readlen(opaque, addr, 1);
173 static void mmio_writew (void *opaque,
174 target_phys_addr_t addr, uint32_t value)
176 #if defined(DEBUG_MMIO)
177 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
179 mmio_writelen(opaque, addr, value, 1);
182 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
184 #if defined(DEBUG_MMIO)
185 printf("%s: addr " PADDRX "\n", __func__, addr);
188 return mmio_readlen(opaque, addr, 2);
191 static void mmio_writel (void *opaque,
192 target_phys_addr_t addr, uint32_t value)
194 #if defined(DEBUG_MMIO)
195 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
197 mmio_writelen(opaque, addr, value, 2);
200 static CPUReadMemoryFunc *mmio_read[] = {
206 static CPUWriteMemoryFunc *mmio_write[] = {
212 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
213 target_phys_addr_t offset, uint32_t len,
214 CPUReadMemoryFunc **mem_read,
215 CPUWriteMemoryFunc **mem_write, void *opaque)
217 target_phys_addr_t end;
220 if ((offset + len) > TARGET_PAGE_SIZE)
222 idx = MMIO_IDX(offset);
223 end = offset + len - 1;
224 eidx = MMIO_IDX(end);
225 #if defined(DEBUG_MMIO)
226 printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
227 __func__, offset, len, end, idx, eidx);
229 for (; idx <= eidx; idx++) {
230 mmio->mem_read[idx] = mem_read;
231 mmio->mem_write[idx] = mem_write;
232 mmio->opaque[idx] = opaque;
238 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
243 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
246 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
247 #if defined(DEBUG_MMIO)
248 printf("%s: base " PADDRX " len %08x %d\n", __func__,
249 base, TARGET_PAGE_SIZE, mmio_memory);
251 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
252 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
253 unassigned_mmio_read, unassigned_mmio_write,
260 /*****************************************************************************/
261 /* "Universal" Interrupt controller */
275 #define UIC_MAX_IRQ 32
276 typedef struct ppcuic_t ppcuic_t;
280 uint32_t level; /* Remembers the state of level-triggered interrupts. */
281 uint32_t uicsr; /* Status register */
282 uint32_t uicer; /* Enable register */
283 uint32_t uiccr; /* Critical register */
284 uint32_t uicpr; /* Polarity register */
285 uint32_t uictr; /* Triggering register */
286 uint32_t uicvcr; /* Vector configuration register */
291 static void ppcuic_trigger_irq (ppcuic_t *uic)
294 int start, end, inc, i;
296 /* Trigger interrupt if any is pending */
297 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
298 cr = uic->uicsr & uic->uicer & uic->uiccr;
300 if (loglevel & CPU_LOG_INT) {
301 fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
302 " uiccr %08" PRIx32 "\n"
303 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
304 __func__, uic->uicsr, uic->uicer, uic->uiccr,
305 uic->uicsr & uic->uicer, ir, cr);
308 if (ir != 0x0000000) {
310 if (loglevel & CPU_LOG_INT) {
311 fprintf(logfile, "Raise UIC interrupt\n");
314 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
317 if (loglevel & CPU_LOG_INT) {
318 fprintf(logfile, "Lower UIC interrupt\n");
321 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
323 /* Trigger critical interrupt if any is pending and update vector */
324 if (cr != 0x0000000) {
325 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
326 if (uic->use_vectors) {
327 /* Compute critical IRQ vector */
328 if (uic->uicvcr & 1) {
337 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
338 for (i = start; i <= end; i += inc) {
340 uic->uicvr += (i - start) * 512 * inc;
346 if (loglevel & CPU_LOG_INT) {
347 fprintf(logfile, "Raise UIC critical interrupt - "
348 "vector %08" PRIx32 "\n", uic->uicvr);
353 if (loglevel & CPU_LOG_INT) {
354 fprintf(logfile, "Lower UIC critical interrupt\n");
357 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
358 uic->uicvr = 0x00000000;
362 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
368 mask = 1 << (31-irq_num);
370 if (loglevel & CPU_LOG_INT) {
371 fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
372 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
373 __func__, irq_num, level,
374 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
377 if (irq_num < 0 || irq_num > 31)
381 /* Update status register */
382 if (uic->uictr & mask) {
383 /* Edge sensitive interrupt */
387 /* Level sensitive interrupt */
397 if (loglevel & CPU_LOG_INT) {
398 fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
399 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
402 if (sr != uic->uicsr)
403 ppcuic_trigger_irq(uic);
406 static target_ulong dcr_read_uic (void *opaque, int dcrn)
412 dcrn -= uic->dcr_base;
431 ret = uic->uicsr & uic->uicer;
434 if (!uic->use_vectors)
439 if (!uic->use_vectors)
452 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
457 dcrn -= uic->dcr_base;
459 if (loglevel & CPU_LOG_INT) {
460 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
466 uic->uicsr |= uic->level;
467 ppcuic_trigger_irq(uic);
471 ppcuic_trigger_irq(uic);
475 ppcuic_trigger_irq(uic);
479 ppcuic_trigger_irq(uic);
486 ppcuic_trigger_irq(uic);
493 uic->uicvcr = val & 0xFFFFFFFD;
494 ppcuic_trigger_irq(uic);
499 static void ppcuic_reset (void *opaque)
504 uic->uiccr = 0x00000000;
505 uic->uicer = 0x00000000;
506 uic->uicpr = 0x00000000;
507 uic->uicsr = 0x00000000;
508 uic->uictr = 0x00000000;
509 if (uic->use_vectors) {
510 uic->uicvcr = 0x00000000;
511 uic->uicvr = 0x0000000;
515 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
516 uint32_t dcr_base, int has_ssr, int has_vr)
521 uic = qemu_mallocz(sizeof(ppcuic_t));
523 uic->dcr_base = dcr_base;
526 uic->use_vectors = 1;
527 for (i = 0; i < DCR_UICMAX; i++) {
528 ppc_dcr_register(env, dcr_base + i, uic,
529 &dcr_read_uic, &dcr_write_uic);
531 qemu_register_reset(ppcuic_reset, uic);
535 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);