2 * QEMU PPC CHRP/PMAC hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define BIOS_FILENAME "ppc_rom.bin"
27 #define VGABIOS_FILENAME "video.x"
28 #define NVRAM_SIZE 0x2000
30 #define KERNEL_LOAD_ADDR 0x01000000
31 #define INITRD_LOAD_ADDR 0x01800000
33 /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
36 static int dbdma_mem_index;
37 static int cuda_mem_index;
38 static int ide0_mem_index = -1;
39 static int ide1_mem_index = -1;
40 static int openpic_mem_index = -1;
41 static int heathrow_pic_mem_index = -1;
42 static int macio_nvram_mem_index = -1;
44 /* DBDMA: currently no op - should suffice right now */
46 static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
48 printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
51 static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
55 static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
59 static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
61 printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
65 static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
70 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
75 static CPUWriteMemoryFunc *dbdma_write[] = {
81 static CPUReadMemoryFunc *dbdma_read[] = {
87 /* macio style NVRAM device */
88 typedef struct MacIONVRAMState {
92 static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
94 MacIONVRAMState *s = opaque;
95 addr = (addr >> 4) & 0x1fff;
96 s->data[addr] = value;
97 // printf("macio_nvram_writeb %04x = %02x\n", addr, value);
100 static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
102 MacIONVRAMState *s = opaque;
105 addr = (addr >> 4) & 0x1fff;
106 value = s->data[addr];
107 // printf("macio_nvram_readb %04x = %02x\n", addr, value);
111 static CPUWriteMemoryFunc *macio_nvram_write[] = {
117 static CPUReadMemoryFunc *macio_nvram_read[] = {
123 static MacIONVRAMState *macio_nvram_init(void)
126 s = qemu_mallocz(sizeof(MacIONVRAMState));
129 macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
130 macio_nvram_write, s);
134 static void macio_map(PCIDevice *pci_dev, int region_num,
135 uint32_t addr, uint32_t size, int type)
137 if (heathrow_pic_mem_index >= 0) {
138 cpu_register_physical_memory(addr + 0x00000, 0x1000,
139 heathrow_pic_mem_index);
141 cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
142 cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
143 if (ide0_mem_index >= 0)
144 cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
145 if (ide1_mem_index >= 0)
146 cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
147 if (openpic_mem_index >= 0) {
148 cpu_register_physical_memory(addr + 0x40000, 0x40000,
151 if (macio_nvram_mem_index >= 0)
152 cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
155 static void macio_init(PCIBus *bus, int device_id)
159 d = pci_register_device(bus, "macio", sizeof(PCIDevice),
161 /* Note: this code is strongly inspirated from the corresponding code
163 d->config[0x00] = 0x6b; // vendor_id
164 d->config[0x01] = 0x10;
165 d->config[0x02] = device_id;
166 d->config[0x03] = device_id >> 8;
168 d->config[0x0a] = 0x00; // class_sub = pci2pci
169 d->config[0x0b] = 0xff; // class_base = bridge
170 d->config[0x0e] = 0x00; // header_type
172 d->config[0x3d] = 0x01; // interrupt on pin 1
174 dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
176 pci_register_io_region(d, 0, 0x80000,
177 PCI_ADDRESS_SPACE_MEM, macio_map);
181 static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
185 static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
190 static CPUWriteMemoryFunc *unin_write[] = {
196 static CPUReadMemoryFunc *unin_read[] = {
202 /* temporary frame buffer OSI calls for the video.x driver. The right
203 solution is to modify the driver to use VGA PCI I/Os */
204 static int vga_osi_call(CPUState *env)
206 static int vga_vbl_enabled;
209 // printf("osi_call R5=%d\n", env->gpr[5]);
211 /* same handler as PearPC, coming from the original MOL video
213 switch(env->gpr[5]) {
216 case 28: /* set_vmode */
217 if (env->gpr[6] != 1 || env->gpr[7] != 0)
222 case 29: /* get_vmode_info */
223 if (env->gpr[6] != 0) {
224 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
230 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
231 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
232 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
233 env->gpr[7] = 85 << 16; /* refresh rate */
234 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
235 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
236 linesize = (linesize + 3) & ~3;
237 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
239 case 31: /* set_video power */
242 case 39: /* video_ctrl */
243 if (env->gpr[6] == 0 || env->gpr[6] == 1)
244 vga_vbl_enabled = env->gpr[6];
249 case 59: /* set_color */
250 /* R6 = index, R7 = RGB */
253 case 64: /* get color */
257 case 116: /* set hwcursor */
258 /* R6 = x, R7 = y, R8 = visible, R9 = data */
261 fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
264 return 1; /* osi_call handled */
267 static uint8_t nvram_chksum(const uint8_t *buf, int n)
271 for(i = 0; i < n; i++)
273 return (sum & 0xff) + (sum >> 8);
276 /* set a free Mac OS NVRAM partition */
277 void pmac_format_nvram_partition(uint8_t *buf, int len)
279 char partition_name[12] = "wwwwwwwwwwww";
281 buf[0] = 0x7f; /* free partition magic */
282 buf[1] = 0; /* checksum */
285 memcpy(buf + 4, partition_name, 12);
286 buf[1] = nvram_chksum(buf, 16);
289 /* PowerPC CHRP hardware initialisation */
290 static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
291 DisplayState *ds, const char **fd_filename,
293 const char *kernel_filename,
294 const char *kernel_cmdline,
295 const char *initrd_filename,
296 const char *cpu_model,
305 unsigned long bios_offset, vga_bios_offset;
306 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
309 const char *arch_name;
310 int vga_bios_size, bios_size;
313 linux_boot = (kernel_filename != NULL);
317 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
319 /* Default CPU is a generic 74x/75x */
320 if (cpu_model == NULL)
322 /* XXX: CPU model (or PVR) should be provided on command line */
323 // ppc_find_by_name("750gx", &def); // Linux boot OK
324 // ppc_find_by_name("750fx", &def); // Linux boot OK
325 /* Linux does not boot on 750cxe (and probably other 750cx based)
326 * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
328 ppc_find_by_name(cpu_model, &def);
330 cpu_abort(env, "Unable to find PowerPC CPU definition\n");
332 cpu_ppc_register(env, def);
333 cpu_ppc_irq_init_cpu(env);
335 /* Set time-base frequency to 100 Mhz */
336 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
338 env->osi_call = vga_osi_call;
341 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
343 /* allocate and load BIOS */
344 bios_offset = ram_size + vga_ram_size;
345 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
346 bios_size = load_image(buf, phys_ram_base + bios_offset);
347 if (bios_size < 0 || bios_size > BIOS_SIZE) {
348 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
351 bios_size = (bios_size + 0xfff) & ~0xfff;
352 cpu_register_physical_memory((uint32_t)(-bios_size),
353 bios_size, bios_offset | IO_MEM_ROM);
355 /* allocate and load VGA BIOS */
356 vga_bios_offset = bios_offset + bios_size;
357 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
358 vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
359 if (vga_bios_size < 0) {
360 /* if no bios is present, we can still work */
361 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
364 /* set a specific header (XXX: find real Apple format for NDRV
366 phys_ram_base[vga_bios_offset] = 'N';
367 phys_ram_base[vga_bios_offset + 1] = 'D';
368 phys_ram_base[vga_bios_offset + 2] = 'R';
369 phys_ram_base[vga_bios_offset + 3] = 'V';
370 cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
374 vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
377 kernel_base = KERNEL_LOAD_ADDR;
378 /* now we can load the kernel */
379 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
380 if (kernel_size < 0) {
381 fprintf(stderr, "qemu: could not load kernel '%s'\n",
386 if (initrd_filename) {
387 initrd_base = INITRD_LOAD_ADDR;
388 initrd_size = load_image(initrd_filename,
389 phys_ram_base + initrd_base);
390 if (initrd_size < 0) {
391 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
408 isa_mem_base = 0x80000000;
410 /* Register 2 MB of ISA IO space */
411 isa_mmio_init(0xfe000000, 0x00200000);
413 /* init basic PC hardware */
414 pic = heathrow_pic_init(&heathrow_pic_mem_index);
415 pci_bus = pci_grackle_init(0xfec00000, pic);
416 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
417 ram_size, vga_ram_size,
418 vga_bios_offset, vga_bios_size);
420 /* XXX: suppress that */
421 dummy_irq = i8259_init(NULL);
423 /* XXX: use Mac Serial port */
424 serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
426 for(i = 0; i < nb_nics; i++) {
427 if (!nd_table[i].model)
428 nd_table[i].model = "ne2k_pci";
429 pci_nic_init(pci_bus, &nd_table[i], -1);
432 pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
434 /* cuda also initialize ADB */
435 cuda_mem_index = cuda_init(pic[0x12]);
437 adb_kbd_init(&adb_bus);
438 adb_mouse_init(&adb_bus);
441 MacIONVRAMState *nvr;
442 nvr = macio_nvram_init();
443 pmac_format_nvram_partition(nvr->data, 0x2000);
446 macio_init(pci_bus, 0x0017);
448 nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
450 arch_name = "HEATHROW";
452 isa_mem_base = 0x80000000;
454 /* Register 8 MB of ISA IO space */
455 isa_mmio_init(0xf2000000, 0x00800000);
458 unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
459 cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
461 pic = openpic_init(NULL, &ppc_openpic_irq, &openpic_mem_index, 1, &env);
462 pci_bus = pci_pmac_init(pic);
463 /* init basic PC hardware */
464 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
465 ram_size, vga_ram_size,
466 vga_bios_offset, vga_bios_size);
468 /* XXX: suppress that */
469 dummy_irq = i8259_init(NULL);
471 /* XXX: use Mac Serial port */
472 serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
473 for(i = 0; i < nb_nics; i++) {
474 if (!nd_table[i].model)
475 nd_table[i].model = "ne2k_pci";
476 pci_nic_init(pci_bus, &nd_table[i], -1);
479 ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
480 ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
482 pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
484 /* cuda also initialize ADB */
485 cuda_mem_index = cuda_init(pic[0x19]);
487 adb_kbd_init(&adb_bus);
488 adb_mouse_init(&adb_bus);
490 macio_init(pci_bus, 0x0022);
492 nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
498 usb_ohci_init_pci(pci_bus, 3, -1);
501 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
504 PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
505 kernel_base, kernel_size,
507 initrd_base, initrd_size,
508 /* XXX: need an option to load a NVRAM image */
510 graphic_width, graphic_height, graphic_depth);
511 /* No PCI init: the BIOS will do it */
513 /* Special port to get debug messages from Open-Firmware */
514 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
517 static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
518 DisplayState *ds, const char **fd_filename,
520 const char *kernel_filename,
521 const char *kernel_cmdline,
522 const char *initrd_filename,
523 const char *cpu_model)
525 ppc_chrp_init(ram_size, vga_ram_size, boot_device,
526 ds, fd_filename, snapshot,
527 kernel_filename, kernel_cmdline,
528 initrd_filename, cpu_model, 0);
531 static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
532 DisplayState *ds, const char **fd_filename,
534 const char *kernel_filename,
535 const char *kernel_cmdline,
536 const char *initrd_filename,
537 const char *cpu_model)
539 ppc_chrp_init(ram_size, vga_ram_size, boot_device,
540 ds, fd_filename, snapshot,
541 kernel_filename, kernel_cmdline,
542 initrd_filename, cpu_model, 1);
545 QEMUMachine core99_machine = {
547 "Mac99 based PowerMAC",
551 QEMUMachine heathrow_machine = {
553 "Heathrow based PowerMAC",