2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define HARD_DEBUG_PPC_IO
27 //#define DEBUG_PPC_IO
29 /* SMP is not enabled, for now */
32 #define BIOS_FILENAME "ppc_rom.bin"
33 #define KERNEL_LOAD_ADDR 0x01000000
34 #define INITRD_LOAD_ADDR 0x01800000
39 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
43 #if defined (HARD_DEBUG_PPC_IO)
44 #define PPC_IO_DPRINTF(fmt, args...) \
46 if (loglevel & CPU_LOG_IOPORT) { \
47 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
49 printf("%s : " fmt, __func__ , ##args); \
52 #elif defined (DEBUG_PPC_IO)
53 #define PPC_IO_DPRINTF(fmt, args...) \
55 if (loglevel & CPU_LOG_IOPORT) { \
56 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
60 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
63 /* Constants for devices init */
64 static const int ide_iobase[2] = { 0x1f0, 0x170 };
65 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
66 static const int ide_irq[2] = { 13, 13 };
68 #define NE2000_NB_MAX 6
70 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
71 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
73 //static PITState *pit;
75 /* ISA IO ports bridge */
76 #define PPC_IO_BASE 0x80000000
78 /* Speaker port 0x61 */
80 int dummy_refresh_clock;
82 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
85 speaker_data_on = (val >> 1) & 1;
86 pit_set_gate(pit, 2, val & 1);
90 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
94 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
95 dummy_refresh_clock ^= 1;
96 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
97 (dummy_refresh_clock << 4);
102 /* PCI intack register */
103 /* Read-only register (?) */
104 static void _PPC_intack_write (void *opaque,
105 target_phys_addr_t addr, uint32_t value)
107 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
110 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
114 if (addr == 0xBFFFFFF0)
115 retval = pic_intack_read(isa_pic);
116 // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
121 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
123 return _PPC_intack_read(addr);
126 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
128 #ifdef TARGET_WORDS_BIGENDIAN
129 return bswap16(_PPC_intack_read(addr));
131 return _PPC_intack_read(addr);
135 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
137 #ifdef TARGET_WORDS_BIGENDIAN
138 return bswap32(_PPC_intack_read(addr));
140 return _PPC_intack_read(addr);
144 static CPUWriteMemoryFunc *PPC_intack_write[] = {
150 static CPUReadMemoryFunc *PPC_intack_read[] = {
156 /* PowerPC control and status registers */
162 /* Control and status */
167 /* General purpose registers */
180 /* Error diagnostic */
183 static void PPC_XCSR_writeb (void *opaque,
184 target_phys_addr_t addr, uint32_t value)
186 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
189 static void PPC_XCSR_writew (void *opaque,
190 target_phys_addr_t addr, uint32_t value)
192 #ifdef TARGET_WORDS_BIGENDIAN
193 value = bswap16(value);
195 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
198 static void PPC_XCSR_writel (void *opaque,
199 target_phys_addr_t addr, uint32_t value)
201 #ifdef TARGET_WORDS_BIGENDIAN
202 value = bswap32(value);
204 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
207 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
211 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
216 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
220 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
221 #ifdef TARGET_WORDS_BIGENDIAN
222 retval = bswap16(retval);
228 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
232 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
233 #ifdef TARGET_WORDS_BIGENDIAN
234 retval = bswap32(retval);
240 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
246 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
253 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
254 typedef struct sysctrl_t {
264 STATE_HARDFILE = 0x01,
267 static sysctrl_t *sysctrl;
269 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
271 sysctrl_t *sysctrl = opaque;
273 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
274 sysctrl->fake_io[addr - 0x0398] = val;
277 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
279 sysctrl_t *sysctrl = opaque;
281 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
282 sysctrl->fake_io[addr - 0x0398]);
283 return sysctrl->fake_io[addr - 0x0398];
286 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
288 sysctrl_t *sysctrl = opaque;
290 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
293 /* Special port 92 */
294 /* Check soft reset asked */
296 // cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
306 /* Motorola CPU configuration register : read-only */
309 /* Motorola base module feature register : read-only */
312 /* Motorola base module status register : read-only */
315 /* Hardfile light register */
317 sysctrl->state |= STATE_HARDFILE;
319 sysctrl->state &= ~STATE_HARDFILE;
322 /* Password protect 1 register */
323 if (sysctrl->nvram != NULL)
324 m48t59_toggle_lock(sysctrl->nvram, 1);
327 /* Password protect 2 register */
328 if (sysctrl->nvram != NULL)
329 m48t59_toggle_lock(sysctrl->nvram, 2);
332 /* L2 invalidate register */
333 // tlb_flush(first_cpu, 1);
336 /* system control register */
337 sysctrl->syscontrol = val & 0x0F;
340 /* I/O map type register */
341 sysctrl->contiguous_map = val & 0x01;
344 printf("ERROR: unaffected IO port write: %04lx => %02x\n",
350 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
352 sysctrl_t *sysctrl = opaque;
353 uint32_t retval = 0xFF;
357 /* Special port 92 */
361 /* Motorola CPU configuration register */
362 retval = 0xEF; /* MPC750 */
365 /* Motorola Base module feature register */
366 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
369 /* Motorola base module status register */
370 retval = 0xE0; /* Standard MPC750 */
373 /* Equipment present register:
375 * no upgrade processor
376 * no cards in PCI slots
382 /* Motorola base module extended feature register */
383 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
386 /* L2 invalidate: don't care */
393 /* system control register
394 * 7 - 6 / 1 - 0: L2 cache enable
396 retval = sysctrl->syscontrol;
400 retval = 0x03; /* no L2 cache */
403 /* I/O map type register */
404 retval = sysctrl->contiguous_map;
407 printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
410 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
415 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
419 if (sysctrl->contiguous_map == 0) {
420 /* 64 KB contiguous space for IOs */
423 /* 8 MB non-contiguous space for IOs */
424 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
430 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
433 sysctrl_t *sysctrl = opaque;
435 addr = prep_IO_address(sysctrl, addr);
436 cpu_outb(NULL, addr, value);
439 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
441 sysctrl_t *sysctrl = opaque;
444 addr = prep_IO_address(sysctrl, addr);
445 ret = cpu_inb(NULL, addr);
450 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
453 sysctrl_t *sysctrl = opaque;
455 addr = prep_IO_address(sysctrl, addr);
456 #ifdef TARGET_WORDS_BIGENDIAN
457 value = bswap16(value);
459 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
460 cpu_outw(NULL, addr, value);
463 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
465 sysctrl_t *sysctrl = opaque;
468 addr = prep_IO_address(sysctrl, addr);
469 ret = cpu_inw(NULL, addr);
470 #ifdef TARGET_WORDS_BIGENDIAN
473 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
478 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
481 sysctrl_t *sysctrl = opaque;
483 addr = prep_IO_address(sysctrl, addr);
484 #ifdef TARGET_WORDS_BIGENDIAN
485 value = bswap32(value);
487 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
488 cpu_outl(NULL, addr, value);
491 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
493 sysctrl_t *sysctrl = opaque;
496 addr = prep_IO_address(sysctrl, addr);
497 ret = cpu_inl(NULL, addr);
498 #ifdef TARGET_WORDS_BIGENDIAN
501 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
506 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
512 CPUReadMemoryFunc *PPC_prep_io_read[] = {
518 #define NVRAM_SIZE 0x2000
520 /* PowerPC PREP hardware initialisation */
521 static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
522 DisplayState *ds, const char **fd_filename,
523 int snapshot, const char *kernel_filename,
524 const char *kernel_cmdline,
525 const char *initrd_filename,
526 const char *cpu_model)
528 CPUState *env, *envs[MAX_CPUS];
532 int linux_boot, i, nb_nics1, bios_size;
533 unsigned long bios_offset;
534 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
539 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
543 linux_boot = (kernel_filename != NULL);
547 if (cpu_model == NULL)
548 cpu_model = "default";
549 ppc_find_by_name(cpu_model, &def);
551 cpu_abort(env, "Unable to find PowerPC CPU definition\n");
553 for (i = 0; i < smp_cpus; i++) {
554 cpu_ppc_register(env, def);
556 /* Set time-base frequency to 100 Mhz */
557 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
558 qemu_register_reset(&cpu_ppc_reset, env);
559 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
564 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
566 /* allocate and load BIOS */
567 bios_offset = ram_size + vga_ram_size;
568 if (bios_name == NULL)
569 bios_name = BIOS_FILENAME;
570 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
571 bios_size = load_image(buf, phys_ram_base + bios_offset);
572 if (bios_size < 0 || bios_size > BIOS_SIZE) {
573 cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
576 bios_size = (bios_size + 0xfff) & ~0xfff;
577 cpu_register_physical_memory((uint32_t)(-bios_size),
578 bios_size, bios_offset | IO_MEM_ROM);
581 kernel_base = KERNEL_LOAD_ADDR;
582 /* now we can load the kernel */
583 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
584 if (kernel_size < 0) {
585 cpu_abort(env, "qemu: could not load kernel '%s'\n",
590 if (initrd_filename) {
591 initrd_base = INITRD_LOAD_ADDR;
592 initrd_size = load_image(initrd_filename,
593 phys_ram_base + initrd_base);
594 if (initrd_size < 0) {
595 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
611 isa_mem_base = 0xc0000000;
612 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
613 cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
616 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
617 pci_bus = pci_prep_init(i8259);
618 // pci_bus = i440fx_init();
619 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
620 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
621 PPC_prep_io_write, sysctrl);
622 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
624 /* init basic PC hardware */
625 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
627 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
628 // pit = pit_init(0x40, i8259[0]);
629 rtc_init(0x70, i8259[8]);
631 serial_init(0x3f8, i8259[4], serial_hds[0]);
633 if (nb_nics1 > NE2000_NB_MAX)
634 nb_nics1 = NE2000_NB_MAX;
635 for(i = 0; i < nb_nics1; i++) {
636 if (nd_table[i].model == NULL
637 || strcmp(nd_table[i].model, "ne2k_isa") == 0) {
638 isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
640 pci_nic_init(pci_bus, &nd_table[i], -1);
644 for(i = 0; i < 2; i++) {
645 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
646 bs_table[2 * i], bs_table[2 * i + 1]);
648 i8042_init(i8259[1], i8259[12], 0x60);
653 fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
655 /* Register speaker port */
656 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
657 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
658 /* Register fake IO ports for PREP */
659 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
660 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
661 /* System control ports */
662 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
663 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
664 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
665 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
666 /* PCI intack location */
667 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
668 PPC_intack_write, NULL);
669 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
670 /* PowerPC control and status register group */
672 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
674 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
678 usb_ohci_init_pci(pci_bus, 3, -1);
681 nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
684 sysctrl->nvram = nvram;
686 /* Initialise NVRAM */
687 PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
688 kernel_base, kernel_size,
690 initrd_base, initrd_size,
691 /* XXX: need an option to load a NVRAM image */
693 graphic_width, graphic_height, graphic_depth);
695 /* Special port to get debug messages from Open-Firmware */
696 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
699 QEMUMachine prep_machine = {
701 "PowerPC PREP platform",