2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define HARD_DEBUG_PPC_IO
27 //#define DEBUG_PPC_IO
29 #define BIOS_FILENAME "ppc_rom.bin"
30 #define KERNEL_LOAD_ADDR 0x01000000
31 #define INITRD_LOAD_ADDR 0x01800000
36 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
40 #if defined (HARD_DEBUG_PPC_IO)
41 #define PPC_IO_DPRINTF(fmt, args...) \
43 if (loglevel & CPU_LOG_IOPORT) { \
44 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
46 printf("%s : " fmt, __func__ , ##args); \
49 #elif defined (DEBUG_PPC_IO)
50 #define PPC_IO_DPRINTF(fmt, args...) \
52 if (loglevel & CPU_LOG_IOPORT) { \
53 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
57 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
60 /* Constants for devices init */
61 static const int ide_iobase[2] = { 0x1f0, 0x170 };
62 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
63 static const int ide_irq[2] = { 13, 13 };
65 #define NE2000_NB_MAX 6
67 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
68 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
70 //static PITState *pit;
72 /* ISA IO ports bridge */
73 #define PPC_IO_BASE 0x80000000
75 /* Speaker port 0x61 */
77 int dummy_refresh_clock;
79 static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
82 speaker_data_on = (val >> 1) & 1;
83 pit_set_gate(pit, 2, val & 1);
87 static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
91 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
92 dummy_refresh_clock ^= 1;
93 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
94 (dummy_refresh_clock << 4);
99 static void pic_irq_request(void *opaque, int level)
102 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
104 cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
107 /* PCI intack register */
108 /* Read-only register (?) */
109 static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value)
111 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
114 static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
118 if (addr == 0xBFFFFFF0)
119 retval = pic_intack_read(isa_pic);
120 // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
125 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
127 return _PPC_intack_read(addr);
130 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
132 #ifdef TARGET_WORDS_BIGENDIAN
133 return bswap16(_PPC_intack_read(addr));
135 return _PPC_intack_read(addr);
139 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
141 #ifdef TARGET_WORDS_BIGENDIAN
142 return bswap32(_PPC_intack_read(addr));
144 return _PPC_intack_read(addr);
148 static CPUWriteMemoryFunc *PPC_intack_write[] = {
154 static CPUReadMemoryFunc *PPC_intack_read[] = {
160 /* PowerPC control and status registers */
166 /* Control and status */
171 /* General purpose registers */
184 /* Error diagnostic */
187 static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
189 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
192 static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
194 #ifdef TARGET_WORDS_BIGENDIAN
195 value = bswap16(value);
197 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
200 static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
202 #ifdef TARGET_WORDS_BIGENDIAN
203 value = bswap32(value);
205 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
208 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
212 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
217 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
221 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
222 #ifdef TARGET_WORDS_BIGENDIAN
223 retval = bswap16(retval);
229 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
233 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
234 #ifdef TARGET_WORDS_BIGENDIAN
235 retval = bswap32(retval);
241 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
247 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
254 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
255 typedef struct sysctrl_t {
264 STATE_HARDFILE = 0x01,
267 static sysctrl_t *sysctrl;
269 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
271 sysctrl_t *sysctrl = opaque;
273 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
274 sysctrl->fake_io[addr - 0x0398] = val;
277 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
279 sysctrl_t *sysctrl = opaque;
281 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
282 sysctrl->fake_io[addr - 0x0398]);
283 return sysctrl->fake_io[addr - 0x0398];
286 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
288 sysctrl_t *sysctrl = opaque;
290 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
293 /* Special port 92 */
294 /* Check soft reset asked */
296 // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
300 printf("Little Endian mode isn't supported (yet ?)\n");
305 /* Motorola CPU configuration register : read-only */
308 /* Motorola base module feature register : read-only */
311 /* Motorola base module status register : read-only */
314 /* Hardfile light register */
316 sysctrl->state |= STATE_HARDFILE;
318 sysctrl->state &= ~STATE_HARDFILE;
321 /* Password protect 1 register */
322 if (sysctrl->nvram != NULL)
323 m48t59_toggle_lock(sysctrl->nvram, 1);
326 /* Password protect 2 register */
327 if (sysctrl->nvram != NULL)
328 m48t59_toggle_lock(sysctrl->nvram, 2);
331 /* L2 invalidate register */
332 // tlb_flush(cpu_single_env, 1);
335 /* system control register */
336 sysctrl->syscontrol = val & 0x0F;
339 /* I/O map type register */
340 sysctrl->contiguous_map = val & 0x01;
343 printf("ERROR: unaffected IO port write: %04lx => %02x\n",
349 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
351 sysctrl_t *sysctrl = opaque;
352 uint32_t retval = 0xFF;
356 /* Special port 92 */
360 /* Motorola CPU configuration register */
361 retval = 0xEF; /* MPC750 */
364 /* Motorola Base module feature register */
365 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
368 /* Motorola base module status register */
369 retval = 0xE0; /* Standard MPC750 */
372 /* Equipment present register:
374 * no upgrade processor
375 * no cards in PCI slots
381 /* Motorola base module extended feature register */
382 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
385 /* L2 invalidate: don't care */
392 /* system control register
393 * 7 - 6 / 1 - 0: L2 cache enable
395 retval = sysctrl->syscontrol;
399 retval = 0x03; /* no L2 cache */
402 /* I/O map type register */
403 retval = sysctrl->contiguous_map;
406 printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
409 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
414 static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
415 target_phys_addr_t addr)
417 if (sysctrl->contiguous_map == 0) {
418 /* 64 KB contiguous space for IOs */
421 /* 8 MB non-contiguous space for IOs */
422 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
428 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
431 sysctrl_t *sysctrl = opaque;
433 addr = prep_IO_address(sysctrl, addr);
434 cpu_outb(NULL, addr, value);
437 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
439 sysctrl_t *sysctrl = opaque;
442 addr = prep_IO_address(sysctrl, addr);
443 ret = cpu_inb(NULL, addr);
448 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
451 sysctrl_t *sysctrl = opaque;
453 addr = prep_IO_address(sysctrl, addr);
454 #ifdef TARGET_WORDS_BIGENDIAN
455 value = bswap16(value);
457 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
458 cpu_outw(NULL, addr, value);
461 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
463 sysctrl_t *sysctrl = opaque;
466 addr = prep_IO_address(sysctrl, addr);
467 ret = cpu_inw(NULL, addr);
468 #ifdef TARGET_WORDS_BIGENDIAN
471 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
476 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
479 sysctrl_t *sysctrl = opaque;
481 addr = prep_IO_address(sysctrl, addr);
482 #ifdef TARGET_WORDS_BIGENDIAN
483 value = bswap32(value);
485 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
486 cpu_outl(NULL, addr, value);
489 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
491 sysctrl_t *sysctrl = opaque;
494 addr = prep_IO_address(sysctrl, addr);
495 ret = cpu_inl(NULL, addr);
496 #ifdef TARGET_WORDS_BIGENDIAN
499 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
504 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
510 CPUReadMemoryFunc *PPC_prep_io_read[] = {
516 #define NVRAM_SIZE 0x2000
518 /* PowerPC PREP hardware initialisation */
519 static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
520 DisplayState *ds, const char **fd_filename, int snapshot,
521 const char *kernel_filename, const char *kernel_cmdline,
522 const char *initrd_filename)
527 int ret, linux_boot, i, nb_nics1;
528 unsigned long bios_offset;
529 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
533 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
537 linux_boot = (kernel_filename != NULL);
540 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
542 /* allocate and load BIOS */
543 bios_offset = ram_size + vga_ram_size;
544 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
545 ret = load_image(buf, phys_ram_base + bios_offset);
546 if (ret != BIOS_SIZE) {
547 fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
550 cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
551 BIOS_SIZE, bios_offset | IO_MEM_ROM);
552 cpu_single_env->nip = 0xfffffffc;
555 kernel_base = KERNEL_LOAD_ADDR;
556 /* now we can load the kernel */
557 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
558 if (kernel_size < 0) {
559 fprintf(stderr, "qemu: could not load kernel '%s'\n",
564 if (initrd_filename) {
565 initrd_base = INITRD_LOAD_ADDR;
566 initrd_size = load_image(initrd_filename,
567 phys_ram_base + initrd_base);
568 if (initrd_size < 0) {
569 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
585 /* Register CPU as a 604 */
586 /* XXX: CPU model (or PVR) should be provided on command line */
587 // ppc_find_by_name("604r", &def);
588 // ppc_find_by_name("604e", &def);
589 ppc_find_by_name("604", &def);
591 cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
593 cpu_ppc_register(cpu_single_env, def);
594 /* Set time-base frequency to 100 Mhz */
595 cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
597 isa_mem_base = 0xc0000000;
598 pci_bus = pci_prep_init();
599 // pci_bus = i440fx_init();
600 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
601 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
602 PPC_prep_io_write, sysctrl);
603 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
605 /* init basic PC hardware */
606 vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
609 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
610 isa_pic = pic_init(pic_irq_request, cpu_single_env);
611 // pit = pit_init(0x40, 0);
613 serial_init(0x3f8, 4, serial_hds[0]);
615 if (nb_nics1 > NE2000_NB_MAX)
616 nb_nics1 = NE2000_NB_MAX;
617 for(i = 0; i < nb_nics1; i++) {
618 isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
621 for(i = 0; i < 2; i++) {
622 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
623 bs_table[2 * i], bs_table[2 * i + 1]);
630 fdctrl_init(6, 2, 0, 0x3f0, fd_table);
632 /* Register speaker port */
633 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
634 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
635 /* Register fake IO ports for PREP */
636 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
637 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
638 /* System control ports */
639 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
640 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
641 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
642 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
643 /* PCI intack location */
644 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
645 PPC_intack_write, NULL);
646 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
647 /* PowerPC control and status register group */
649 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
650 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
653 nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
656 sysctrl->nvram = nvram;
658 /* Initialise NVRAM */
659 PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
660 kernel_base, kernel_size,
662 initrd_base, initrd_size,
663 /* XXX: need an option to load a NVRAM image */
665 graphic_width, graphic_height, graphic_depth);
667 /* Special port to get debug messages from Open-Firmware */
668 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
671 QEMUMachine prep_machine = {
673 "PowerPC PREP platform",