2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define HARD_DEBUG_PPC_IO
27 //#define DEBUG_PPC_IO
29 #define BIOS_FILENAME "ppc_rom.bin"
30 #define KERNEL_LOAD_ADDR 0x01000000
31 #define INITRD_LOAD_ADDR 0x01800000
36 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
40 #if defined (HARD_DEBUG_PPC_IO)
41 #define PPC_IO_DPRINTF(fmt, args...) \
43 if (loglevel & CPU_LOG_IOPORT) { \
44 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
46 printf("%s : " fmt, __func__ , ##args); \
49 #elif defined (DEBUG_PPC_IO)
50 #define PPC_IO_DPRINTF(fmt, args...) \
52 if (loglevel & CPU_LOG_IOPORT) { \
53 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
57 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
60 /* Constants for devices init */
61 static const int ide_iobase[2] = { 0x1f0, 0x170 };
62 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
63 static const int ide_irq[2] = { 13, 13 };
65 #define NE2000_NB_MAX 6
67 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
68 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
70 //static PITState *pit;
72 /* ISA IO ports bridge */
73 #define PPC_IO_BASE 0x80000000
75 /* Speaker port 0x61 */
77 int dummy_refresh_clock;
79 static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
82 speaker_data_on = (val >> 1) & 1;
83 pit_set_gate(pit, 2, val & 1);
87 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
91 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
92 dummy_refresh_clock ^= 1;
93 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
94 (dummy_refresh_clock << 4);
99 static void pic_irq_request (void *opaque, int level)
101 ppc_set_irq(opaque, PPC_INTERRUPT_EXT, level);
104 /* PCI intack register */
105 /* Read-only register (?) */
106 static void _PPC_intack_write (void *opaque,
107 target_phys_addr_t addr, uint32_t value)
109 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
112 static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
116 if (addr == 0xBFFFFFF0)
117 retval = pic_intack_read(isa_pic);
118 // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
123 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
125 return _PPC_intack_read(addr);
128 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
130 #ifdef TARGET_WORDS_BIGENDIAN
131 return bswap16(_PPC_intack_read(addr));
133 return _PPC_intack_read(addr);
137 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
139 #ifdef TARGET_WORDS_BIGENDIAN
140 return bswap32(_PPC_intack_read(addr));
142 return _PPC_intack_read(addr);
146 static CPUWriteMemoryFunc *PPC_intack_write[] = {
152 static CPUReadMemoryFunc *PPC_intack_read[] = {
158 /* PowerPC control and status registers */
164 /* Control and status */
169 /* General purpose registers */
182 /* Error diagnostic */
185 static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
187 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
190 static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
192 #ifdef TARGET_WORDS_BIGENDIAN
193 value = bswap16(value);
195 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
198 static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
200 #ifdef TARGET_WORDS_BIGENDIAN
201 value = bswap32(value);
203 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
206 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
210 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
215 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
219 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
220 #ifdef TARGET_WORDS_BIGENDIAN
221 retval = bswap16(retval);
227 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
231 printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
232 #ifdef TARGET_WORDS_BIGENDIAN
233 retval = bswap32(retval);
239 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
245 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
252 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
253 typedef struct sysctrl_t {
263 STATE_HARDFILE = 0x01,
266 static sysctrl_t *sysctrl;
268 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
270 sysctrl_t *sysctrl = opaque;
272 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
273 sysctrl->fake_io[addr - 0x0398] = val;
276 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
278 sysctrl_t *sysctrl = opaque;
280 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
281 sysctrl->fake_io[addr - 0x0398]);
282 return sysctrl->fake_io[addr - 0x0398];
285 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
287 sysctrl_t *sysctrl = opaque;
289 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
292 /* Special port 92 */
293 /* Check soft reset asked */
295 // cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
305 /* Motorola CPU configuration register : read-only */
308 /* Motorola base module feature register : read-only */
311 /* Motorola base module status register : read-only */
314 /* Hardfile light register */
316 sysctrl->state |= STATE_HARDFILE;
318 sysctrl->state &= ~STATE_HARDFILE;
321 /* Password protect 1 register */
322 if (sysctrl->nvram != NULL)
323 m48t59_toggle_lock(sysctrl->nvram, 1);
326 /* Password protect 2 register */
327 if (sysctrl->nvram != NULL)
328 m48t59_toggle_lock(sysctrl->nvram, 2);
331 /* L2 invalidate register */
332 // tlb_flush(first_cpu, 1);
335 /* system control register */
336 sysctrl->syscontrol = val & 0x0F;
339 /* I/O map type register */
340 sysctrl->contiguous_map = val & 0x01;
343 printf("ERROR: unaffected IO port write: %04lx => %02x\n",
349 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
351 sysctrl_t *sysctrl = opaque;
352 uint32_t retval = 0xFF;
356 /* Special port 92 */
360 /* Motorola CPU configuration register */
361 retval = 0xEF; /* MPC750 */
364 /* Motorola Base module feature register */
365 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
368 /* Motorola base module status register */
369 retval = 0xE0; /* Standard MPC750 */
372 /* Equipment present register:
374 * no upgrade processor
375 * no cards in PCI slots
381 /* Motorola base module extended feature register */
382 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
385 /* L2 invalidate: don't care */
392 /* system control register
393 * 7 - 6 / 1 - 0: L2 cache enable
395 retval = sysctrl->syscontrol;
399 retval = 0x03; /* no L2 cache */
402 /* I/O map type register */
403 retval = sysctrl->contiguous_map;
406 printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
409 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
414 static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
415 target_phys_addr_t addr)
417 if (sysctrl->contiguous_map == 0) {
418 /* 64 KB contiguous space for IOs */
421 /* 8 MB non-contiguous space for IOs */
422 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
428 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
431 sysctrl_t *sysctrl = opaque;
433 addr = prep_IO_address(sysctrl, addr);
434 cpu_outb(NULL, addr, value);
437 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
439 sysctrl_t *sysctrl = opaque;
442 addr = prep_IO_address(sysctrl, addr);
443 ret = cpu_inb(NULL, addr);
448 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
451 sysctrl_t *sysctrl = opaque;
453 addr = prep_IO_address(sysctrl, addr);
454 #ifdef TARGET_WORDS_BIGENDIAN
455 value = bswap16(value);
457 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
458 cpu_outw(NULL, addr, value);
461 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
463 sysctrl_t *sysctrl = opaque;
466 addr = prep_IO_address(sysctrl, addr);
467 ret = cpu_inw(NULL, addr);
468 #ifdef TARGET_WORDS_BIGENDIAN
471 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
476 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
479 sysctrl_t *sysctrl = opaque;
481 addr = prep_IO_address(sysctrl, addr);
482 #ifdef TARGET_WORDS_BIGENDIAN
483 value = bswap32(value);
485 PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
486 cpu_outl(NULL, addr, value);
489 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
491 sysctrl_t *sysctrl = opaque;
494 addr = prep_IO_address(sysctrl, addr);
495 ret = cpu_inl(NULL, addr);
496 #ifdef TARGET_WORDS_BIGENDIAN
499 PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
504 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
510 CPUReadMemoryFunc *PPC_prep_io_read[] = {
516 #define NVRAM_SIZE 0x2000
518 /* PowerPC PREP hardware initialisation */
519 static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
520 DisplayState *ds, const char **fd_filename,
521 int snapshot, const char *kernel_filename,
522 const char *kernel_cmdline,
523 const char *initrd_filename,
524 const char *cpu_model)
530 int linux_boot, i, nb_nics1, bios_size;
531 unsigned long bios_offset;
532 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
536 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
540 linux_boot = (kernel_filename != NULL);
545 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
547 /* Default CPU is a 604 */
548 if (cpu_model == NULL)
550 ppc_find_by_name(cpu_model, &def);
552 cpu_abort(env, "Unable to find PowerPC CPU definition\n");
554 cpu_ppc_register(env, def);
555 /* Set time-base frequency to 100 Mhz */
556 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
559 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
561 /* allocate and load BIOS */
562 bios_offset = ram_size + vga_ram_size;
563 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
564 bios_size = load_image(buf, phys_ram_base + bios_offset);
565 if (bios_size < 0 || bios_size > BIOS_SIZE) {
566 fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
569 bios_size = (bios_size + 0xfff) & ~0xfff;
570 cpu_register_physical_memory((uint32_t)(-bios_size),
571 bios_size, bios_offset | IO_MEM_ROM);
574 kernel_base = KERNEL_LOAD_ADDR;
575 /* now we can load the kernel */
576 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
577 if (kernel_size < 0) {
578 fprintf(stderr, "qemu: could not load kernel '%s'\n",
583 if (initrd_filename) {
584 initrd_base = INITRD_LOAD_ADDR;
585 initrd_size = load_image(initrd_filename,
586 phys_ram_base + initrd_base);
587 if (initrd_size < 0) {
588 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
604 isa_mem_base = 0xc0000000;
605 pci_bus = pci_prep_init();
606 // pci_bus = i440fx_init();
607 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
608 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
609 PPC_prep_io_write, sysctrl);
610 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
612 /* init basic PC hardware */
613 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
616 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
617 isa_pic = pic_init(pic_irq_request, first_cpu);
618 // pit = pit_init(0x40, 0);
620 serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
622 if (nb_nics1 > NE2000_NB_MAX)
623 nb_nics1 = NE2000_NB_MAX;
624 for(i = 0; i < nb_nics1; i++) {
625 if (nd_table[0].model == NULL
626 || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
627 isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
629 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
634 for(i = 0; i < 2; i++) {
635 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
636 bs_table[2 * i], bs_table[2 * i + 1]);
643 fdctrl_init(6, 2, 0, 0x3f0, fd_table);
645 /* Register speaker port */
646 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
647 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
648 /* Register fake IO ports for PREP */
649 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
650 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
651 /* System control ports */
652 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
653 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
654 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
655 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
656 /* PCI intack location */
657 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
658 PPC_intack_write, NULL);
659 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
660 /* PowerPC control and status register group */
662 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
663 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
667 usb_ohci_init_pci(pci_bus, 3, -1);
670 nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
673 sysctrl->nvram = nvram;
675 /* Initialise NVRAM */
676 PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
677 kernel_base, kernel_size,
679 initrd_base, initrd_size,
680 /* XXX: need an option to load a NVRAM image */
682 graphic_width, graphic_height, graphic_depth);
684 /* Special port to get debug messages from Open-Firmware */
685 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
688 QEMUMachine prep_machine = {
690 "PowerPC PREP platform",