2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 //#define HARD_DEBUG_PPC_IO
36 //#define DEBUG_PPC_IO
38 /* SMP is not enabled, for now */
41 #define BIOS_FILENAME "ppc_rom.bin"
42 #define KERNEL_LOAD_ADDR 0x01000000
43 #define INITRD_LOAD_ADDR 0x01800000
48 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
52 #if defined (HARD_DEBUG_PPC_IO)
53 #define PPC_IO_DPRINTF(fmt, args...) \
55 if (loglevel & CPU_LOG_IOPORT) { \
56 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
58 printf("%s : " fmt, __func__ , ##args); \
61 #elif defined (DEBUG_PPC_IO)
62 #define PPC_IO_DPRINTF(fmt, args...) \
64 if (loglevel & CPU_LOG_IOPORT) { \
65 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
69 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
72 /* Constants for devices init */
73 static const int ide_iobase[2] = { 0x1f0, 0x170 };
74 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
75 static const int ide_irq[2] = { 13, 13 };
77 #define NE2000_NB_MAX 6
79 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
80 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
82 //static PITState *pit;
84 /* ISA IO ports bridge */
85 #define PPC_IO_BASE 0x80000000
87 /* Speaker port 0x61 */
89 int dummy_refresh_clock;
91 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
94 speaker_data_on = (val >> 1) & 1;
95 pit_set_gate(pit, 2, val & 1);
99 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
103 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
104 dummy_refresh_clock ^= 1;
105 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
106 (dummy_refresh_clock << 4);
111 /* PCI intack register */
112 /* Read-only register (?) */
113 static void _PPC_intack_write (void *opaque,
114 target_phys_addr_t addr, uint32_t value)
116 // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
119 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
123 if (addr == 0xBFFFFFF0)
124 retval = pic_intack_read(isa_pic);
125 // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
130 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
132 return _PPC_intack_read(addr);
135 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
137 #ifdef TARGET_WORDS_BIGENDIAN
138 return bswap16(_PPC_intack_read(addr));
140 return _PPC_intack_read(addr);
144 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
146 #ifdef TARGET_WORDS_BIGENDIAN
147 return bswap32(_PPC_intack_read(addr));
149 return _PPC_intack_read(addr);
153 static CPUWriteMemoryFunc *PPC_intack_write[] = {
159 static CPUReadMemoryFunc *PPC_intack_read[] = {
165 /* PowerPC control and status registers */
171 /* Control and status */
176 /* General purpose registers */
189 /* Error diagnostic */
192 static void PPC_XCSR_writeb (void *opaque,
193 target_phys_addr_t addr, uint32_t value)
195 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
198 static void PPC_XCSR_writew (void *opaque,
199 target_phys_addr_t addr, uint32_t value)
201 #ifdef TARGET_WORDS_BIGENDIAN
202 value = bswap16(value);
204 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
207 static void PPC_XCSR_writel (void *opaque,
208 target_phys_addr_t addr, uint32_t value)
210 #ifdef TARGET_WORDS_BIGENDIAN
211 value = bswap32(value);
213 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
216 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
220 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
225 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
229 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
230 #ifdef TARGET_WORDS_BIGENDIAN
231 retval = bswap16(retval);
237 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
241 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
242 #ifdef TARGET_WORDS_BIGENDIAN
243 retval = bswap32(retval);
249 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
255 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
262 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
263 typedef struct sysctrl_t {
274 STATE_HARDFILE = 0x01,
277 static sysctrl_t *sysctrl;
279 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
281 sysctrl_t *sysctrl = opaque;
283 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
285 sysctrl->fake_io[addr - 0x0398] = val;
288 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
290 sysctrl_t *sysctrl = opaque;
292 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
293 sysctrl->fake_io[addr - 0x0398]);
294 return sysctrl->fake_io[addr - 0x0398];
297 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
299 sysctrl_t *sysctrl = opaque;
301 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
302 addr - PPC_IO_BASE, val);
305 /* Special port 92 */
306 /* Check soft reset asked */
308 qemu_irq_raise(sysctrl->reset_irq);
310 qemu_irq_lower(sysctrl->reset_irq);
320 /* Motorola CPU configuration register : read-only */
323 /* Motorola base module feature register : read-only */
326 /* Motorola base module status register : read-only */
329 /* Hardfile light register */
331 sysctrl->state |= STATE_HARDFILE;
333 sysctrl->state &= ~STATE_HARDFILE;
336 /* Password protect 1 register */
337 if (sysctrl->nvram != NULL)
338 m48t59_toggle_lock(sysctrl->nvram, 1);
341 /* Password protect 2 register */
342 if (sysctrl->nvram != NULL)
343 m48t59_toggle_lock(sysctrl->nvram, 2);
346 /* L2 invalidate register */
347 // tlb_flush(first_cpu, 1);
350 /* system control register */
351 sysctrl->syscontrol = val & 0x0F;
354 /* I/O map type register */
355 sysctrl->contiguous_map = val & 0x01;
358 printf("ERROR: unaffected IO port write: %04" PRIx32
359 " => %02" PRIx32"\n", addr, val);
364 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
366 sysctrl_t *sysctrl = opaque;
367 uint32_t retval = 0xFF;
371 /* Special port 92 */
375 /* Motorola CPU configuration register */
376 retval = 0xEF; /* MPC750 */
379 /* Motorola Base module feature register */
380 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
383 /* Motorola base module status register */
384 retval = 0xE0; /* Standard MPC750 */
387 /* Equipment present register:
389 * no upgrade processor
390 * no cards in PCI slots
396 /* Motorola base module extended feature register */
397 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
400 /* L2 invalidate: don't care */
407 /* system control register
408 * 7 - 6 / 1 - 0: L2 cache enable
410 retval = sysctrl->syscontrol;
414 retval = 0x03; /* no L2 cache */
417 /* I/O map type register */
418 retval = sysctrl->contiguous_map;
421 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
424 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
425 addr - PPC_IO_BASE, retval);
430 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
434 if (sysctrl->contiguous_map == 0) {
435 /* 64 KB contiguous space for IOs */
438 /* 8 MB non-contiguous space for IOs */
439 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
445 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
448 sysctrl_t *sysctrl = opaque;
450 addr = prep_IO_address(sysctrl, addr);
451 cpu_outb(NULL, addr, value);
454 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
456 sysctrl_t *sysctrl = opaque;
459 addr = prep_IO_address(sysctrl, addr);
460 ret = cpu_inb(NULL, addr);
465 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
468 sysctrl_t *sysctrl = opaque;
470 addr = prep_IO_address(sysctrl, addr);
471 #ifdef TARGET_WORDS_BIGENDIAN
472 value = bswap16(value);
474 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
475 cpu_outw(NULL, addr, value);
478 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
480 sysctrl_t *sysctrl = opaque;
483 addr = prep_IO_address(sysctrl, addr);
484 ret = cpu_inw(NULL, addr);
485 #ifdef TARGET_WORDS_BIGENDIAN
488 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
493 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
496 sysctrl_t *sysctrl = opaque;
498 addr = prep_IO_address(sysctrl, addr);
499 #ifdef TARGET_WORDS_BIGENDIAN
500 value = bswap32(value);
502 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
503 cpu_outl(NULL, addr, value);
506 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
508 sysctrl_t *sysctrl = opaque;
511 addr = prep_IO_address(sysctrl, addr);
512 ret = cpu_inl(NULL, addr);
513 #ifdef TARGET_WORDS_BIGENDIAN
516 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
521 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
527 CPUReadMemoryFunc *PPC_prep_io_read[] = {
533 #define NVRAM_SIZE 0x2000
535 /* PowerPC PREP hardware initialisation */
536 static void ppc_prep_init (int ram_size, int vga_ram_size,
537 const char *boot_device, DisplayState *ds,
538 const char *kernel_filename,
539 const char *kernel_cmdline,
540 const char *initrd_filename,
541 const char *cpu_model)
543 CPUState *env = NULL, *envs[MAX_CPUS];
548 int linux_boot, i, nb_nics1, bios_size;
549 unsigned long bios_offset;
550 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
555 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
559 linux_boot = (kernel_filename != NULL);
562 if (cpu_model == NULL)
563 cpu_model = "default";
564 for (i = 0; i < smp_cpus; i++) {
565 env = cpu_init(cpu_model);
567 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
570 if (env->flags & POWERPC_FLAG_RTC_CLK) {
571 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
572 cpu_ppc_tb_init(env, 7812500UL);
574 /* Set time-base frequency to 100 Mhz */
575 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
577 qemu_register_reset(&cpu_ppc_reset, env);
578 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
583 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
585 /* allocate and load BIOS */
586 bios_offset = ram_size + vga_ram_size;
587 if (bios_name == NULL)
588 bios_name = BIOS_FILENAME;
589 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
590 bios_size = load_image(buf, phys_ram_base + bios_offset);
591 if (bios_size < 0 || bios_size > BIOS_SIZE) {
592 cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
595 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
596 cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
598 bios_size = (bios_size + 0xfff) & ~0xfff;
599 cpu_register_physical_memory((uint32_t)(-bios_size),
600 bios_size, bios_offset | IO_MEM_ROM);
603 kernel_base = KERNEL_LOAD_ADDR;
604 /* now we can load the kernel */
605 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
606 if (kernel_size < 0) {
607 cpu_abort(env, "qemu: could not load kernel '%s'\n",
612 if (initrd_filename) {
613 initrd_base = INITRD_LOAD_ADDR;
614 initrd_size = load_image(initrd_filename,
615 phys_ram_base + initrd_base);
616 if (initrd_size < 0) {
617 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
625 ppc_boot_device = 'm';
631 ppc_boot_device = '\0';
632 /* For now, OHW cannot boot from the network. */
633 for (i = 0; boot_device[i] != '\0'; i++) {
634 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
635 ppc_boot_device = boot_device[i];
639 if (ppc_boot_device == '\0') {
640 fprintf(stderr, "No valid boot device for Mac99 machine\n");
645 isa_mem_base = 0xc0000000;
646 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
647 cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
650 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
651 pci_bus = pci_prep_init(i8259);
652 // pci_bus = i440fx_init();
653 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
654 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
655 PPC_prep_io_write, sysctrl);
656 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
658 /* init basic PC hardware */
659 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
661 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
662 // pit = pit_init(0x40, i8259[0]);
663 rtc_init(0x70, i8259[8]);
665 serial_init(0x3f8, i8259[4], serial_hds[0]);
667 if (nb_nics1 > NE2000_NB_MAX)
668 nb_nics1 = NE2000_NB_MAX;
669 for(i = 0; i < nb_nics1; i++) {
670 if (nd_table[i].model == NULL
671 || strcmp(nd_table[i].model, "ne2k_isa") == 0) {
672 isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
674 pci_nic_init(pci_bus, &nd_table[i], -1);
678 for(i = 0; i < 2; i++) {
679 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
680 bs_table[2 * i], bs_table[2 * i + 1]);
682 i8042_init(i8259[1], i8259[12], 0x60);
687 fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
689 /* Register speaker port */
690 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
691 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
692 /* Register fake IO ports for PREP */
693 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
694 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
695 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
696 /* System control ports */
697 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
698 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
699 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
700 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
701 /* PCI intack location */
702 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
703 PPC_intack_write, NULL);
704 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
705 /* PowerPC control and status register group */
707 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
709 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
713 usb_ohci_init_pci(pci_bus, 3, -1);
716 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
719 sysctrl->nvram = m48t59;
721 /* Initialise NVRAM */
722 nvram.opaque = m48t59;
723 nvram.read_fn = &m48t59_read;
724 nvram.write_fn = &m48t59_write;
725 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
726 kernel_base, kernel_size,
728 initrd_base, initrd_size,
729 /* XXX: need an option to load a NVRAM image */
731 graphic_width, graphic_height, graphic_depth);
733 /* Special port to get debug messages from Open-Firmware */
734 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
737 QEMUMachine prep_machine = {
739 "PowerPC PREP platform",