2 * QEMU RTL8139 emulation
4 * Copyright (c) 2006 Igor Kovalenko
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
48 #include "qemu-timer.h"
51 /* debug RTL8139 card */
52 //#define DEBUG_RTL8139 1
54 #define PCI_FREQUENCY 33000000L
56 /* debug RTL8139 card C+ mode only */
57 //#define DEBUG_RTL8139CP 1
59 /* Calculate CRCs properly on Rx packets */
60 #define RTL8139_CALCULATE_RXCRC 1
62 /* Uncomment to enable on-board timer interrupts */
63 //#define RTL8139_ONBOARD_TIMER 1
65 #if defined(RTL8139_CALCULATE_RXCRC)
70 #define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
73 /* arg % size for size which is a power of 2 */
74 #define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
77 #if defined (DEBUG_RTL8139)
78 # define DEBUG_PRINT(x) do { printf x ; } while (0)
80 # define DEBUG_PRINT(x)
83 /* Symbolic offsets to registers. */
84 enum RTL8139_registers {
85 MAC0 = 0, /* Ethernet hardware address. */
86 MAR0 = 8, /* Multicast filter. */
87 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
88 /* Dump Tally Conter control register(64bit). C+ mode only */
89 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
98 Timer = 0x48, /* A general-purpose counter. */
99 RxMissed = 0x4C, /* 24 bits valid, write clears. */
106 Config4 = 0x5A, /* absent on RTL-8139A */
109 PCIRevisionID = 0x5E,
110 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
111 BasicModeCtrl = 0x62,
112 BasicModeStatus = 0x64,
115 NWayExpansion = 0x6A,
116 /* Undocumented registers, but required for proper operation. */
117 FIFOTMS = 0x70, /* FIFO Control and test. */
118 CSCR = 0x74, /* Chip Status and Configuration Register. */
120 PARA7c = 0x7c, /* Magic transceiver parameter register. */
121 Config5 = 0xD8, /* absent on RTL-8139A */
123 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
124 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
125 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
126 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
127 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
128 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
129 TxThresh = 0xEC, /* Early Tx threshold */
133 MultiIntrClear = 0xF000,
135 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
147 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
148 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
153 /* Interrupt register bits, using my own meaningful names. */
154 enum IntrStatusBits {
165 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
172 TxOutOfWindow = 0x20000000,
173 TxAborted = 0x40000000,
174 TxCarrierLost = 0x80000000,
177 RxMulticast = 0x8000,
179 RxBroadcast = 0x2000,
180 RxBadSymbol = 0x0020,
188 /* Bits in RxConfig. */
192 AcceptBroadcast = 0x08,
193 AcceptMulticast = 0x04,
195 AcceptAllPhys = 0x01,
198 /* Bits in TxConfig. */
199 enum tx_config_bits {
201 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
203 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
204 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
205 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
206 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
208 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
209 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
210 TxClearAbt = (1 << 0), /* Clear abort (WO) */
211 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
212 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
214 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
218 /* Transmit Status of All Descriptors (TSAD) Register */
220 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
221 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
222 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
223 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
224 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
225 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
226 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
227 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
228 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
229 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
230 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
231 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
232 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
233 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
234 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
235 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
239 /* Bits in Config1 */
241 Cfg1_PM_Enable = 0x01,
242 Cfg1_VPD_Enable = 0x02,
245 LWAKE = 0x10, /* not on 8139, 8139A */
246 Cfg1_Driver_Load = 0x20,
249 SLEEP = (1 << 1), /* only on 8139, 8139A */
250 PWRDN = (1 << 0), /* only on 8139, 8139A */
253 /* Bits in Config3 */
255 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
256 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
257 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
258 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
259 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
260 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
261 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
262 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
265 /* Bits in Config4 */
267 LWPTN = (1 << 2), /* not on 8139, 8139A */
270 /* Bits in Config5 */
272 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
273 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
274 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
275 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
276 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
277 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
278 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
282 /* rx fifo threshold */
284 RxCfgFIFONone = (7 << RxCfgFIFOShift),
288 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
290 /* rx ring buffer length */
292 RxCfgRcv16K = (1 << 11),
293 RxCfgRcv32K = (1 << 12),
294 RxCfgRcv64K = (1 << 11) | (1 << 12),
296 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
300 /* Twister tuning parameters from RealTek.
301 Completely undocumented, but required to tune bad links on some boards. */
304 CSCR_LinkOKBit = 0x0400,
305 CSCR_LinkChangeBit = 0x0800,
306 CSCR_LinkStatusBits = 0x0f000,
307 CSCR_LinkDownOffCmd = 0x003c0,
308 CSCR_LinkDownCmd = 0x0f3c0,
311 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
312 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
313 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
314 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
315 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
316 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
317 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
318 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
319 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
324 Cfg9346_Unlock = 0xC0,
341 HasHltClk = (1 << 0),
345 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
346 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
347 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
349 #define RTL8139_PCI_REVID_8139 0x10
350 #define RTL8139_PCI_REVID_8139CPLUS 0x20
352 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
354 /* Size is 64 * 16bit words */
355 #define EEPROM_9346_ADDR_BITS 6
356 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
357 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
359 enum Chip9346Operation
361 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
362 Chip9346_op_read = 0x80, /* 10 AAAAAA */
363 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
364 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
365 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
366 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
367 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
373 Chip9346_enter_command_mode,
374 Chip9346_read_command,
375 Chip9346_data_read, /* from output register */
376 Chip9346_data_write, /* to input register, then to contents at specified address */
377 Chip9346_data_write_all, /* to input register, then filling contents */
380 typedef struct EEprom9346
382 uint16_t contents[EEPROM_9346_SIZE];
395 typedef struct RTL8139TallyCounters
411 } RTL8139TallyCounters;
413 /* Clears all tally counters */
414 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
416 /* Writes tally counters to specified physical memory address */
417 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
419 /* Loads values of tally counters from VM state file */
420 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
422 /* Saves values of tally counters to VM state file */
423 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
425 typedef struct RTL8139State {
426 uint8_t phys[8]; /* mac address */
427 uint8_t mult[8]; /* multicast mask array */
429 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
430 uint32_t TxAddr[4]; /* TxAddr0 */
431 uint32_t RxBuf; /* Receive buffer */
432 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
452 uint8_t clock_enabled;
453 uint8_t bChipCmdState;
457 uint16_t BasicModeCtrl;
458 uint16_t BasicModeStatus;
461 uint16_t NWayExpansion;
469 int rtl8139_mmio_io_addr;
475 uint32_t currCPlusRxDesc;
476 uint32_t currCPlusTxDesc;
478 uint32_t RxRingAddrLO;
479 uint32_t RxRingAddrHI;
488 RTL8139TallyCounters tally_counters;
490 /* Non-persistent data */
491 uint8_t *cplus_txbuffer;
492 int cplus_txbuffer_len;
493 int cplus_txbuffer_offset;
495 /* PCI interrupt timer */
500 void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
502 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
504 switch (command & Chip9346_op_mask)
506 case Chip9346_op_read:
508 eeprom->address = command & EEPROM_9346_ADDR_MASK;
509 eeprom->output = eeprom->contents[eeprom->address];
512 eeprom->mode = Chip9346_data_read;
513 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
514 eeprom->address, eeprom->output));
518 case Chip9346_op_write:
520 eeprom->address = command & EEPROM_9346_ADDR_MASK;
523 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
524 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
529 eeprom->mode = Chip9346_none;
530 switch (command & Chip9346_op_ext_mask)
532 case Chip9346_op_write_enable:
533 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
535 case Chip9346_op_write_all:
536 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
538 case Chip9346_op_write_disable:
539 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
546 void prom9346_shift_clock(EEprom9346 *eeprom)
548 int bit = eeprom->eedi?1:0;
552 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
554 switch (eeprom->mode)
556 case Chip9346_enter_command_mode:
559 eeprom->mode = Chip9346_read_command;
562 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
566 case Chip9346_read_command:
567 eeprom->input = (eeprom->input << 1) | (bit & 1);
568 if (eeprom->tick == 8)
570 prom9346_decode_command(eeprom, eeprom->input & 0xff);
574 case Chip9346_data_read:
575 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
576 eeprom->output <<= 1;
577 if (eeprom->tick == 16)
580 // the FreeBSD drivers (rl and re) don't explicitly toggle
581 // CS between reads (or does setting Cfg9346 to 0 count too?),
582 // so we need to enter wait-for-command state here
583 eeprom->mode = Chip9346_enter_command_mode;
587 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
589 // original behaviour
591 eeprom->address &= EEPROM_9346_ADDR_MASK;
592 eeprom->output = eeprom->contents[eeprom->address];
595 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
596 eeprom->address, eeprom->output));
601 case Chip9346_data_write:
602 eeprom->input = (eeprom->input << 1) | (bit & 1);
603 if (eeprom->tick == 16)
605 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
606 eeprom->address, eeprom->input));
608 eeprom->contents[eeprom->address] = eeprom->input;
609 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
615 case Chip9346_data_write_all:
616 eeprom->input = (eeprom->input << 1) | (bit & 1);
617 if (eeprom->tick == 16)
620 for (i = 0; i < EEPROM_9346_SIZE; i++)
622 eeprom->contents[i] = eeprom->input;
624 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
627 eeprom->mode = Chip9346_enter_command_mode;
638 int prom9346_get_wire(RTL8139State *s)
640 EEprom9346 *eeprom = &s->eeprom;
647 void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
649 EEprom9346 *eeprom = &s->eeprom;
650 uint8_t old_eecs = eeprom->eecs;
651 uint8_t old_eesk = eeprom->eesk;
657 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
658 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
660 if (!old_eecs && eecs)
662 /* Synchronize start */
666 eeprom->mode = Chip9346_enter_command_mode;
668 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
673 DEBUG_PRINT(("=== eeprom: end access\n"));
677 if (!old_eesk && eesk)
680 prom9346_shift_clock(eeprom);
684 static void rtl8139_update_irq(RTL8139State *s)
687 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
689 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
690 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
692 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
695 #define POLYNOMIAL 0x04c11db6
699 static int compute_mcast_idx(const uint8_t *ep)
706 for (i = 0; i < 6; i++) {
708 for (j = 0; j < 8; j++) {
709 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
713 crc = ((crc ^ POLYNOMIAL) | carry);
719 static int rtl8139_RxWrap(RTL8139State *s)
721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
722 return (s->RxConfig & (1 << 7));
725 static int rtl8139_receiver_enabled(RTL8139State *s)
727 return s->bChipCmdState & CmdRxEnb;
730 static int rtl8139_transmitter_enabled(RTL8139State *s)
732 return s->bChipCmdState & CmdTxEnb;
735 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
737 return s->CpCmd & CPlusRxEnb;
740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
742 return s->CpCmd & CPlusTxEnb;
745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
747 if (s->RxBufAddr + size > s->RxBufferSize)
749 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
751 /* write packet data */
752 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
754 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
758 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
762 /* reset buffer pointer */
765 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
766 buf + (size-wrapped), wrapped );
768 s->RxBufAddr = wrapped;
774 /* non-wrapping path or overwrapping enabled */
775 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
777 s->RxBufAddr += size;
780 #define MIN_BUF_SIZE 60
781 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
783 #if TARGET_PHYS_ADDR_BITS > 32
784 return low | ((target_phys_addr_t)high << 32);
790 static int rtl8139_can_receive(void *opaque)
792 RTL8139State *s = opaque;
795 /* Receive (drop) packets if card is disabled. */
796 if (!s->clock_enabled)
798 if (!rtl8139_receiver_enabled(s))
801 if (rtl8139_cp_receiver_enabled(s)) {
802 /* ??? Flow control not implemented in c+ mode.
803 This is a hack to work around slirp deficiencies anyway. */
806 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
808 return (avail == 0 || avail >= 1514);
812 static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
814 RTL8139State *s = opaque;
816 uint32_t packet_header = 0;
819 static const uint8_t broadcast_macaddr[6] =
820 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
822 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
824 /* test if board clock is stopped */
825 if (!s->clock_enabled)
827 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
831 /* first check if receiver is enabled */
833 if (!rtl8139_receiver_enabled(s))
835 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
839 /* XXX: check this */
840 if (s->RxConfig & AcceptAllPhys) {
841 /* promiscuous: receive all */
842 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
845 if (!memcmp(buf, broadcast_macaddr, 6)) {
846 /* broadcast address */
847 if (!(s->RxConfig & AcceptBroadcast))
849 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
851 /* update tally counter */
852 ++s->tally_counters.RxERR;
857 packet_header |= RxBroadcast;
859 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
861 /* update tally counter */
862 ++s->tally_counters.RxOkBrd;
864 } else if (buf[0] & 0x01) {
866 if (!(s->RxConfig & AcceptMulticast))
868 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
876 int mcast_idx = compute_mcast_idx(buf);
878 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
880 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
882 /* update tally counter */
883 ++s->tally_counters.RxERR;
888 packet_header |= RxMulticast;
890 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
892 /* update tally counter */
893 ++s->tally_counters.RxOkMul;
895 } else if (s->phys[0] == buf[0] &&
896 s->phys[1] == buf[1] &&
897 s->phys[2] == buf[2] &&
898 s->phys[3] == buf[3] &&
899 s->phys[4] == buf[4] &&
900 s->phys[5] == buf[5]) {
902 if (!(s->RxConfig & AcceptMyPhys))
904 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
906 /* update tally counter */
907 ++s->tally_counters.RxERR;
912 packet_header |= RxPhysical;
914 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
916 /* update tally counter */
917 ++s->tally_counters.RxOkPhy;
921 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
923 /* update tally counter */
924 ++s->tally_counters.RxERR;
930 /* if too small buffer, then expand it */
931 if (size < MIN_BUF_SIZE) {
932 memcpy(buf1, buf, size);
933 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
938 if (rtl8139_cp_receiver_enabled(s))
940 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
942 /* begin C+ receiver mode */
944 /* w0 ownership flag */
945 #define CP_RX_OWN (1<<31)
946 /* w0 end of ring flag */
947 #define CP_RX_EOR (1<<30)
948 /* w0 bits 0...12 : buffer size */
949 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
950 /* w1 tag available flag */
951 #define CP_RX_TAVA (1<<16)
952 /* w1 bits 0...15 : VLAN tag */
953 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
954 /* w2 low 32bit of Rx buffer ptr */
955 /* w3 high 32bit of Rx buffer ptr */
957 int descriptor = s->currCPlusRxDesc;
958 target_phys_addr_t cplus_rx_ring_desc;
960 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
961 cplus_rx_ring_desc += 16 * descriptor;
963 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
964 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
966 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
968 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
969 rxdw0 = le32_to_cpu(val);
970 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
971 rxdw1 = le32_to_cpu(val);
972 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
973 rxbufLO = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
975 rxbufHI = le32_to_cpu(val);
977 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
979 rxdw0, rxdw1, rxbufLO, rxbufHI));
981 if (!(rxdw0 & CP_RX_OWN))
983 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
985 s->IntrStatus |= RxOverflow;
988 /* update tally counter */
989 ++s->tally_counters.RxERR;
990 ++s->tally_counters.MissPkt;
992 rtl8139_update_irq(s);
996 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
998 /* TODO: scatter the packet over available receive ring descriptors space */
1000 if (size+4 > rx_space)
1002 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1003 descriptor, rx_space, size));
1005 s->IntrStatus |= RxOverflow;
1008 /* update tally counter */
1009 ++s->tally_counters.RxERR;
1010 ++s->tally_counters.MissPkt;
1012 rtl8139_update_irq(s);
1016 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1018 /* receive/copy to target memory */
1019 cpu_physical_memory_write( rx_addr, buf, size );
1021 if (s->CpCmd & CPlusRxChkSum)
1023 /* do some packet checksumming */
1026 /* write checksum */
1027 #if defined (RTL8139_CALCULATE_RXCRC)
1028 val = cpu_to_le32(crc32(0, buf, size));
1032 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1034 /* first segment of received packet flag */
1035 #define CP_RX_STATUS_FS (1<<29)
1036 /* last segment of received packet flag */
1037 #define CP_RX_STATUS_LS (1<<28)
1038 /* multicast packet flag */
1039 #define CP_RX_STATUS_MAR (1<<26)
1040 /* physical-matching packet flag */
1041 #define CP_RX_STATUS_PAM (1<<25)
1042 /* broadcast packet flag */
1043 #define CP_RX_STATUS_BAR (1<<24)
1044 /* runt packet flag */
1045 #define CP_RX_STATUS_RUNT (1<<19)
1046 /* crc error flag */
1047 #define CP_RX_STATUS_CRC (1<<18)
1048 /* IP checksum error flag */
1049 #define CP_RX_STATUS_IPF (1<<15)
1050 /* UDP checksum error flag */
1051 #define CP_RX_STATUS_UDPF (1<<14)
1052 /* TCP checksum error flag */
1053 #define CP_RX_STATUS_TCPF (1<<13)
1055 /* transfer ownership to target */
1056 rxdw0 &= ~CP_RX_OWN;
1058 /* set first segment bit */
1059 rxdw0 |= CP_RX_STATUS_FS;
1061 /* set last segment bit */
1062 rxdw0 |= CP_RX_STATUS_LS;
1064 /* set received packet type flags */
1065 if (packet_header & RxBroadcast)
1066 rxdw0 |= CP_RX_STATUS_BAR;
1067 if (packet_header & RxMulticast)
1068 rxdw0 |= CP_RX_STATUS_MAR;
1069 if (packet_header & RxPhysical)
1070 rxdw0 |= CP_RX_STATUS_PAM;
1072 /* set received size */
1073 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1076 /* reset VLAN tag flag */
1077 rxdw1 &= ~CP_RX_TAVA;
1079 /* update ring data */
1080 val = cpu_to_le32(rxdw0);
1081 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1082 val = cpu_to_le32(rxdw1);
1083 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1085 /* update tally counter */
1086 ++s->tally_counters.RxOk;
1088 /* seek to next Rx descriptor */
1089 if (rxdw0 & CP_RX_EOR)
1091 s->currCPlusRxDesc = 0;
1095 ++s->currCPlusRxDesc;
1098 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1103 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1105 /* begin ring receiver mode */
1106 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1108 /* if receiver buffer is empty then avail == 0 */
1110 if (avail != 0 && size + 8 >= avail)
1112 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1113 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1115 s->IntrStatus |= RxOverflow;
1117 rtl8139_update_irq(s);
1121 packet_header |= RxStatusOK;
1123 packet_header |= (((size+4) << 16) & 0xffff0000);
1126 uint32_t val = cpu_to_le32(packet_header);
1128 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1130 rtl8139_write_buffer(s, buf, size);
1132 /* write checksum */
1133 #if defined (RTL8139_CALCULATE_RXCRC)
1134 val = cpu_to_le32(crc32(0, buf, size));
1139 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1141 /* correct buffer write pointer */
1142 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1144 /* now we can signal we have received something */
1146 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1147 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1150 s->IntrStatus |= RxOK;
1154 rtl8139_update_irq(s);
1158 static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1160 rtl8139_do_receive(opaque, buf, size, 1);
1163 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1165 s->RxBufferSize = bufferSize;
1170 static void rtl8139_reset(RTL8139State *s)
1174 /* restore MAC address */
1175 memcpy(s->phys, s->macaddr, 6);
1177 /* reset interrupt mask */
1181 rtl8139_update_irq(s);
1183 /* prepare eeprom */
1184 s->eeprom.contents[0] = 0x8129;
1186 // PCI vendor and device ID should be mirrored here
1187 s->eeprom.contents[1] = 0x10ec;
1188 s->eeprom.contents[2] = 0x8139;
1191 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1192 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1193 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
1195 /* mark all status registers as owned by host */
1196 for (i = 0; i < 4; ++i)
1198 s->TxStatus[i] = TxHostOwns;
1202 s->currCPlusRxDesc = 0;
1203 s->currCPlusTxDesc = 0;
1205 s->RxRingAddrLO = 0;
1206 s->RxRingAddrHI = 0;
1210 rtl8139_reset_rxring(s, 8192);
1216 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1217 s->clock_enabled = 0;
1219 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1220 s->clock_enabled = 1;
1223 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1225 /* set initial state data */
1226 s->Config0 = 0x0; /* No boot ROM */
1227 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1228 s->Config3 = 0x1; /* fast back-to-back compatible */
1231 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1233 s->CpCmd = 0x0; /* reset C+ mode */
1235 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1236 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1237 s->BasicModeCtrl = 0x1000; // autonegotiation
1239 s->BasicModeStatus = 0x7809;
1240 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1241 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1242 s->BasicModeStatus |= 0x0004; /* link is up */
1244 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1245 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1246 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1248 /* also reset timer and disable timer interrupt */
1253 /* reset tally counters */
1254 RTL8139TallyCounters_clear(&s->tally_counters);
1257 void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1261 counters->TxERR = 0;
1262 counters->RxERR = 0;
1263 counters->MissPkt = 0;
1265 counters->Tx1Col = 0;
1266 counters->TxMCol = 0;
1267 counters->RxOkPhy = 0;
1268 counters->RxOkBrd = 0;
1269 counters->RxOkMul = 0;
1270 counters->TxAbt = 0;
1271 counters->TxUndrn = 0;
1274 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1280 val64 = cpu_to_le64(tally_counters->TxOk);
1281 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1283 val64 = cpu_to_le64(tally_counters->RxOk);
1284 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1286 val64 = cpu_to_le64(tally_counters->TxERR);
1287 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1289 val32 = cpu_to_le32(tally_counters->RxERR);
1290 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1292 val16 = cpu_to_le16(tally_counters->MissPkt);
1293 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1295 val16 = cpu_to_le16(tally_counters->FAE);
1296 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1298 val32 = cpu_to_le32(tally_counters->Tx1Col);
1299 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1301 val32 = cpu_to_le32(tally_counters->TxMCol);
1302 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1304 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1305 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1307 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1308 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1310 val32 = cpu_to_le32(tally_counters->RxOkMul);
1311 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1313 val16 = cpu_to_le16(tally_counters->TxAbt);
1314 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1316 val16 = cpu_to_le16(tally_counters->TxUndrn);
1317 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1320 /* Loads values of tally counters from VM state file */
1321 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1323 qemu_get_be64s(f, &tally_counters->TxOk);
1324 qemu_get_be64s(f, &tally_counters->RxOk);
1325 qemu_get_be64s(f, &tally_counters->TxERR);
1326 qemu_get_be32s(f, &tally_counters->RxERR);
1327 qemu_get_be16s(f, &tally_counters->MissPkt);
1328 qemu_get_be16s(f, &tally_counters->FAE);
1329 qemu_get_be32s(f, &tally_counters->Tx1Col);
1330 qemu_get_be32s(f, &tally_counters->TxMCol);
1331 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1332 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1333 qemu_get_be32s(f, &tally_counters->RxOkMul);
1334 qemu_get_be16s(f, &tally_counters->TxAbt);
1335 qemu_get_be16s(f, &tally_counters->TxUndrn);
1338 /* Saves values of tally counters to VM state file */
1339 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1341 qemu_put_be64s(f, &tally_counters->TxOk);
1342 qemu_put_be64s(f, &tally_counters->RxOk);
1343 qemu_put_be64s(f, &tally_counters->TxERR);
1344 qemu_put_be32s(f, &tally_counters->RxERR);
1345 qemu_put_be16s(f, &tally_counters->MissPkt);
1346 qemu_put_be16s(f, &tally_counters->FAE);
1347 qemu_put_be32s(f, &tally_counters->Tx1Col);
1348 qemu_put_be32s(f, &tally_counters->TxMCol);
1349 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1350 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1351 qemu_put_be32s(f, &tally_counters->RxOkMul);
1352 qemu_put_be16s(f, &tally_counters->TxAbt);
1353 qemu_put_be16s(f, &tally_counters->TxUndrn);
1356 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1360 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1364 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1369 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1371 s->currCPlusRxDesc = 0;
1375 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1377 s->currCPlusTxDesc = 0;
1380 /* mask unwriteable bits */
1381 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1383 /* Deassert reset pin before next read */
1386 s->bChipCmdState = val;
1389 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1391 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1395 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1399 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1404 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1406 uint32_t ret = s->bChipCmdState;
1408 if (rtl8139_RxBufferEmpty(s))
1411 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1416 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1420 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1422 /* mask unwriteable bits */
1423 val = SET_MASKED(val, 0xff84, s->CpCmd);
1428 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1430 uint32_t ret = s->CpCmd;
1432 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1437 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1439 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1442 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1446 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1451 int rtl8139_config_writeable(RTL8139State *s)
1453 if (s->Cfg9346 & Cfg9346_Unlock)
1458 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1463 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1467 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1469 /* mask unwriteable bits */
1470 uint32_t mask = 0x4cff;
1472 if (1 || !rtl8139_config_writeable(s))
1474 /* Speed setting and autonegotiation enable bits are read-only */
1476 /* Duplex mode setting is read-only */
1480 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1482 s->BasicModeCtrl = val;
1485 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1487 uint32_t ret = s->BasicModeCtrl;
1489 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1494 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1498 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1500 /* mask unwriteable bits */
1501 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1503 s->BasicModeStatus = val;
1506 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1508 uint32_t ret = s->BasicModeStatus;
1510 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1515 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1519 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1521 /* mask unwriteable bits */
1522 val = SET_MASKED(val, 0x31, s->Cfg9346);
1524 uint32_t opmode = val & 0xc0;
1525 uint32_t eeprom_val = val & 0xf;
1527 if (opmode == 0x80) {
1529 int eecs = (eeprom_val & 0x08)?1:0;
1530 int eesk = (eeprom_val & 0x04)?1:0;
1531 int eedi = (eeprom_val & 0x02)?1:0;
1532 prom9346_set_wire(s, eecs, eesk, eedi);
1533 } else if (opmode == 0x40) {
1542 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1544 uint32_t ret = s->Cfg9346;
1546 uint32_t opmode = ret & 0xc0;
1551 int eedo = prom9346_get_wire(s);
1562 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1567 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1571 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1573 if (!rtl8139_config_writeable(s))
1576 /* mask unwriteable bits */
1577 val = SET_MASKED(val, 0xf8, s->Config0);
1582 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1584 uint32_t ret = s->Config0;
1586 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1591 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1595 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1597 if (!rtl8139_config_writeable(s))
1600 /* mask unwriteable bits */
1601 val = SET_MASKED(val, 0xC, s->Config1);
1606 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1608 uint32_t ret = s->Config1;
1610 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1615 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1619 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1621 if (!rtl8139_config_writeable(s))
1624 /* mask unwriteable bits */
1625 val = SET_MASKED(val, 0x8F, s->Config3);
1630 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1632 uint32_t ret = s->Config3;
1634 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1639 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1643 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1645 if (!rtl8139_config_writeable(s))
1648 /* mask unwriteable bits */
1649 val = SET_MASKED(val, 0x0a, s->Config4);
1654 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1656 uint32_t ret = s->Config4;
1658 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1663 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1667 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1669 /* mask unwriteable bits */
1670 val = SET_MASKED(val, 0x80, s->Config5);
1675 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1677 uint32_t ret = s->Config5;
1679 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1684 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1686 if (!rtl8139_transmitter_enabled(s))
1688 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1692 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1694 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1699 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1701 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1703 uint32_t tc = s->TxConfig;
1705 tc |= (val & 0x000000FF);
1706 rtl8139_TxConfig_write(s, tc);
1709 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1711 uint32_t ret = s->TxConfig;
1713 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1718 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1720 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1722 /* mask unwriteable bits */
1723 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1727 /* reset buffer size and read/write pointers */
1728 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1730 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1733 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1735 uint32_t ret = s->RxConfig;
1737 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1742 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1746 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1750 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1752 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1753 rtl8139_do_receive(s, buf, size, do_interrupt);
1757 qemu_send_packet(s->vc, buf, size);
1761 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1763 if (!rtl8139_transmitter_enabled(s))
1765 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1770 if (s->TxStatus[descriptor] & TxHostOwns)
1772 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1773 descriptor, s->TxStatus[descriptor]));
1777 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1779 int txsize = s->TxStatus[descriptor] & 0x1fff;
1780 uint8_t txbuffer[0x2000];
1782 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1783 txsize, s->TxAddr[descriptor]));
1785 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1787 /* Mark descriptor as transferred */
1788 s->TxStatus[descriptor] |= TxHostOwns;
1789 s->TxStatus[descriptor] |= TxStatOK;
1791 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1793 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1795 /* update interrupt */
1796 s->IntrStatus |= TxOK;
1797 rtl8139_update_irq(s);
1802 /* structures and macros for task offloading */
1803 typedef struct ip_header
1805 uint8_t ip_ver_len; /* version and header length */
1806 uint8_t ip_tos; /* type of service */
1807 uint16_t ip_len; /* total length */
1808 uint16_t ip_id; /* identification */
1809 uint16_t ip_off; /* fragment offset field */
1810 uint8_t ip_ttl; /* time to live */
1811 uint8_t ip_p; /* protocol */
1812 uint16_t ip_sum; /* checksum */
1813 uint32_t ip_src,ip_dst; /* source and dest address */
1816 #define IP_HEADER_VERSION_4 4
1817 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1818 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1820 typedef struct tcp_header
1822 uint16_t th_sport; /* source port */
1823 uint16_t th_dport; /* destination port */
1824 uint32_t th_seq; /* sequence number */
1825 uint32_t th_ack; /* acknowledgement number */
1826 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1827 uint16_t th_win; /* window */
1828 uint16_t th_sum; /* checksum */
1829 uint16_t th_urp; /* urgent pointer */
1832 typedef struct udp_header
1834 uint16_t uh_sport; /* source port */
1835 uint16_t uh_dport; /* destination port */
1836 uint16_t uh_ulen; /* udp length */
1837 uint16_t uh_sum; /* udp checksum */
1840 typedef struct ip_pseudo_header
1846 uint16_t ip_payload;
1849 #define IP_PROTO_TCP 6
1850 #define IP_PROTO_UDP 17
1852 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1853 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1854 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1856 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1858 #define TCP_FLAG_FIN 0x01
1859 #define TCP_FLAG_PUSH 0x08
1861 /* produces ones' complement sum of data */
1862 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1864 uint32_t result = 0;
1866 for (; len > 1; data+=2, len-=2)
1868 result += *(uint16_t*)data;
1871 /* add the remainder byte */
1874 uint8_t odd[2] = {*data, 0};
1875 result += *(uint16_t*)odd;
1879 result = (result & 0xffff) + (result >> 16);
1884 static uint16_t ip_checksum(void *data, size_t len)
1886 return ~ones_complement_sum((uint8_t*)data, len);
1889 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1891 if (!rtl8139_transmitter_enabled(s))
1893 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1897 if (!rtl8139_cp_transmitter_enabled(s))
1899 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1903 int descriptor = s->currCPlusTxDesc;
1905 target_phys_addr_t cplus_tx_ring_desc =
1906 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1908 /* Normal priority ring */
1909 cplus_tx_ring_desc += 16 * descriptor;
1911 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1912 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1914 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1916 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1917 txdw0 = le32_to_cpu(val);
1918 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1919 txdw1 = le32_to_cpu(val);
1920 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1921 txbufLO = le32_to_cpu(val);
1922 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1923 txbufHI = le32_to_cpu(val);
1925 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1927 txdw0, txdw1, txbufLO, txbufHI));
1929 /* w0 ownership flag */
1930 #define CP_TX_OWN (1<<31)
1931 /* w0 end of ring flag */
1932 #define CP_TX_EOR (1<<30)
1933 /* first segment of received packet flag */
1934 #define CP_TX_FS (1<<29)
1935 /* last segment of received packet flag */
1936 #define CP_TX_LS (1<<28)
1937 /* large send packet flag */
1938 #define CP_TX_LGSEN (1<<27)
1939 /* large send MSS mask, bits 16...25 */
1940 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1942 /* IP checksum offload flag */
1943 #define CP_TX_IPCS (1<<18)
1944 /* UDP checksum offload flag */
1945 #define CP_TX_UDPCS (1<<17)
1946 /* TCP checksum offload flag */
1947 #define CP_TX_TCPCS (1<<16)
1949 /* w0 bits 0...15 : buffer size */
1950 #define CP_TX_BUFFER_SIZE (1<<16)
1951 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1952 /* w1 tag available flag */
1953 #define CP_RX_TAGC (1<<17)
1954 /* w1 bits 0...15 : VLAN tag */
1955 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1956 /* w2 low 32bit of Rx buffer ptr */
1957 /* w3 high 32bit of Rx buffer ptr */
1959 /* set after transmission */
1960 /* FIFO underrun flag */
1961 #define CP_TX_STATUS_UNF (1<<25)
1962 /* transmit error summary flag, valid if set any of three below */
1963 #define CP_TX_STATUS_TES (1<<23)
1964 /* out-of-window collision flag */
1965 #define CP_TX_STATUS_OWC (1<<22)
1966 /* link failure flag */
1967 #define CP_TX_STATUS_LNKF (1<<21)
1968 /* excessive collisions flag */
1969 #define CP_TX_STATUS_EXC (1<<20)
1971 if (!(txdw0 & CP_TX_OWN))
1973 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1977 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1979 if (txdw0 & CP_TX_FS)
1981 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1983 /* reset internal buffer offset */
1984 s->cplus_txbuffer_offset = 0;
1987 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1988 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1990 /* make sure we have enough space to assemble the packet */
1991 if (!s->cplus_txbuffer)
1993 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1994 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
1995 s->cplus_txbuffer_offset = 0;
1997 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
2000 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2002 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2003 s->cplus_txbuffer = realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2005 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2008 if (!s->cplus_txbuffer)
2012 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2014 /* update tally counter */
2015 ++s->tally_counters.TxERR;
2016 ++s->tally_counters.TxAbt;
2021 /* append more data to the packet */
2023 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2024 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2026 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2027 s->cplus_txbuffer_offset += txsize;
2029 /* seek to next Rx descriptor */
2030 if (txdw0 & CP_TX_EOR)
2032 s->currCPlusTxDesc = 0;
2036 ++s->currCPlusTxDesc;
2037 if (s->currCPlusTxDesc >= 64)
2038 s->currCPlusTxDesc = 0;
2041 /* transfer ownership to target */
2042 txdw0 &= ~CP_RX_OWN;
2044 /* reset error indicator bits */
2045 txdw0 &= ~CP_TX_STATUS_UNF;
2046 txdw0 &= ~CP_TX_STATUS_TES;
2047 txdw0 &= ~CP_TX_STATUS_OWC;
2048 txdw0 &= ~CP_TX_STATUS_LNKF;
2049 txdw0 &= ~CP_TX_STATUS_EXC;
2051 /* update ring data */
2052 val = cpu_to_le32(txdw0);
2053 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2054 // val = cpu_to_le32(txdw1);
2055 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2057 /* Now decide if descriptor being processed is holding the last segment of packet */
2058 if (txdw0 & CP_TX_LS)
2060 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2062 /* can transfer fully assembled packet */
2064 uint8_t *saved_buffer = s->cplus_txbuffer;
2065 int saved_size = s->cplus_txbuffer_offset;
2066 int saved_buffer_len = s->cplus_txbuffer_len;
2068 /* reset the card space to protect from recursive call */
2069 s->cplus_txbuffer = NULL;
2070 s->cplus_txbuffer_offset = 0;
2071 s->cplus_txbuffer_len = 0;
2073 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2075 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2077 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2079 #define ETH_MTU 1500
2081 /* ip packet header */
2084 uint8_t ip_protocol = 0;
2085 uint16_t ip_data_len = 0;
2087 uint8_t *eth_payload_data = 0;
2088 size_t eth_payload_len = 0;
2090 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2091 if (proto == ETH_P_IP)
2093 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2096 eth_payload_data = saved_buffer + ETH_HLEN;
2097 eth_payload_len = saved_size - ETH_HLEN;
2099 ip = (ip_header*)eth_payload_data;
2101 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2102 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2105 hlen = IP_HEADER_LENGTH(ip);
2106 ip_protocol = ip->ip_p;
2107 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2113 if (txdw0 & CP_TX_IPCS)
2115 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2117 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2118 /* bad packet header len */
2119 /* or packet too short */
2124 ip->ip_sum = ip_checksum(ip, hlen);
2125 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2129 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2131 #if defined (DEBUG_RTL8139)
2132 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2134 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2135 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2137 int tcp_send_offset = 0;
2140 /* maximum IP header length is 60 bytes */
2141 uint8_t saved_ip_header[60];
2143 /* save IP header template; data area is used in tcp checksum calculation */
2144 memcpy(saved_ip_header, eth_payload_data, hlen);
2146 /* a placeholder for checksum calculation routine in tcp case */
2147 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2148 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2150 /* pointer to TCP header */
2151 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2153 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2155 /* ETH_MTU = ip header len + tcp header len + payload */
2156 int tcp_data_len = ip_data_len - tcp_hlen;
2157 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2159 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2160 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2162 /* note the cycle below overwrites IP header data,
2163 but restores it from saved_ip_header before sending packet */
2165 int is_last_frame = 0;
2167 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2169 uint16_t chunk_size = tcp_chunk_size;
2171 /* check if this is the last frame */
2172 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2175 chunk_size = tcp_data_len - tcp_send_offset;
2178 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2180 /* add 4 TCP pseudoheader fields */
2181 /* copy IP source and destination fields */
2182 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2184 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2186 if (tcp_send_offset)
2188 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2191 /* keep PUSH and FIN flags only for the last frame */
2194 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2197 /* recalculate TCP checksum */
2198 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2199 p_tcpip_hdr->zeros = 0;
2200 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2201 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2203 p_tcp_hdr->th_sum = 0;
2205 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2206 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2208 p_tcp_hdr->th_sum = tcp_checksum;
2210 /* restore IP header */
2211 memcpy(eth_payload_data, saved_ip_header, hlen);
2213 /* set IP data length and recalculate IP checksum */
2214 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2216 /* increment IP id for subsequent frames */
2217 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2220 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2221 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2223 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2224 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2225 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2227 /* add transferred count to TCP sequence number */
2228 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2232 /* Stop sending this frame */
2235 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2237 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2239 /* maximum IP header length is 60 bytes */
2240 uint8_t saved_ip_header[60];
2241 memcpy(saved_ip_header, eth_payload_data, hlen);
2243 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2244 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2246 /* add 4 TCP pseudoheader fields */
2247 /* copy IP source and destination fields */
2248 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2250 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2252 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2254 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2255 p_tcpip_hdr->zeros = 0;
2256 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2257 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2259 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2261 p_tcp_hdr->th_sum = 0;
2263 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2264 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2266 p_tcp_hdr->th_sum = tcp_checksum;
2268 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2270 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2272 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2273 p_udpip_hdr->zeros = 0;
2274 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2275 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2277 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2279 p_udp_hdr->uh_sum = 0;
2281 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2282 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2284 p_udp_hdr->uh_sum = udp_checksum;
2287 /* restore IP header */
2288 memcpy(eth_payload_data, saved_ip_header, hlen);
2293 /* update tally counter */
2294 ++s->tally_counters.TxOk;
2296 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2298 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2300 /* restore card space if there was no recursion and reset offset */
2301 if (!s->cplus_txbuffer)
2303 s->cplus_txbuffer = saved_buffer;
2304 s->cplus_txbuffer_len = saved_buffer_len;
2305 s->cplus_txbuffer_offset = 0;
2314 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2320 static void rtl8139_cplus_transmit(RTL8139State *s)
2324 while (rtl8139_cplus_transmit_one(s))
2329 /* Mark transfer completed */
2332 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2333 s->currCPlusTxDesc));
2337 /* update interrupt status */
2338 s->IntrStatus |= TxOK;
2339 rtl8139_update_irq(s);
2343 static void rtl8139_transmit(RTL8139State *s)
2345 int descriptor = s->currTxDesc, txcount = 0;
2348 if (rtl8139_transmit_one(s, descriptor))
2355 /* Mark transfer completed */
2358 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2362 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2365 int descriptor = txRegOffset/4;
2367 /* handle C+ transmit mode register configuration */
2369 if (rtl8139_cp_transmitter_enabled(s))
2371 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2373 /* handle Dump Tally Counters command */
2374 s->TxStatus[descriptor] = val;
2376 if (descriptor == 0 && (val & 0x8))
2378 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2380 /* dump tally counters to specified memory location */
2381 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2383 /* mark dump completed */
2384 s->TxStatus[0] &= ~0x8;
2390 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2392 /* mask only reserved bits */
2393 val &= ~0xff00c000; /* these bits are reset on write */
2394 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2396 s->TxStatus[descriptor] = val;
2398 /* attempt to start transmission */
2399 rtl8139_transmit(s);
2402 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2404 uint32_t ret = s->TxStatus[txRegOffset/4];
2406 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2411 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2415 /* Simulate TSAD, it is read only anyway */
2417 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2418 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2419 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2420 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2422 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2423 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2424 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2425 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2427 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2428 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2429 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2430 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2432 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2433 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2434 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2435 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2438 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2443 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2445 uint16_t ret = s->CSCR;
2447 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2452 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2454 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2456 s->TxAddr[txAddrOffset/4] = val;
2459 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2461 uint32_t ret = s->TxAddr[txAddrOffset/4];
2463 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2468 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2470 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2472 /* this value is off by 16 */
2473 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2475 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2476 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2479 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2481 /* this value is off by 16 */
2482 uint32_t ret = s->RxBufPtr - 0x10;
2484 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2489 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2491 /* this value is NOT off by 16 */
2492 uint32_t ret = s->RxBufAddr;
2494 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2499 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2501 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2505 /* may need to reset rxring here */
2508 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2510 uint32_t ret = s->RxBuf;
2512 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2517 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2519 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2521 /* mask unwriteable bits */
2522 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2526 rtl8139_update_irq(s);
2529 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2531 uint32_t ret = s->IntrMask;
2533 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2538 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2540 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2544 /* writing to ISR has no effect */
2549 uint16_t newStatus = s->IntrStatus & ~val;
2551 /* mask unwriteable bits */
2552 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2554 /* writing 1 to interrupt status register bit clears it */
2556 rtl8139_update_irq(s);
2558 s->IntrStatus = newStatus;
2559 rtl8139_update_irq(s);
2563 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2565 uint32_t ret = s->IntrStatus;
2567 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2571 /* reading ISR clears all interrupts */
2574 rtl8139_update_irq(s);
2581 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2583 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2585 /* mask unwriteable bits */
2586 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2591 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2593 uint32_t ret = s->MultiIntr;
2595 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2600 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2602 RTL8139State *s = opaque;
2608 case MAC0 ... MAC0+5:
2609 s->phys[addr - MAC0] = val;
2611 case MAC0+6 ... MAC0+7:
2614 case MAR0 ... MAR0+7:
2615 s->mult[addr - MAR0] = val;
2618 rtl8139_ChipCmd_write(s, val);
2621 rtl8139_Cfg9346_write(s, val);
2623 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2624 rtl8139_TxConfig_writeb(s, val);
2627 rtl8139_Config0_write(s, val);
2630 rtl8139_Config1_write(s, val);
2633 rtl8139_Config3_write(s, val);
2636 rtl8139_Config4_write(s, val);
2639 rtl8139_Config5_write(s, val);
2643 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2647 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2650 s->clock_enabled = 1;
2652 else if (val == 'H')
2654 s->clock_enabled = 0;
2659 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2664 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2667 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2668 //rtl8139_cplus_transmit(s);
2672 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2673 rtl8139_cplus_transmit(s);
2679 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2684 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2686 RTL8139State *s = opaque;
2693 rtl8139_IntrMask_write(s, val);
2697 rtl8139_IntrStatus_write(s, val);
2701 rtl8139_MultiIntr_write(s, val);
2705 rtl8139_RxBufPtr_write(s, val);
2709 rtl8139_BasicModeCtrl_write(s, val);
2711 case BasicModeStatus:
2712 rtl8139_BasicModeStatus_write(s, val);
2715 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2716 s->NWayAdvert = val;
2719 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2722 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2723 s->NWayExpansion = val;
2727 rtl8139_CpCmd_write(s, val);
2731 rtl8139_IntrMitigate_write(s, val);
2735 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2737 #ifdef TARGET_WORDS_BIGENDIAN
2738 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2739 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2741 rtl8139_io_writeb(opaque, addr, val & 0xff);
2742 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2748 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2750 RTL8139State *s = opaque;
2757 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2762 rtl8139_TxConfig_write(s, val);
2766 rtl8139_RxConfig_write(s, val);
2769 case TxStatus0 ... TxStatus0+4*4-1:
2770 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2773 case TxAddr0 ... TxAddr0+4*4-1:
2774 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2778 rtl8139_RxBuf_write(s, val);
2782 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2783 s->RxRingAddrLO = val;
2787 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2788 s->RxRingAddrHI = val;
2792 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2794 s->TCTR_base = qemu_get_clock(vm_clock);
2798 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2803 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2804 #ifdef TARGET_WORDS_BIGENDIAN
2805 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2806 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2807 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2808 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2810 rtl8139_io_writeb(opaque, addr, val & 0xff);
2811 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2812 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2813 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2819 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2821 RTL8139State *s = opaque;
2828 case MAC0 ... MAC0+5:
2829 ret = s->phys[addr - MAC0];
2831 case MAC0+6 ... MAC0+7:
2834 case MAR0 ... MAR0+7:
2835 ret = s->mult[addr - MAR0];
2838 ret = rtl8139_ChipCmd_read(s);
2841 ret = rtl8139_Cfg9346_read(s);
2844 ret = rtl8139_Config0_read(s);
2847 ret = rtl8139_Config1_read(s);
2850 ret = rtl8139_Config3_read(s);
2853 ret = rtl8139_Config4_read(s);
2856 ret = rtl8139_Config5_read(s);
2861 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2865 ret = s->clock_enabled;
2866 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2870 ret = RTL8139_PCI_REVID;
2871 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2876 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2879 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2880 ret = s->TxConfig >> 24;
2881 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2885 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2893 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2895 RTL8139State *s = opaque;
2898 addr &= 0xfe; /* mask lower bit */
2903 ret = rtl8139_IntrMask_read(s);
2907 ret = rtl8139_IntrStatus_read(s);
2911 ret = rtl8139_MultiIntr_read(s);
2915 ret = rtl8139_RxBufPtr_read(s);
2919 ret = rtl8139_RxBufAddr_read(s);
2923 ret = rtl8139_BasicModeCtrl_read(s);
2925 case BasicModeStatus:
2926 ret = rtl8139_BasicModeStatus_read(s);
2929 ret = s->NWayAdvert;
2930 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2934 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2937 ret = s->NWayExpansion;
2938 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2942 ret = rtl8139_CpCmd_read(s);
2946 ret = rtl8139_IntrMitigate_read(s);
2950 ret = rtl8139_TSAD_read(s);
2954 ret = rtl8139_CSCR_read(s);
2958 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2960 #ifdef TARGET_WORDS_BIGENDIAN
2961 ret = rtl8139_io_readb(opaque, addr) << 8;
2962 ret |= rtl8139_io_readb(opaque, addr + 1);
2964 ret = rtl8139_io_readb(opaque, addr);
2965 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2968 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2975 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2977 RTL8139State *s = opaque;
2980 addr &= 0xfc; /* also mask low 2 bits */
2987 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
2991 ret = rtl8139_TxConfig_read(s);
2995 ret = rtl8139_RxConfig_read(s);
2998 case TxStatus0 ... TxStatus0+4*4-1:
2999 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3002 case TxAddr0 ... TxAddr0+4*4-1:
3003 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3007 ret = rtl8139_RxBuf_read(s);
3011 ret = s->RxRingAddrLO;
3012 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3016 ret = s->RxRingAddrHI;
3017 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3022 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3027 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3031 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3033 #ifdef TARGET_WORDS_BIGENDIAN
3034 ret = rtl8139_io_readb(opaque, addr) << 24;
3035 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
3036 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
3037 ret |= rtl8139_io_readb(opaque, addr + 3);
3039 ret = rtl8139_io_readb(opaque, addr);
3040 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3041 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3042 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3045 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3054 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3056 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3059 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3061 rtl8139_io_writew(opaque, addr & 0xFF, val);
3064 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3066 rtl8139_io_writel(opaque, addr & 0xFF, val);
3069 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3071 return rtl8139_io_readb(opaque, addr & 0xFF);
3074 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3076 return rtl8139_io_readw(opaque, addr & 0xFF);
3079 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3081 return rtl8139_io_readl(opaque, addr & 0xFF);
3086 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3088 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3091 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3093 rtl8139_io_writew(opaque, addr & 0xFF, val);
3096 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3098 rtl8139_io_writel(opaque, addr & 0xFF, val);
3101 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3103 return rtl8139_io_readb(opaque, addr & 0xFF);
3106 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3108 return rtl8139_io_readw(opaque, addr & 0xFF);
3111 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3113 return rtl8139_io_readl(opaque, addr & 0xFF);
3118 static void rtl8139_save(QEMUFile* f,void* opaque)
3120 RTL8139State* s=(RTL8139State*)opaque;
3123 pci_device_save(s->pci_dev, f);
3125 qemu_put_buffer(f, s->phys, 6);
3126 qemu_put_buffer(f, s->mult, 8);
3130 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3134 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3137 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3138 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3139 qemu_put_be32s(f, &s->RxBufPtr);
3140 qemu_put_be32s(f, &s->RxBufAddr);
3142 qemu_put_be16s(f, &s->IntrStatus);
3143 qemu_put_be16s(f, &s->IntrMask);
3145 qemu_put_be32s(f, &s->TxConfig);
3146 qemu_put_be32s(f, &s->RxConfig);
3147 qemu_put_be32s(f, &s->RxMissed);
3148 qemu_put_be16s(f, &s->CSCR);
3150 qemu_put_8s(f, &s->Cfg9346);
3151 qemu_put_8s(f, &s->Config0);
3152 qemu_put_8s(f, &s->Config1);
3153 qemu_put_8s(f, &s->Config3);
3154 qemu_put_8s(f, &s->Config4);
3155 qemu_put_8s(f, &s->Config5);
3157 qemu_put_8s(f, &s->clock_enabled);
3158 qemu_put_8s(f, &s->bChipCmdState);
3160 qemu_put_be16s(f, &s->MultiIntr);
3162 qemu_put_be16s(f, &s->BasicModeCtrl);
3163 qemu_put_be16s(f, &s->BasicModeStatus);
3164 qemu_put_be16s(f, &s->NWayAdvert);
3165 qemu_put_be16s(f, &s->NWayLPAR);
3166 qemu_put_be16s(f, &s->NWayExpansion);
3168 qemu_put_be16s(f, &s->CpCmd);
3169 qemu_put_8s(f, &s->TxThresh);
3172 qemu_put_be32s(f, &i); /* unused. */
3173 qemu_put_buffer(f, s->macaddr, 6);
3174 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
3176 qemu_put_be32s(f, &s->currTxDesc);
3177 qemu_put_be32s(f, &s->currCPlusRxDesc);
3178 qemu_put_be32s(f, &s->currCPlusTxDesc);
3179 qemu_put_be32s(f, &s->RxRingAddrLO);
3180 qemu_put_be32s(f, &s->RxRingAddrHI);
3182 for (i=0; i<EEPROM_9346_SIZE; ++i)
3184 qemu_put_be16s(f, &s->eeprom.contents[i]);
3186 qemu_put_be32s(f, &s->eeprom.mode);
3187 qemu_put_be32s(f, &s->eeprom.tick);
3188 qemu_put_8s(f, &s->eeprom.address);
3189 qemu_put_be16s(f, &s->eeprom.input);
3190 qemu_put_be16s(f, &s->eeprom.output);
3192 qemu_put_8s(f, &s->eeprom.eecs);
3193 qemu_put_8s(f, &s->eeprom.eesk);
3194 qemu_put_8s(f, &s->eeprom.eedi);
3195 qemu_put_8s(f, &s->eeprom.eedo);
3197 qemu_put_be32s(f, &s->TCTR);
3198 qemu_put_be32s(f, &s->TimerInt);
3199 qemu_put_be64s(f, &s->TCTR_base);
3201 RTL8139TallyCounters_save(f, &s->tally_counters);
3204 static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3206 RTL8139State* s=(RTL8139State*)opaque;
3209 /* just 2 versions for now */
3213 if (version_id >= 3) {
3214 ret = pci_device_load(s->pci_dev, f);
3219 /* saved since version 1 */
3220 qemu_get_buffer(f, s->phys, 6);
3221 qemu_get_buffer(f, s->mult, 8);
3225 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3229 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3232 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3233 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3234 qemu_get_be32s(f, &s->RxBufPtr);
3235 qemu_get_be32s(f, &s->RxBufAddr);
3237 qemu_get_be16s(f, &s->IntrStatus);
3238 qemu_get_be16s(f, &s->IntrMask);
3240 qemu_get_be32s(f, &s->TxConfig);
3241 qemu_get_be32s(f, &s->RxConfig);
3242 qemu_get_be32s(f, &s->RxMissed);
3243 qemu_get_be16s(f, &s->CSCR);
3245 qemu_get_8s(f, &s->Cfg9346);
3246 qemu_get_8s(f, &s->Config0);
3247 qemu_get_8s(f, &s->Config1);
3248 qemu_get_8s(f, &s->Config3);
3249 qemu_get_8s(f, &s->Config4);
3250 qemu_get_8s(f, &s->Config5);
3252 qemu_get_8s(f, &s->clock_enabled);
3253 qemu_get_8s(f, &s->bChipCmdState);
3255 qemu_get_be16s(f, &s->MultiIntr);
3257 qemu_get_be16s(f, &s->BasicModeCtrl);
3258 qemu_get_be16s(f, &s->BasicModeStatus);
3259 qemu_get_be16s(f, &s->NWayAdvert);
3260 qemu_get_be16s(f, &s->NWayLPAR);
3261 qemu_get_be16s(f, &s->NWayExpansion);
3263 qemu_get_be16s(f, &s->CpCmd);
3264 qemu_get_8s(f, &s->TxThresh);
3266 qemu_get_be32s(f, &i); /* unused. */
3267 qemu_get_buffer(f, s->macaddr, 6);
3268 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3270 qemu_get_be32s(f, &s->currTxDesc);
3271 qemu_get_be32s(f, &s->currCPlusRxDesc);
3272 qemu_get_be32s(f, &s->currCPlusTxDesc);
3273 qemu_get_be32s(f, &s->RxRingAddrLO);
3274 qemu_get_be32s(f, &s->RxRingAddrHI);
3276 for (i=0; i<EEPROM_9346_SIZE; ++i)
3278 qemu_get_be16s(f, &s->eeprom.contents[i]);
3280 qemu_get_be32s(f, &s->eeprom.mode);
3281 qemu_get_be32s(f, &s->eeprom.tick);
3282 qemu_get_8s(f, &s->eeprom.address);
3283 qemu_get_be16s(f, &s->eeprom.input);
3284 qemu_get_be16s(f, &s->eeprom.output);
3286 qemu_get_8s(f, &s->eeprom.eecs);
3287 qemu_get_8s(f, &s->eeprom.eesk);
3288 qemu_get_8s(f, &s->eeprom.eedi);
3289 qemu_get_8s(f, &s->eeprom.eedo);
3291 /* saved since version 2 */
3292 if (version_id >= 2)
3294 qemu_get_be32s(f, &s->TCTR);
3295 qemu_get_be32s(f, &s->TimerInt);
3296 qemu_get_be64s(f, &s->TCTR_base);
3298 RTL8139TallyCounters_load(f, &s->tally_counters);
3302 /* not saved, use default */
3307 RTL8139TallyCounters_clear(&s->tally_counters);
3313 /***********************************************************/
3314 /* PCI RTL8139 definitions */
3316 typedef struct PCIRTL8139State {
3318 RTL8139State rtl8139;
3321 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3322 uint32_t addr, uint32_t size, int type)
3324 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3325 RTL8139State *s = &d->rtl8139;
3327 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3330 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3331 uint32_t addr, uint32_t size, int type)
3333 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3334 RTL8139State *s = &d->rtl8139;
3336 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3337 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3339 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3340 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3342 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3343 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3346 static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3352 static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3353 rtl8139_mmio_writeb,
3354 rtl8139_mmio_writew,
3355 rtl8139_mmio_writel,
3358 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3360 int64_t next_time = current_time +
3361 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3362 if (next_time <= current_time)
3363 next_time = current_time + 1;
3367 #if RTL8139_ONBOARD_TIMER
3368 static void rtl8139_timer(void *opaque)
3370 RTL8139State *s = opaque;
3377 if (!s->clock_enabled)
3379 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3383 curr_time = qemu_get_clock(vm_clock);
3385 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3387 if (s->TimerInt && curr_tick >= s->TimerInt)
3389 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3395 s->TCTR = curr_tick;
3397 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3401 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3402 s->IntrStatus |= PCSTimeout;
3403 rtl8139_update_irq(s);
3406 qemu_mod_timer(s->timer,
3407 rtl8139_get_next_tctr_time(s,curr_time));
3409 #endif /* RTL8139_ONBOARD_TIMER */
3411 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
3417 d = (PCIRTL8139State *)pci_register_device(bus,
3418 "RTL8139", sizeof(PCIRTL8139State),
3421 pci_conf = d->dev.config;
3422 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3423 pci_conf[0x01] = 0x10;
3424 pci_conf[0x02] = 0x39;
3425 pci_conf[0x03] = 0x81;
3426 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3427 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3428 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3429 pci_conf[0x0b] = 0x02;
3430 pci_conf[0x0e] = 0x00; /* header_type */
3431 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3432 pci_conf[0x34] = 0xdc;
3436 /* I/O handler for memory-mapped I/O */
3437 s->rtl8139_mmio_io_addr =
3438 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3440 pci_register_io_region(&d->dev, 0, 0x100,
3441 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3443 pci_register_io_region(&d->dev, 1, 0x100,
3444 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3446 s->pci_dev = (PCIDevice *)d;
3447 memcpy(s->macaddr, nd->macaddr, 6);
3449 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3450 rtl8139_can_receive, s);
3452 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3453 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3461 s->cplus_txbuffer = NULL;
3462 s->cplus_txbuffer_len = 0;
3463 s->cplus_txbuffer_offset = 0;
3465 /* XXX: instance number ? */
3466 register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
3468 #if RTL8139_ONBOARD_TIMER
3469 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3471 qemu_mod_timer(s->timer,
3472 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3473 #endif /* RTL8139_ONBOARD_TIMER */