2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-char.h"
28 #include "qemu-timer.h"
30 //#define DEBUG_SERIAL
32 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
34 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
35 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
36 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
37 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
39 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
40 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
42 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
43 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
44 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
45 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
48 * These are the definitions for the Modem Control Register
50 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
51 #define UART_MCR_OUT2 0x08 /* Out2 complement */
52 #define UART_MCR_OUT1 0x04 /* Out1 complement */
53 #define UART_MCR_RTS 0x02 /* RTS complement */
54 #define UART_MCR_DTR 0x01 /* DTR complement */
57 * These are the definitions for the Modem Status Register
59 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
60 #define UART_MSR_RI 0x40 /* Ring Indicator */
61 #define UART_MSR_DSR 0x20 /* Data Set Ready */
62 #define UART_MSR_CTS 0x10 /* Clear to Send */
63 #define UART_MSR_DDCD 0x08 /* Delta DCD */
64 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
65 #define UART_MSR_DDSR 0x02 /* Delta DSR */
66 #define UART_MSR_DCTS 0x01 /* Delta CTS */
67 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
69 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
70 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
71 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
72 #define UART_LSR_FE 0x08 /* Frame error indicator */
73 #define UART_LSR_PE 0x04 /* Parity error indicator */
74 #define UART_LSR_OE 0x02 /* Overrun error indicator */
75 #define UART_LSR_DR 0x01 /* Receiver data ready */
78 * Delay TX IRQ after sending as much characters as the given interval would
79 * contain on real hardware. This avoids overloading the guest if it processes
80 * its output buffer in a loop inside the TX IRQ handler.
82 #define THROTTLE_TX_INTERVAL 10 /* ms */
86 uint8_t rbr; /* receive register */
88 uint8_t iir; /* read only */
91 uint8_t lsr; /* read only */
92 uint8_t msr; /* read only */
94 /* NOTE: this hidden state is necessary for tx irq generation as
95 it can be reset while reading iir */
99 int last_break_enable;
100 target_phys_addr_t base;
107 static void serial_receive_byte(SerialState *s, int ch);
109 static void serial_update_irq(SerialState *s)
111 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
112 s->iir = UART_IIR_RDI;
113 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
114 s->iir = UART_IIR_THRI;
116 s->iir = UART_IIR_NO_INT;
118 if (s->iir != UART_IIR_NO_INT) {
119 qemu_irq_raise(s->irq);
121 qemu_irq_lower(s->irq);
125 static void serial_tx_done(void *opaque)
127 SerialState *s = opaque;
129 if (s->tx_burst < 0) {
133 divider = s->divider;
137 /* We assume 10 bits/char, OK for this purpose. */
138 s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
139 (1000000 * 10 / (s->baudbase / divider));
142 s->lsr |= UART_LSR_THRE;
143 s->lsr |= UART_LSR_TEMT;
144 serial_update_irq(s);
147 static void serial_update_parameters(SerialState *s)
149 int speed, parity, data_bits, stop_bits;
150 QEMUSerialSetParams ssp;
164 data_bits = (s->lcr & 0x03) + 5;
167 speed = s->baudbase / s->divider;
170 ssp.data_bits = data_bits;
171 ssp.stop_bits = stop_bits;
172 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
174 printf("speed=%d parity=%c data=%d stop=%d\n",
175 speed, parity, data_bits, stop_bits);
179 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
181 SerialState *s = opaque;
186 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
191 if (s->lcr & UART_LCR_DLAB) {
192 s->divider = (s->divider & 0xff00) | val;
193 serial_update_parameters(s);
196 s->lsr &= ~UART_LSR_THRE;
197 serial_update_irq(s);
199 if (!(s->mcr & UART_MCR_LOOP)) {
200 /* when not in loopback mode, send the char */
201 qemu_chr_write(s->chr, &ch, 1);
203 /* in loopback mode, say that we just received a char */
204 serial_receive_byte(s, ch);
206 if (s->tx_burst > 0) {
209 } else if (s->tx_burst == 0) {
211 qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) +
212 ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
217 if (s->lcr & UART_LCR_DLAB) {
218 s->divider = (s->divider & 0x00ff) | (val << 8);
219 serial_update_parameters(s);
222 if (s->lsr & UART_LSR_THRE) {
225 serial_update_irq(s);
234 serial_update_parameters(s);
235 break_enable = (val >> 6) & 1;
236 if (break_enable != s->last_break_enable) {
237 s->last_break_enable = break_enable;
238 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
256 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
258 SerialState *s = opaque;
265 if (s->lcr & UART_LCR_DLAB) {
266 ret = s->divider & 0xff;
269 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
270 serial_update_irq(s);
271 if (!(s->mcr & UART_MCR_LOOP)) {
272 /* in loopback mode, don't receive any data */
273 qemu_chr_accept_input(s->chr);
278 if (s->lcr & UART_LCR_DLAB) {
279 ret = (s->divider >> 8) & 0xff;
286 /* reset THR pending bit */
287 if ((ret & 0x7) == UART_IIR_THRI)
289 serial_update_irq(s);
301 if (s->mcr & UART_MCR_LOOP) {
302 /* in loopback, the modem output pins are connected to the
304 ret = (s->mcr & 0x0c) << 4;
305 ret |= (s->mcr & 0x02) << 3;
306 ret |= (s->mcr & 0x01) << 5;
316 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
321 static int serial_can_receive(SerialState *s)
323 return !(s->lsr & UART_LSR_DR);
326 static void serial_receive_byte(SerialState *s, int ch)
329 s->lsr |= UART_LSR_DR;
330 serial_update_irq(s);
333 static void serial_receive_break(SerialState *s)
336 s->lsr |= UART_LSR_BI | UART_LSR_DR;
337 serial_update_irq(s);
340 static int serial_can_receive1(void *opaque)
342 SerialState *s = opaque;
343 return serial_can_receive(s);
346 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
348 SerialState *s = opaque;
349 serial_receive_byte(s, buf[0]);
352 static void serial_event(void *opaque, int event)
354 SerialState *s = opaque;
355 if (event == CHR_EVENT_BREAK)
356 serial_receive_break(s);
359 static void serial_save(QEMUFile *f, void *opaque)
361 SerialState *s = opaque;
363 qemu_put_be16s(f,&s->divider);
364 qemu_put_8s(f,&s->rbr);
365 qemu_put_8s(f,&s->ier);
366 qemu_put_8s(f,&s->iir);
367 qemu_put_8s(f,&s->lcr);
368 qemu_put_8s(f,&s->mcr);
369 qemu_put_8s(f,&s->lsr);
370 qemu_put_8s(f,&s->msr);
371 qemu_put_8s(f,&s->scr);
374 static int serial_load(QEMUFile *f, void *opaque, int version_id)
376 SerialState *s = opaque;
382 qemu_get_be16s(f, &s->divider);
384 s->divider = qemu_get_byte(f);
385 qemu_get_8s(f,&s->rbr);
386 qemu_get_8s(f,&s->ier);
387 qemu_get_8s(f,&s->iir);
388 qemu_get_8s(f,&s->lcr);
389 qemu_get_8s(f,&s->mcr);
390 qemu_get_8s(f,&s->lsr);
391 qemu_get_8s(f,&s->msr);
392 qemu_get_8s(f,&s->scr);
397 static void serial_reset(void *opaque)
399 SerialState *s = opaque;
404 s->iir = UART_IIR_NO_INT;
407 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
408 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
412 s->last_break_enable = 0;
413 qemu_irq_lower(s->irq);
416 /* If fd is zero, it means that the serial device uses the console */
417 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
418 CharDriverState *chr)
422 s = qemu_mallocz(sizeof(SerialState));
426 s->baudbase = baudbase;
428 s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
432 qemu_register_reset(serial_reset, s);
435 register_savevm("serial", base, 2, serial_save, serial_load, s);
437 register_ioport_write(base, 8, 1, serial_ioport_write, s);
438 register_ioport_read(base, 8, 1, serial_ioport_read, s);
440 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
445 /* Memory mapped interface */
446 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
448 SerialState *s = opaque;
450 return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
453 void serial_mm_writeb (void *opaque,
454 target_phys_addr_t addr, uint32_t value)
456 SerialState *s = opaque;
458 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
461 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
463 SerialState *s = opaque;
466 val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
467 #ifdef TARGET_WORDS_BIGENDIAN
473 void serial_mm_writew (void *opaque,
474 target_phys_addr_t addr, uint32_t value)
476 SerialState *s = opaque;
477 #ifdef TARGET_WORDS_BIGENDIAN
478 value = bswap16(value);
480 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
483 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
485 SerialState *s = opaque;
488 val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
489 #ifdef TARGET_WORDS_BIGENDIAN
495 void serial_mm_writel (void *opaque,
496 target_phys_addr_t addr, uint32_t value)
498 SerialState *s = opaque;
499 #ifdef TARGET_WORDS_BIGENDIAN
500 value = bswap32(value);
502 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
505 static CPUReadMemoryFunc *serial_mm_read[] = {
511 static CPUWriteMemoryFunc *serial_mm_write[] = {
517 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
518 qemu_irq irq, int baudbase,
519 CharDriverState *chr, int ioregister)
524 s = qemu_mallocz(sizeof(SerialState));
529 s->it_shift = it_shift;
530 s->baudbase= baudbase;
532 s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
536 qemu_register_reset(serial_reset, s);
539 register_savevm("serial", base, 2, serial_save, serial_load, s);
542 s_io_memory = cpu_register_io_memory(0, serial_mm_read,
544 cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
547 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,