4 * Copyright (c) 2005 Samuel Tardieu
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sh7750_regs.h"
28 #include "sh7750_regnames.h"
32 typedef struct SH7750State {
35 /* Peripheral frequency in Hz */
37 /* SDRAM controller */
43 uint16_t portdira; /* Cached */
44 uint16_t portpullupa; /* Cached */
45 uint16_t portdirb; /* Cached */
46 uint16_t portpullupb; /* Cached */
49 uint16_t periph_pdtra; /* Imposed by the peripherals */
50 uint16_t periph_portdira; /* Direction seen from the peripherals */
51 uint16_t periph_pdtrb; /* Imposed by the peripherals */
52 uint16_t periph_portdirb; /* Direction seen from the peripherals */
53 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
68 /**********************************************************************
70 **********************************************************************/
72 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
76 for (i = 0; i < NB_DEVICES; i++) {
77 if (s->devices[i] == NULL) {
78 s->devices[i] = device;
85 static uint16_t portdir(uint32_t v)
87 #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
89 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
90 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
91 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
92 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
93 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
97 static uint16_t portpullup(uint32_t v)
99 #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
101 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
102 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
103 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
104 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
105 ODDPORTMASK(1) | ODDPORTMASK(0);
108 static uint16_t porta_lines(SH7750State * s)
110 return (s->portdira & s->pdtra) | /* CPU */
111 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
112 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
115 static uint16_t portb_lines(SH7750State * s)
117 return (s->portdirb & s->pdtrb) | /* CPU */
118 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
119 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
122 static void gen_port_interrupts(SH7750State * s)
124 /* XXXXX interrupts not generated */
127 static void porta_changed(SH7750State * s, uint16_t prev)
129 uint16_t currenta, changes;
133 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
134 prev, porta_lines(s));
135 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
137 currenta = porta_lines(s);
138 if (currenta == prev)
140 changes = currenta ^ prev;
142 for (i = 0; i < NB_DEVICES; i++) {
143 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
144 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
148 &s->periph_portdirb);
153 gen_port_interrupts(s);
156 static void portb_changed(SH7750State * s, uint16_t prev)
158 uint16_t currentb, changes;
161 currentb = portb_lines(s);
162 if (currentb == prev)
164 changes = currentb ^ prev;
166 for (i = 0; i < NB_DEVICES; i++) {
167 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
168 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
172 &s->periph_portdirb);
177 gen_port_interrupts(s);
180 /**********************************************************************
182 **********************************************************************/
184 static void error_access(const char *kind, target_phys_addr_t addr)
186 fprintf(stderr, "%s to %s (0x%08x) not supported\n",
187 kind, regname(addr), addr);
190 static void ignore_access(const char *kind, target_phys_addr_t addr)
192 fprintf(stderr, "%s to %s (0x%08x) ignored\n",
193 kind, regname(addr), addr);
196 static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
200 error_access("byte read", addr);
205 static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
207 SH7750State *s = opaque;
212 "Read access to refresh count register, incrementing\n");
214 case SH7750_PDTRA_A7:
215 return porta_lines(s);
216 case SH7750_PDTRB_A7:
217 return portb_lines(s);
229 error_access("word read", addr);
234 static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
236 SH7750State *s = opaque;
239 case SH7750_MMUCR_A7:
240 return s->cpu->mmucr;
251 case SH7750_EXPEVT_A7:
252 return s->cpu->expevt;
253 case SH7750_INTEVT_A7:
254 return s->cpu->intevt;
257 case 0x1f000030: /* Processor version PVR */
258 return 0x00050000; /* SH7750R */
259 case 0x1f000040: /* Processor version CVR */
260 return 0x00110000; /* Minimum caches */
261 case 0x1f000044: /* Processor version PRR */
262 return 0x00000100; /* SH7750R */
272 error_access("long read", addr);
277 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
281 /* PRECHARGE ? XXXXX */
282 case SH7750_PRECHARGE0_A7:
283 case SH7750_PRECHARGE1_A7:
284 ignore_access("byte write", addr);
287 error_access("byte write", addr);
292 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
295 SH7750State *s = opaque;
299 /* SDRAM controller */
302 case SH7750_RTCOR_A7:
303 case SH7750_RTCNT_A7:
304 case SH7750_RTCSR_A7:
305 ignore_access("word write", addr);
308 case SH7750_PDTRA_A7:
309 temp = porta_lines(s);
310 s->pdtra = mem_value;
311 porta_changed(s, temp);
313 case SH7750_PDTRB_A7:
314 temp = portb_lines(s);
315 s->pdtrb = mem_value;
316 portb_changed(s, temp);
319 fprintf(stderr, "Write access to refresh count register\n");
322 case SH7750_GPIOIC_A7:
323 s->gpioic = mem_value;
324 if (mem_value != 0) {
325 fprintf(stderr, "I/O interrupts not implemented\n");
345 error_access("word write", addr);
350 static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
353 SH7750State *s = opaque;
357 /* SDRAM controller */
364 ignore_access("long write", addr);
367 case SH7750_PCTRA_A7:
368 temp = porta_lines(s);
369 s->pctra = mem_value;
370 s->portdira = portdir(mem_value);
371 s->portpullupa = portpullup(mem_value);
372 porta_changed(s, temp);
374 case SH7750_PCTRB_A7:
375 temp = portb_lines(s);
376 s->pctrb = mem_value;
377 s->portdirb = portdir(mem_value);
378 s->portpullupb = portpullup(mem_value);
379 portb_changed(s, temp);
381 case SH7750_MMUCR_A7:
382 s->cpu->mmucr = mem_value;
385 s->cpu->pteh = mem_value;
388 s->cpu->ptel = mem_value;
391 s->cpu->ttb = mem_value;
394 s->cpu->tea = mem_value;
397 s->cpu->tra = mem_value & 0x000007ff;
399 case SH7750_EXPEVT_A7:
400 s->cpu->expevt = mem_value & 0x000007ff;
402 case SH7750_INTEVT_A7:
403 s->cpu->intevt = mem_value & 0x000007ff;
409 s->intpri00 = mem_value;
414 s->intmsk00 = mem_value;
419 error_access("long write", addr);
424 static CPUReadMemoryFunc *sh7750_mem_read[] = {
430 static CPUWriteMemoryFunc *sh7750_mem_write[] = {
436 SH7750State *sh7750_init(CPUSH4State * cpu)
439 int sh7750_io_memory;
441 s = qemu_mallocz(sizeof(SH7750State));
443 s->periph_freq = 60000000; /* 60MHz */
444 sh7750_io_memory = cpu_register_io_memory(0,
446 sh7750_mem_write, s);
447 cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
449 sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
450 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
451 s->periph_freq, serial_hds[1]);
453 tmu012_init(0x1fd80000,
454 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
456 tmu012_init(0x1e100000, 0, s->periph_freq);