4 * Copyright (c) 2007 Magnus Damm
5 * Copyright (c) 2005 Samuel Tardieu
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "sh7750_regs.h"
31 #include "sh7750_regnames.h"
38 typedef struct SH7750State {
41 /* Peripheral frequency in Hz */
43 /* SDRAM controller */
49 uint16_t portdira; /* Cached */
50 uint16_t portpullupa; /* Cached */
51 uint16_t portdirb; /* Cached */
52 uint16_t portpullupb; /* Cached */
55 uint16_t periph_pdtra; /* Imposed by the peripherals */
56 uint16_t periph_portdira; /* Direction seen from the peripherals */
57 uint16_t periph_pdtrb; /* Imposed by the peripherals */
58 uint16_t periph_portdirb; /* Direction seen from the peripherals */
59 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
65 struct intc_desc intc;
69 /**********************************************************************
71 **********************************************************************/
73 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
77 for (i = 0; i < NB_DEVICES; i++) {
78 if (s->devices[i] == NULL) {
79 s->devices[i] = device;
86 static uint16_t portdir(uint32_t v)
88 #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
90 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
91 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
92 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
93 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
94 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
98 static uint16_t portpullup(uint32_t v)
100 #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
102 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
103 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
104 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
105 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
106 ODDPORTMASK(1) | ODDPORTMASK(0);
109 static uint16_t porta_lines(SH7750State * s)
111 return (s->portdira & s->pdtra) | /* CPU */
112 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
113 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
116 static uint16_t portb_lines(SH7750State * s)
118 return (s->portdirb & s->pdtrb) | /* CPU */
119 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
120 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
123 static void gen_port_interrupts(SH7750State * s)
125 /* XXXXX interrupts not generated */
128 static void porta_changed(SH7750State * s, uint16_t prev)
130 uint16_t currenta, changes;
134 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
135 prev, porta_lines(s));
136 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
138 currenta = porta_lines(s);
139 if (currenta == prev)
141 changes = currenta ^ prev;
143 for (i = 0; i < NB_DEVICES; i++) {
144 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
145 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
149 &s->periph_portdirb);
154 gen_port_interrupts(s);
157 static void portb_changed(SH7750State * s, uint16_t prev)
159 uint16_t currentb, changes;
162 currentb = portb_lines(s);
163 if (currentb == prev)
165 changes = currentb ^ prev;
167 for (i = 0; i < NB_DEVICES; i++) {
168 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
169 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
173 &s->periph_portdirb);
178 gen_port_interrupts(s);
181 /**********************************************************************
183 **********************************************************************/
185 static void error_access(const char *kind, target_phys_addr_t addr)
187 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
188 kind, regname(addr), addr);
191 static void ignore_access(const char *kind, target_phys_addr_t addr)
193 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
194 kind, regname(addr), addr);
197 static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
201 error_access("byte read", addr);
206 static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
208 SH7750State *s = opaque;
211 case SH7750_FRQCR_A7:
215 "Read access to refresh count register, incrementing\n");
217 case SH7750_PDTRA_A7:
218 return porta_lines(s);
219 case SH7750_PDTRB_A7:
220 return portb_lines(s);
224 error_access("word read", addr);
229 static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
231 SH7750State *s = opaque;
234 case SH7750_MMUCR_A7:
235 return s->cpu->mmucr;
246 case SH7750_EXPEVT_A7:
247 return s->cpu->expevt;
248 case SH7750_INTEVT_A7:
249 return s->cpu->intevt;
252 case 0x1f000030: /* Processor version */
254 case 0x1f000040: /* Cache version */
256 case 0x1f000044: /* Processor revision */
259 error_access("long read", addr);
264 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
268 /* PRECHARGE ? XXXXX */
269 case SH7750_PRECHARGE0_A7:
270 case SH7750_PRECHARGE1_A7:
271 ignore_access("byte write", addr);
274 error_access("byte write", addr);
279 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
282 SH7750State *s = opaque;
286 /* SDRAM controller */
289 case SH7750_RTCOR_A7:
290 case SH7750_RTCNT_A7:
291 case SH7750_RTCSR_A7:
292 ignore_access("word write", addr);
295 case SH7750_PDTRA_A7:
296 temp = porta_lines(s);
297 s->pdtra = mem_value;
298 porta_changed(s, temp);
300 case SH7750_PDTRB_A7:
301 temp = portb_lines(s);
302 s->pdtrb = mem_value;
303 portb_changed(s, temp);
306 fprintf(stderr, "Write access to refresh count register\n");
309 case SH7750_GPIOIC_A7:
310 s->gpioic = mem_value;
311 if (mem_value != 0) {
312 fprintf(stderr, "I/O interrupts not implemented\n");
320 error_access("word write", addr);
325 static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
328 SH7750State *s = opaque;
332 /* SDRAM controller */
339 ignore_access("long write", addr);
342 case SH7750_PCTRA_A7:
343 temp = porta_lines(s);
344 s->pctra = mem_value;
345 s->portdira = portdir(mem_value);
346 s->portpullupa = portpullup(mem_value);
347 porta_changed(s, temp);
349 case SH7750_PCTRB_A7:
350 temp = portb_lines(s);
351 s->pctrb = mem_value;
352 s->portdirb = portdir(mem_value);
353 s->portpullupb = portpullup(mem_value);
354 portb_changed(s, temp);
356 case SH7750_MMUCR_A7:
357 s->cpu->mmucr = mem_value;
360 /* If asid changes, clear all registered tlb entries. */
361 if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
362 tlb_flush(s->cpu, 1);
363 s->cpu->pteh = mem_value;
366 s->cpu->ptel = mem_value;
369 s->cpu->ptea = mem_value & 0x0000000f;
372 s->cpu->ttb = mem_value;
375 s->cpu->tea = mem_value;
378 s->cpu->tra = mem_value & 0x000007ff;
380 case SH7750_EXPEVT_A7:
381 s->cpu->expevt = mem_value & 0x000007ff;
383 case SH7750_INTEVT_A7:
384 s->cpu->intevt = mem_value & 0x000007ff;
390 error_access("long write", addr);
395 static CPUReadMemoryFunc *sh7750_mem_read[] = {
401 static CPUWriteMemoryFunc *sh7750_mem_write[] = {
407 /* sh775x interrupt controller tables for sh_intc.c
408 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
414 /* interrupt sources */
415 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
416 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
417 IRL0, IRL1, IRL2, IRL3,
419 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
420 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
422 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
423 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
424 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
425 RTC_ATI, RTC_PRI, RTC_CUI,
426 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
427 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
431 /* interrupt groups */
432 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
439 static struct intc_vect vectors[] = {
440 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
441 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
442 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
443 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
444 INTC_VECT(RTC_CUI, 0x4c0),
445 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
446 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
447 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
448 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
449 INTC_VECT(WDT, 0x560),
450 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
453 static struct intc_group groups[] = {
454 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
455 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
456 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
457 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
458 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
461 static struct intc_prio_reg prio_registers[] = {
462 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
463 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
464 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
465 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
466 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
468 PCIC1, PCIC0_PCISERR } },
471 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
473 static struct intc_vect vectors_dma4[] = {
474 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
475 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
476 INTC_VECT(DMAC_DMAE, 0x6c0),
479 static struct intc_group groups_dma4[] = {
480 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
481 DMAC_DMTE3, DMAC_DMAE),
484 /* SH7750R and SH7751R both have 8-channel DMA controllers */
486 static struct intc_vect vectors_dma8[] = {
487 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
488 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
489 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
490 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
491 INTC_VECT(DMAC_DMAE, 0x6c0),
494 static struct intc_group groups_dma8[] = {
495 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
496 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
497 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
500 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
502 static struct intc_vect vectors_tmu34[] = {
503 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
506 static struct intc_mask_reg mask_registers[] = {
507 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
508 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
509 0, 0, 0, 0, 0, 0, TMU4, TMU3,
510 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
511 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
512 PCIC1_PCIDMA3, PCIC0_PCISERR } },
515 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
517 static struct intc_vect vectors_irlm[] = {
518 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
519 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
522 /* SH7751 and SH7751R both have PCI */
524 static struct intc_vect vectors_pci[] = {
525 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
526 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
527 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
528 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
531 static struct intc_group groups_pci[] = {
532 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
533 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
536 static struct intc_vect vectors_irl[] = {
537 INTC_VECT(IRL_0, 0x200),
538 INTC_VECT(IRL_1, 0x220),
539 INTC_VECT(IRL_2, 0x240),
540 INTC_VECT(IRL_3, 0x260),
541 INTC_VECT(IRL_4, 0x280),
542 INTC_VECT(IRL_5, 0x2a0),
543 INTC_VECT(IRL_6, 0x2c0),
544 INTC_VECT(IRL_7, 0x2e0),
545 INTC_VECT(IRL_8, 0x300),
546 INTC_VECT(IRL_9, 0x320),
547 INTC_VECT(IRL_A, 0x340),
548 INTC_VECT(IRL_B, 0x360),
549 INTC_VECT(IRL_C, 0x380),
550 INTC_VECT(IRL_D, 0x3a0),
551 INTC_VECT(IRL_E, 0x3c0),
554 static struct intc_group groups_irl[] = {
555 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
556 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
559 /**********************************************************************
560 Memory mapped cache and TLB
561 **********************************************************************/
563 #define MM_REGION_MASK 0x07000000
564 #define MM_ICACHE_ADDR (0)
565 #define MM_ICACHE_DATA (1)
566 #define MM_ITLB_ADDR (2)
567 #define MM_ITLB_DATA (3)
568 #define MM_OCACHE_ADDR (4)
569 #define MM_OCACHE_DATA (5)
570 #define MM_UTLB_ADDR (6)
571 #define MM_UTLB_DATA (7)
572 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
574 static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
581 static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
585 switch (MM_REGION_TYPE(addr)) {
611 static void invalid_write(void *opaque, target_phys_addr_t addr,
617 static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
620 SH7750State *s = opaque;
622 switch (MM_REGION_TYPE(addr)) {
637 cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
649 static CPUReadMemoryFunc *sh7750_mmct_read[] = {
655 static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
661 SH7750State *sh7750_init(CPUSH4State * cpu)
664 int sh7750_io_memory;
665 int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
667 s = qemu_mallocz(sizeof(SH7750State));
669 s->periph_freq = 60000000; /* 60MHz */
670 sh7750_io_memory = cpu_register_io_memory(0,
672 sh7750_mem_write, s);
673 cpu_register_physical_memory_offset(0x1c000000, 0x04000000,
674 sh7750_io_memory, 0x1c000000);
676 sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
678 sh7750_mmct_write, s);
679 cpu_register_physical_memory(0xf0000000, 0x08000000,
680 sh7750_mm_cache_and_tlb);
682 sh_intc_init(&s->intc, NR_SOURCES,
683 _INTC_ARRAY(mask_registers),
684 _INTC_ARRAY(prio_registers));
686 sh_intc_register_sources(&s->intc,
687 _INTC_ARRAY(vectors),
688 _INTC_ARRAY(groups));
690 cpu->intc_handle = &s->intc;
692 sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
693 s->intc.irqs[SCI1_ERI],
694 s->intc.irqs[SCI1_RXI],
695 s->intc.irqs[SCI1_TXI],
696 s->intc.irqs[SCI1_TEI],
698 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
699 s->periph_freq, serial_hds[1],
700 s->intc.irqs[SCIF_ERI],
701 s->intc.irqs[SCIF_RXI],
702 s->intc.irqs[SCIF_TXI],
704 s->intc.irqs[SCIF_BRI]);
706 tmu012_init(0x1fd80000,
707 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
711 s->intc.irqs[TMU2_TUNI],
712 s->intc.irqs[TMU2_TICPI]);
714 if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
715 sh_intc_register_sources(&s->intc,
716 _INTC_ARRAY(vectors_dma4),
717 _INTC_ARRAY(groups_dma4));
720 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
721 sh_intc_register_sources(&s->intc,
722 _INTC_ARRAY(vectors_dma8),
723 _INTC_ARRAY(groups_dma8));
726 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
727 sh_intc_register_sources(&s->intc,
728 _INTC_ARRAY(vectors_tmu34),
730 tmu012_init(0x1e100000, 0, s->periph_freq,
736 if (cpu->id & (SH_CPU_SH7751_ALL)) {
737 sh_intc_register_sources(&s->intc,
738 _INTC_ARRAY(vectors_pci),
739 _INTC_ARRAY(groups_pci));
742 if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
743 sh_intc_register_sources(&s->intc,
744 _INTC_ARRAY(vectors_irlm),
748 sh_intc_register_sources(&s->intc,
749 _INTC_ARRAY(vectors_irl),
750 _INTC_ARRAY(groups_irl));
754 qemu_irq sh7750_irl(SH7750State *s)
756 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
757 return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),