2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
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7 * of this software and associated documentation files (the "Software"), to deal
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29 //#define DEBUG_IRQ_COUNT
33 #define DPRINTF(fmt, ...) \
34 do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF(fmt, ...)
40 * Registers of interrupt controller in sun4m.
42 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
43 * produced as NCR89C105. See
44 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
46 * There is a system master controller and one for each cpu.
53 struct SLAVIO_INTCTLState;
55 typedef struct SLAVIO_CPUINTCTLState {
56 uint32_t intreg_pending;
57 struct SLAVIO_INTCTLState *master;
59 } SLAVIO_CPUINTCTLState;
61 typedef struct SLAVIO_INTCTLState {
63 uint32_t intregm_pending;
64 uint32_t intregm_disabled;
66 #ifdef DEBUG_IRQ_COUNT
67 uint64_t irq_count[32];
69 qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
70 const uint32_t *intbit_to_level;
71 uint32_t cputimer_lbit, cputimer_mbit;
72 uint32_t cputimer_bit;
73 uint32_t pil_out[MAX_CPUS];
74 SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
77 #define INTCTL_MAXADDR 0xf
78 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
79 #define INTCTLM_SIZE 0x14
80 #define MASTER_IRQ_MASK ~0x0fa2007f
81 #define MASTER_DISABLE 0x80000000
82 #define CPU_SOFTIRQ_MASK 0xfffe0000
83 #define CPU_IRQ_INT15_IN 0x0004000
84 #define CPU_IRQ_INT15_MASK 0x80000000
86 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
88 // per-cpu interrupt controller
89 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
91 SLAVIO_CPUINTCTLState *s = opaque;
97 ret = s->intreg_pending;
103 DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
108 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
111 SLAVIO_CPUINTCTLState *s = opaque;
115 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
117 case 1: // clear pending softints
118 if (val & CPU_IRQ_INT15_IN)
119 val |= CPU_IRQ_INT15_MASK;
120 val &= CPU_SOFTIRQ_MASK;
121 s->intreg_pending &= ~val;
122 slavio_check_interrupts(s->master, 1);
123 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
126 case 2: // set softint
127 val &= CPU_SOFTIRQ_MASK;
128 s->intreg_pending |= val;
129 slavio_check_interrupts(s->master, 1);
130 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
138 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
141 slavio_intctl_mem_readl,
144 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
147 slavio_intctl_mem_writel,
150 // master system interrupt controller
151 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
153 SLAVIO_INTCTLState *s = opaque;
159 ret = s->intregm_pending & ~MASTER_DISABLE;
162 ret = s->intregm_disabled & MASTER_IRQ_MASK;
171 DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
176 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
179 SLAVIO_INTCTLState *s = opaque;
183 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
185 case 2: // clear (enable)
186 // Force clear unused bits
187 val &= MASTER_IRQ_MASK;
188 s->intregm_disabled &= ~val;
189 DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
190 s->intregm_disabled);
191 slavio_check_interrupts(s, 1);
193 case 3: // set (disable, clear pending)
194 // Force clear unused bits
195 val &= MASTER_IRQ_MASK;
196 s->intregm_disabled |= val;
197 s->intregm_pending &= ~val;
198 slavio_check_interrupts(s, 1);
199 DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
200 s->intregm_disabled);
203 s->target_cpu = val & (MAX_CPUS - 1);
204 slavio_check_interrupts(s, 1);
205 DPRINTF("Set master irq cpu %d\n", s->target_cpu);
212 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
215 slavio_intctlm_mem_readl,
218 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
221 slavio_intctlm_mem_writel,
224 void slavio_pic_info(Monitor *mon, void *opaque)
226 SLAVIO_INTCTLState *s = opaque;
229 for (i = 0; i < MAX_CPUS; i++) {
230 monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
231 s->slaves[i].intreg_pending);
233 monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
234 s->intregm_pending, s->intregm_disabled);
237 void slavio_irq_info(Monitor *mon, void *opaque)
239 #ifndef DEBUG_IRQ_COUNT
240 monitor_printf(mon, "irq statistic code not compiled.\n");
242 SLAVIO_INTCTLState *s = opaque;
246 monitor_printf(mon, "IRQ statistics:\n");
247 for (i = 0; i < 32; i++) {
248 count = s->irq_count[i];
250 monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
255 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
257 uint32_t pending = s->intregm_pending, pil_pending;
260 pending &= ~s->intregm_disabled;
262 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
263 for (i = 0; i < MAX_CPUS; i++) {
265 if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
266 (i == s->target_cpu)) {
267 for (j = 0; j < 32; j++) {
268 if (pending & (1 << j))
269 pil_pending |= 1 << s->intbit_to_level[j];
272 pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
275 for (j = 0; j < MAX_PILS; j++) {
276 if (pil_pending & (1 << j)) {
277 if (!(s->pil_out[i] & (1 << j))) {
278 qemu_irq_raise(s->cpu_irqs[i][j]);
281 if (s->pil_out[i] & (1 << j)) {
282 qemu_irq_lower(s->cpu_irqs[i][j]);
287 s->pil_out[i] = pil_pending;
292 * "irq" here is the bit number in the system interrupt register to
293 * separate serial and keyboard interrupts sharing a level.
295 static void slavio_set_irq(void *opaque, int irq, int level)
297 SLAVIO_INTCTLState *s = opaque;
298 uint32_t mask = 1 << irq;
299 uint32_t pil = s->intbit_to_level[irq];
301 DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
305 #ifdef DEBUG_IRQ_COUNT
308 s->intregm_pending |= mask;
309 s->slaves[s->target_cpu].intreg_pending |= 1 << pil;
311 s->intregm_pending &= ~mask;
312 s->slaves[s->target_cpu].intreg_pending &= ~(1 << pil);
314 slavio_check_interrupts(s, 1);
318 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
320 SLAVIO_INTCTLState *s = opaque;
322 DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
325 s->intregm_pending |= s->cputimer_mbit;
326 s->slaves[cpu].intreg_pending |= s->cputimer_lbit;
328 s->intregm_pending &= ~s->cputimer_mbit;
329 s->slaves[cpu].intreg_pending &= ~s->cputimer_lbit;
332 slavio_check_interrupts(s, 1);
335 static void slavio_set_irq_all(void *opaque, int irq, int level)
338 slavio_set_irq(opaque, irq, level);
340 slavio_set_timer_irq_cpu(opaque, irq - 32, level);
344 static void slavio_intctl_save(QEMUFile *f, void *opaque)
346 SLAVIO_INTCTLState *s = opaque;
349 for (i = 0; i < MAX_CPUS; i++) {
350 qemu_put_be32s(f, &s->slaves[i].intreg_pending);
352 qemu_put_be32s(f, &s->intregm_pending);
353 qemu_put_be32s(f, &s->intregm_disabled);
354 qemu_put_be32s(f, &s->target_cpu);
357 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
359 SLAVIO_INTCTLState *s = opaque;
365 for (i = 0; i < MAX_CPUS; i++) {
366 qemu_get_be32s(f, &s->slaves[i].intreg_pending);
368 qemu_get_be32s(f, &s->intregm_pending);
369 qemu_get_be32s(f, &s->intregm_disabled);
370 qemu_get_be32s(f, &s->target_cpu);
371 slavio_check_interrupts(s, 0);
375 static void slavio_intctl_reset(void *opaque)
377 SLAVIO_INTCTLState *s = opaque;
380 for (i = 0; i < MAX_CPUS; i++) {
381 s->slaves[i].intreg_pending = 0;
383 s->intregm_disabled = ~MASTER_IRQ_MASK;
384 s->intregm_pending = 0;
386 slavio_check_interrupts(s, 0);
389 static void slavio_intctl_init1(SysBusDevice *dev)
391 SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
395 qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
396 io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
397 slavio_intctlm_mem_write, s);
398 sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
399 s->cputimer_mbit = 1 << s->cputimer_bit;
400 s->cputimer_lbit = 1 << s->intbit_to_level[s->cputimer_bit];
402 for (i = 0; i < MAX_CPUS; i++) {
403 for (j = 0; j < MAX_PILS; j++) {
404 sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
406 io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
407 slavio_intctl_mem_write,
409 sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
410 s->slaves[i].cpu = i;
411 s->slaves[i].master = s;
413 register_savevm("slavio_intctl", -1, 1, slavio_intctl_save,
414 slavio_intctl_load, s);
415 qemu_register_reset(slavio_intctl_reset, s);
416 slavio_intctl_reset(s);
419 static SysBusDeviceInfo slavio_intctl_info = {
420 .init = slavio_intctl_init1,
421 .qdev.name = "slavio_intctl",
422 .qdev.size = sizeof(SLAVIO_INTCTLState),
423 .qdev.props = (Property[]) {
425 .name = "intbit_to_level",
426 .info = &qdev_prop_ptr,
427 .offset = offsetof(SLAVIO_INTCTLState, intbit_to_level),
430 .name = "cputimer_bit",
431 .info = &qdev_prop_uint32,
432 .offset = offsetof(SLAVIO_INTCTLState, cputimer_bit),
434 {/* end of property list */}
438 static void slavio_intctl_register_devices(void)
440 sysbus_register_withprop(&slavio_intctl_info);
443 device_init(slavio_intctl_register_devices)