2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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29 #define DPRINTF(fmt, args...) \
30 do { printf("TIMER: " fmt , ##args); } while (0)
32 #define DPRINTF(fmt, args...)
36 * Registers of hardware timer in sun4m.
38 * This is the timer/counter part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
43 * are zero. Bit 31 is 1 when count has been reached.
45 * Per-CPU timers interrupt local CPU, system timer uses normal
52 typedef struct SLAVIO_TIMERState {
55 uint32_t count, counthigh, reached;
58 int mode; // 0 = processor, 1 = user, 2 = system
59 struct SLAVIO_TIMERState *slave[MAX_CPUS];
63 #define TIMER_MAXADDR 0x1f
64 #define TIMER_SIZE (TIMER_MAXADDR + 1)
65 #define CPU_TIMER_SIZE 0x10
67 // Update count, set irq, update expire_time
68 // Convert from ptimer countdown units
69 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
73 count = s->limit - (ptimer_get_count(s->timer) << 9);
74 DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
76 s->count = count & 0xfffffe00;
77 s->counthigh = count >> 32;
81 static void slavio_timer_irq(void *opaque)
83 SLAVIO_TIMERState *s = opaque;
85 slavio_timer_get_out(s);
86 DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
87 s->reached = 0x80000000;
89 qemu_irq_raise(s->irq);
92 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
94 SLAVIO_TIMERState *s = opaque;
97 saddr = (addr & TIMER_MAXADDR) >> 2;
100 // read limit (system counter mode) or read most signifying
101 // part of counter (user mode)
104 qemu_irq_lower(s->irq);
106 ret = s->limit & 0x7fffffff;
109 slavio_timer_get_out(s);
110 ret = s->counthigh & 0x7fffffff;
114 // read counter and reached bit (system mode) or read lsbits
115 // of counter (user mode)
116 slavio_timer_get_out(s);
118 ret = (s->count & 0x7fffffff) | s->reached;
123 // read start/stop status
127 // read user/system mode
134 DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
139 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
141 SLAVIO_TIMERState *s = opaque;
145 DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
146 saddr = (addr & TIMER_MAXADDR) >> 2;
150 // set user counter limit MSW, reset counter
151 qemu_irq_lower(s->irq);
152 s->limit &= 0xfffffe00ULL;
153 s->limit |= (uint64_t)val << 32;
155 s->limit = 0x7ffffffffffffe00ULL;
156 ptimer_set_limit(s->timer, s->limit >> 9, 1);
159 // set limit, reset counter
161 qemu_irq_lower(s->irq);
164 // set limit without resetting counter
165 s->limit = val & 0x7ffffe00ULL;
167 s->limit = 0x7ffffe00ULL;
168 ptimer_set_limit(s->timer, s->limit >> 9, reload);
171 // set user counter limit LSW, reset counter
173 qemu_irq_lower(s->irq);
174 s->limit &= 0x7fffffff00000000ULL;
175 s->limit |= val & 0xfffffe00ULL;
177 s->limit = 0x7ffffffffffffe00ULL;
178 ptimer_set_limit(s->timer, s->limit >> 9, 1);
182 // start/stop user counter
185 ptimer_stop(s->timer);
189 ptimer_run(s->timer, 0);
195 // bit 0: user (1) or system (0) counter mode
199 for (i = 0; i < MAX_CPUS; i++) {
200 if (val & (1 << i)) {
201 qemu_irq_lower(s->slave[i]->irq);
202 s->slave[i]->limit = -1ULL;
203 s->slave[i]->mode = 1;
205 s->slave[i]->mode = 0;
207 ptimer_stop(s->slave[i]->timer);
208 ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9,
210 ptimer_run(s->slave[i]->timer, 0);
212 s->slave_mode = val & ((1 << MAX_CPUS) - 1);
220 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
221 slavio_timer_mem_readl,
222 slavio_timer_mem_readl,
223 slavio_timer_mem_readl,
226 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
227 slavio_timer_mem_writel,
228 slavio_timer_mem_writel,
229 slavio_timer_mem_writel,
232 static void slavio_timer_save(QEMUFile *f, void *opaque)
234 SLAVIO_TIMERState *s = opaque;
236 qemu_put_be64s(f, &s->limit);
237 qemu_put_be32s(f, &s->count);
238 qemu_put_be32s(f, &s->counthigh);
239 qemu_put_be32(f, 0); // Was irq
240 qemu_put_be32s(f, &s->reached);
241 qemu_put_be32s(f, &s->stopped);
242 qemu_put_be32s(f, &s->mode);
243 qemu_put_ptimer(f, s->timer);
246 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
248 SLAVIO_TIMERState *s = opaque;
254 qemu_get_be64s(f, &s->limit);
255 qemu_get_be32s(f, &s->count);
256 qemu_get_be32s(f, &s->counthigh);
257 qemu_get_be32s(f, &tmp); // Was irq
258 qemu_get_be32s(f, &s->reached);
259 qemu_get_be32s(f, &s->stopped);
260 qemu_get_be32s(f, &s->mode);
261 qemu_get_ptimer(f, s->timer);
266 static void slavio_timer_reset(void *opaque)
268 SLAVIO_TIMERState *s = opaque;
270 s->limit = 0x7ffffe00ULL;
274 ptimer_set_limit(s->timer, s->limit >> 9, 1);
275 ptimer_run(s->timer, 0);
277 qemu_irq_lower(s->irq);
280 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
281 qemu_irq irq, int mode)
283 int slavio_timer_io_memory;
284 SLAVIO_TIMERState *s;
287 s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
292 bh = qemu_bh_new(slavio_timer_irq, s);
293 s->timer = ptimer_init(bh);
294 ptimer_set_period(s->timer, 500ULL);
296 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
297 slavio_timer_mem_write, s);
299 cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
301 cpu_register_physical_memory(addr, TIMER_SIZE,
302 slavio_timer_io_memory);
303 register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
304 qemu_register_reset(slavio_timer_reset, s);
305 slavio_timer_reset(s);
310 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
313 SLAVIO_TIMERState *master;
316 master = slavio_timer_init(base + 0x10000ULL, master_irq, 2);
318 for (i = 0; i < MAX_CPUS; i++) {
319 master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
320 (i * TARGET_PAGE_SIZE),