2 * QEMU Sparc32 DMA controller emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * This is the DMA controller part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("DMA: " fmt , ##args); } while (0)
41 #define DPRINTF(fmt, args...)
45 #define DMA_SIZE (4 * sizeof(uint32_t))
46 #define DMA_MAXADDR (DMA_SIZE - 1)
48 #define DMA_VER 0xa0000000
50 #define DMA_INTREN 0x10
51 #define DMA_WRITE_MEM 0x100
52 #define DMA_LOADED 0x04000000
53 #define DMA_DRAIN_FIFO 0x40
54 #define DMA_RESET 0x80
56 typedef struct DMAState DMAState;
59 uint32_t dmaregs[DMA_REGS];
61 void *iommu, *dev_opaque;
62 void (*dev_reset)(void *dev_opaque);
66 /* Note: on sparc, the lance 16 bit bus is swapped */
67 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
68 uint8_t *buf, int len, int do_bswap)
73 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
74 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
75 addr |= s->dmaregs[3];
77 sparc_iommu_memory_read(s->iommu, addr, buf, len);
81 sparc_iommu_memory_read(s->iommu, addr, buf, len);
82 for(i = 0; i < len; i += 2) {
83 bswap16s((uint16_t *)(buf + i));
88 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
89 uint8_t *buf, int len, int do_bswap)
95 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
96 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
97 addr |= s->dmaregs[3];
99 sparc_iommu_memory_write(s->iommu, addr, buf, len);
105 if (l > sizeof(tmp_buf))
107 for(i = 0; i < l; i += 2) {
108 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
110 sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
118 void espdma_raise_irq(void *opaque)
120 DMAState *s = opaque;
122 DPRINTF("Raise ESP IRQ\n");
123 s->dmaregs[0] |= DMA_INTR;
124 qemu_irq_raise(s->irq);
127 void espdma_clear_irq(void *opaque)
129 DMAState *s = opaque;
131 s->dmaregs[0] &= ~DMA_INTR;
132 DPRINTF("Lower ESP IRQ\n");
133 qemu_irq_lower(s->irq);
136 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
138 DMAState *s = opaque;
140 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
141 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
142 sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
143 s->dmaregs[0] |= DMA_INTR;
144 s->dmaregs[1] += len;
147 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
149 DMAState *s = opaque;
151 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
152 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
153 sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
154 s->dmaregs[0] |= DMA_INTR;
155 s->dmaregs[1] += len;
158 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
160 DMAState *s = opaque;
163 saddr = (addr & DMA_MAXADDR) >> 2;
164 DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
167 return s->dmaregs[saddr];
170 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
172 DMAState *s = opaque;
175 saddr = (addr & DMA_MAXADDR) >> 2;
176 DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
177 s->dmaregs[saddr], val);
180 if (!(val & DMA_INTREN)) {
181 DPRINTF("Lower IRQ\n");
182 qemu_irq_lower(s->irq);
184 if (val & DMA_RESET) {
185 s->dev_reset(s->dev_opaque);
186 } else if (val & DMA_DRAIN_FIFO) {
187 val &= ~DMA_DRAIN_FIFO;
189 val = DMA_DRAIN_FIFO;
194 s->dmaregs[0] |= DMA_LOADED;
199 s->dmaregs[saddr] = val;
202 static CPUReadMemoryFunc *dma_mem_read[3] = {
208 static CPUWriteMemoryFunc *dma_mem_write[3] = {
214 static void dma_reset(void *opaque)
216 DMAState *s = opaque;
218 memset(s->dmaregs, 0, DMA_SIZE);
219 s->dmaregs[0] = DMA_VER;
222 static void dma_save(QEMUFile *f, void *opaque)
224 DMAState *s = opaque;
227 for (i = 0; i < DMA_REGS; i++)
228 qemu_put_be32s(f, &s->dmaregs[i]);
231 static int dma_load(QEMUFile *f, void *opaque, int version_id)
233 DMAState *s = opaque;
238 for (i = 0; i < DMA_REGS; i++)
239 qemu_get_be32s(f, &s->dmaregs[i]);
244 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
249 s = qemu_mallocz(sizeof(DMAState));
256 dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
257 cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
259 register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
260 qemu_register_reset(dma_reset, s);
265 void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
268 DMAState *s = opaque;
270 s->dev_reset = dev_reset;
271 s->dev_opaque = dev_opaque;