2 * PXA270-based Clamshell PDA platforms.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GNU GPL v2.
12 #define spitz_printf(format, ...) \
13 fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
15 #if TARGET_PHYS_ADDR_BITS == 32
16 #define REG_FMT "0x%02x"
18 #define REG_FMT "0x%02lx"
22 #define FLASH_BASE 0x0c000000
23 #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
24 #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
25 #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
26 #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
27 #define FLASH_ECCCLRR 0x10 /* Clear ECC */
28 #define FLASH_FLASHIO 0x14 /* Flash I/O */
29 #define FLASH_FLASHCTL 0x18 /* Flash Control */
31 #define FLASHCTL_CE0 (1 << 0)
32 #define FLASHCTL_CLE (1 << 1)
33 #define FLASHCTL_ALE (1 << 2)
34 #define FLASHCTL_WP (1 << 3)
35 #define FLASHCTL_CE1 (1 << 4)
36 #define FLASHCTL_RYBY (1 << 5)
37 #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
40 target_phys_addr_t target_base;
41 struct nand_flash_s *nand;
43 struct ecc_state_s ecc;
46 static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
48 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
50 addr -= s->target_base;
53 #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
55 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
56 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
58 #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
60 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
61 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
67 return s->ecc.count & 0xff;
70 nand_getpins(s->nand, &ryby);
72 return s->ctl | FLASHCTL_RYBY;
77 return ecc_digest(&s->ecc, nand_getio(s->nand));
80 spitz_printf("Bad register offset " REG_FMT "\n", addr);
85 static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
87 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
88 addr -= s->target_base;
90 if (addr == FLASH_FLASHIO)
91 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
92 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
94 return sl_readb(opaque, addr);
97 static void sl_writeb(void *opaque, target_phys_addr_t addr,
100 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
101 addr -= s->target_base;
105 /* Value is ignored. */
110 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
111 nand_setpins(s->nand,
112 s->ctl & FLASHCTL_CLE,
113 s->ctl & FLASHCTL_ALE,
114 s->ctl & FLASHCTL_NCE,
115 s->ctl & FLASHCTL_WP,
120 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
124 spitz_printf("Bad register offset " REG_FMT "\n", addr);
128 static void sl_save(QEMUFile *f, void *opaque)
130 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
132 qemu_put_8s(f, &s->ctl);
136 static int sl_load(QEMUFile *f, void *opaque, int version_id)
138 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
140 qemu_get_8s(f, &s->ctl);
151 static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
155 CPUReadMemoryFunc *sl_readfn[] = {
160 CPUWriteMemoryFunc *sl_writefn[] = {
166 s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
167 s->target_base = FLASH_BASE;
169 if (size == FLASH_128M)
170 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
171 else if (size == FLASH_1024M)
172 s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
174 iomemtype = cpu_register_io_memory(0, sl_readfn,
176 cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
178 register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
183 #define SPITZ_KEY_STROBE_NUM 11
184 #define SPITZ_KEY_SENSE_NUM 7
186 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
187 12, 17, 91, 34, 36, 38, 39
190 static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
191 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
194 /* Eighth additional row maps the special keys */
195 static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
196 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
197 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
198 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
199 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
200 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
201 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
202 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
203 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
206 #define SPITZ_GPIO_AK_INT 13 /* Remote control */
207 #define SPITZ_GPIO_SYNC 16 /* Sync button */
208 #define SPITZ_GPIO_ON_KEY 95 /* Power button */
209 #define SPITZ_GPIO_SWA 97 /* Lid */
210 #define SPITZ_GPIO_SWB 96 /* Tablet mode */
212 /* The special buttons are mapped to unused keys */
213 static const int spitz_gpiomap[5] = {
214 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
215 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
217 static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
219 struct spitz_keyboard_s {
220 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
224 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
225 uint16_t strobe_state;
226 uint16_t sense_state;
228 uint16_t pre_map[0x100];
232 int fifopos, fifolen;
236 static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
239 uint16_t strobe, sense = 0;
240 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
241 strobe = s->keyrow[i] & s->strobe_state;
244 if (!(s->sense_state & (1 << i)))
245 qemu_irq_raise(s->sense[i]);
246 } else if (s->sense_state & (1 << i))
247 qemu_irq_lower(s->sense[i]);
250 s->sense_state = sense;
253 static void spitz_keyboard_strobe(void *opaque, int line, int level)
255 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
258 s->strobe_state |= 1 << line;
260 s->strobe_state &= ~(1 << line);
261 spitz_keyboard_sense_update(s);
264 static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
266 int spitz_keycode = s->keymap[keycode & 0x7f];
267 if (spitz_keycode == -1)
270 /* Handle the additional keys */
271 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
272 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
273 spitz_gpio_invert[spitz_keycode & 0xf]);
278 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
280 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
282 spitz_keyboard_sense_update(s);
285 #define SHIFT (1 << 7)
286 #define CTRL (1 << 8)
289 #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
291 static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
296 case 0x2a: /* Left Shift */
302 case 0x36: /* Right Shift */
308 case 0x1d: /* Control */
322 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
324 (keycode & ~SHIFT))];
326 if (code != mapcode) {
328 if ((code & SHIFT) && !(s->modifiers & 1))
329 QUEUE_KEY(0x2a | (keycode & 0x80));
330 if ((code & CTRL ) && !(s->modifiers & 4))
331 QUEUE_KEY(0x1d | (keycode & 0x80));
332 if ((code & FN ) && !(s->modifiers & 8))
333 QUEUE_KEY(0x38 | (keycode & 0x80));
334 if ((code & FN ) && (s->modifiers & 1))
335 QUEUE_KEY(0x2a | (~keycode & 0x80));
336 if ((code & FN ) && (s->modifiers & 2))
337 QUEUE_KEY(0x36 | (~keycode & 0x80));
339 if (keycode & 0x80) {
340 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
341 QUEUE_KEY(0x2a | 0x80);
342 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
343 QUEUE_KEY(0x1d | 0x80);
344 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
345 QUEUE_KEY(0x38 | 0x80);
346 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
348 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
352 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
356 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
360 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
364 if ((code & FN ) && (s->modifiers & 1) &&
365 !(s->imodifiers & 0x10)) {
366 QUEUE_KEY(0x2a | 0x80);
367 s->imodifiers |= 0x10;
369 if ((code & FN ) && (s->modifiers & 2) &&
370 !(s->imodifiers & 0x20)) {
371 QUEUE_KEY(0x36 | 0x80);
372 s->imodifiers |= 0x20;
378 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
381 static void spitz_keyboard_tick(void *opaque)
383 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
386 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
388 if (s->fifopos >= 16)
392 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
395 static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
398 for (i = 0; i < 0x100; i ++)
400 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
401 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
402 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
403 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
404 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
405 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
406 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
407 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
408 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
409 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
410 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
411 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
412 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
413 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
414 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
415 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
416 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
417 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
418 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
419 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
420 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
421 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
422 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
423 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
424 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
425 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
426 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
427 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
428 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
429 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
430 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
431 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
437 s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
438 spitz_keyboard_tick(s);
445 static void spitz_keyboard_save(QEMUFile *f, void *opaque)
447 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
450 qemu_put_be16s(f, &s->sense_state);
451 qemu_put_be16s(f, &s->strobe_state);
452 for (i = 0; i < 5; i ++)
453 qemu_put_byte(f, spitz_gpio_invert[i]);
456 static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
458 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
461 qemu_get_be16s(f, &s->sense_state);
462 qemu_get_be16s(f, &s->strobe_state);
463 for (i = 0; i < 5; i ++)
464 spitz_gpio_invert[i] = qemu_get_byte(f);
466 /* Release all pressed keys */
467 memset(s->keyrow, 0, sizeof(s->keyrow));
468 spitz_keyboard_sense_update(s);
477 static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
480 struct spitz_keyboard_s *s;
482 s = (struct spitz_keyboard_s *)
483 qemu_mallocz(sizeof(struct spitz_keyboard_s));
484 memset(s, 0, sizeof(struct spitz_keyboard_s));
486 for (i = 0; i < 0x80; i ++)
488 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
489 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
490 if (spitz_keymap[i][j] != -1)
491 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
493 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
494 s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
496 for (i = 0; i < 5; i ++)
497 s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
499 s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
500 SPITZ_KEY_STROBE_NUM);
501 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
502 pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
504 spitz_keyboard_pre_map(s);
505 qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
507 register_savevm("spitz_keyboard", 0, 0,
508 spitz_keyboard_save, spitz_keyboard_load, s);
513 struct scoop_info_s {
514 target_phys_addr_t target_base;
515 qemu_irq handler[16];
532 #define SCOOP_MCR 0x00
533 #define SCOOP_CDR 0x04
534 #define SCOOP_CSR 0x08
535 #define SCOOP_CPR 0x0c
536 #define SCOOP_CCR 0x10
537 #define SCOOP_IRR_IRM 0x14
538 #define SCOOP_IMR 0x18
539 #define SCOOP_ISR 0x1c
540 #define SCOOP_GPCR 0x20
541 #define SCOOP_GPWR 0x24
542 #define SCOOP_GPRR 0x28
544 static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
545 uint32_t level, diff;
547 level = s->gpio_level & s->gpio_dir;
549 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
551 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
554 s->prev_level = level;
557 static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
559 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
560 addr -= s->target_base;
582 return s->gpio_level;
586 spitz_printf("Bad register offset " REG_FMT "\n", addr);
592 static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
594 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
595 addr -= s->target_base;
624 scoop_gpio_handler_update(s);
627 s->gpio_level = value & s->gpio_dir;
628 scoop_gpio_handler_update(s);
634 spitz_printf("Bad register offset " REG_FMT "\n", addr);
638 CPUReadMemoryFunc *scoop_readfn[] = {
643 CPUWriteMemoryFunc *scoop_writefn[] = {
649 static void scoop_gpio_set(void *opaque, int line, int level)
651 struct scoop_info_s *s = (struct scoop_info_s *) s;
654 s->gpio_level |= (1 << line);
656 s->gpio_level &= ~(1 << line);
659 static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
664 static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line,
667 spitz_printf("No GPIO pin %i\n", line);
671 s->handler[line] = handler;
674 static void scoop_save(QEMUFile *f, void *opaque)
676 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
677 qemu_put_be16s(f, &s->status);
678 qemu_put_be16s(f, &s->power);
679 qemu_put_be32s(f, &s->gpio_level);
680 qemu_put_be32s(f, &s->gpio_dir);
681 qemu_put_be32s(f, &s->prev_level);
682 qemu_put_be16s(f, &s->mcr);
683 qemu_put_be16s(f, &s->cdr);
684 qemu_put_be16s(f, &s->ccr);
685 qemu_put_be16s(f, &s->irr);
686 qemu_put_be16s(f, &s->imr);
687 qemu_put_be16s(f, &s->isr);
688 qemu_put_be16s(f, &s->gprr);
691 static int scoop_load(QEMUFile *f, void *opaque, int version_id)
693 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
694 qemu_get_be16s(f, &s->status);
695 qemu_get_be16s(f, &s->power);
696 qemu_get_be32s(f, &s->gpio_level);
697 qemu_get_be32s(f, &s->gpio_dir);
698 qemu_get_be32s(f, &s->prev_level);
699 qemu_get_be16s(f, &s->mcr);
700 qemu_get_be16s(f, &s->cdr);
701 qemu_get_be16s(f, &s->ccr);
702 qemu_get_be16s(f, &s->irr);
703 qemu_get_be16s(f, &s->imr);
704 qemu_get_be16s(f, &s->isr);
705 qemu_get_be16s(f, &s->gprr);
710 static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
713 struct scoop_info_s *s;
715 s = (struct scoop_info_s *)
716 qemu_mallocz(sizeof(struct scoop_info_s) * 2);
717 memset(s, 0, sizeof(struct scoop_info_s) * count);
718 s[0].target_base = 0x10800000;
719 s[1].target_base = 0x08800040;
725 s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16);
726 iomemtype = cpu_register_io_memory(0, scoop_readfn,
727 scoop_writefn, &s[0]);
728 cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
729 register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
734 s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16);
735 iomemtype = cpu_register_io_memory(0, scoop_readfn,
736 scoop_writefn, &s[1]);
737 cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
738 register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
743 /* LCD backlight controller */
745 #define LCDTG_RESCTL 0x00
746 #define LCDTG_PHACTRL 0x01
747 #define LCDTG_DUTYCTRL 0x02
748 #define LCDTG_POWERREG0 0x03
749 #define LCDTG_POWERREG1 0x04
750 #define LCDTG_GPOR3 0x05
751 #define LCDTG_PICTRL 0x06
752 #define LCDTG_POLCTRL 0x07
754 static int bl_intensity, bl_power;
756 static void spitz_bl_update(struct pxa2xx_state_s *s)
758 if (bl_power && bl_intensity)
759 spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
761 spitz_printf("LCD Backlight now off\n");
764 static inline void spitz_bl_bit5(void *opaque, int line, int level)
766 int prev = bl_intensity;
769 bl_intensity &= ~0x20;
771 bl_intensity |= 0x20;
773 if (bl_power && prev != bl_intensity)
774 spitz_bl_update((struct pxa2xx_state_s *) opaque);
777 static inline void spitz_bl_power(void *opaque, int line, int level)
780 spitz_bl_update((struct pxa2xx_state_s *) opaque);
783 static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
792 spitz_printf("LCD in QVGA mode\n");
794 spitz_printf("LCD in VGA mode\n");
798 bl_intensity &= ~0x1f;
799 bl_intensity |= value;
801 spitz_bl_update((struct pxa2xx_state_s *) opaque);
804 case LCDTG_POWERREG0:
805 /* Set common voltage to M62332FP */
812 #define CORGI_SSP_PORT 2
814 #define SPITZ_GPIO_LCDCON_CS 53
815 #define SPITZ_GPIO_ADS7846_CS 14
816 #define SPITZ_GPIO_MAX1111_CS 20
817 #define SPITZ_GPIO_TP_INT 11
819 static int lcd_en, ads_en, max_en;
820 static struct max111x_s *max1111;
821 static struct ads7846_state_s *ads7846;
823 /* "Demux" the signal based on current chipselect */
824 static uint32_t corgi_ssp_read(void *opaque)
829 return ads7846_read(ads7846);
831 return max111x_read(max1111);
835 static void corgi_ssp_write(void *opaque, uint32_t value)
838 spitz_lcdtg_dac_put(opaque, value);
840 ads7846_write(ads7846, value);
842 max111x_write(max1111, value);
845 static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
860 #define MAX1111_BATT_VOLT 1
861 #define MAX1111_BATT_TEMP 2
862 #define MAX1111_ACIN_VOLT 3
864 #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
865 #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
866 #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
868 static void spitz_adc_temp_on(void *opaque, int line, int level)
874 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
876 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
879 static void spitz_ssp_save(QEMUFile *f, void *opaque)
881 qemu_put_be32(f, lcd_en);
882 qemu_put_be32(f, ads_en);
883 qemu_put_be32(f, max_en);
884 qemu_put_be32(f, bl_intensity);
885 qemu_put_be32(f, bl_power);
888 static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
890 lcd_en = qemu_get_be32(f);
891 ads_en = qemu_get_be32(f);
892 max_en = qemu_get_be32(f);
893 bl_intensity = qemu_get_be32(f);
894 bl_power = qemu_get_be32(f);
899 static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
901 qemu_irq *chipselects;
903 lcd_en = ads_en = max_en = 0;
905 ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
907 max1111 = max1111_init(0);
908 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
909 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
910 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
912 pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
913 corgi_ssp_write, cpu);
915 chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
916 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
917 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
918 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
923 register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
928 static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
930 struct pcmcia_card_s *md;
931 BlockDriverState *bs = bs_table[0];
933 if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
934 md = dscm1xxxx_init(bs);
935 pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
939 /* Wm8750 and Max7310 on I2C */
941 #define AKITA_MAX_ADDR 0x18
942 #define SPITZ_WM_ADDRL 0x1b
943 #define SPITZ_WM_ADDRH 0x1a
945 #define SPITZ_GPIO_WM 5
948 static void spitz_wm8750_addr(void *opaque, int line, int level)
950 i2c_slave *wm = (i2c_slave *) opaque;
952 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
954 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
958 static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
960 /* Attach the CPU on one end of our I2C bus. */
961 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
970 /* Attach a WM8750 to the bus */
971 wm = wm8750_init(bus, audio);
973 spitz_wm8750_addr(wm, 0, 0);
974 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
975 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
976 /* .. and to the sound interface. */
977 cpu->i2s->opaque = wm;
978 cpu->i2s->codec_out = wm8750_dac_dat;
979 cpu->i2s->codec_in = wm8750_adc_dat;
980 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
984 static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
986 /* Attach a Max7310 to Akita I2C bus. */
987 i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
991 /* Other peripherals */
993 static void spitz_out_switch(void *opaque, int line, int level)
997 spitz_printf("Charging %s.\n", level ? "off" : "on");
1000 spitz_printf("Discharging %s.\n", level ? "on" : "off");
1003 spitz_printf("Green LED %s.\n", level ? "on" : "off");
1006 spitz_printf("Orange LED %s.\n", level ? "on" : "off");
1009 spitz_bl_bit5(opaque, line, level);
1012 spitz_bl_power(opaque, line, level);
1015 spitz_adc_temp_on(opaque, line, level);
1020 #define SPITZ_SCP_LED_GREEN 1
1021 #define SPITZ_SCP_JK_B 2
1022 #define SPITZ_SCP_CHRG_ON 3
1023 #define SPITZ_SCP_MUTE_L 4
1024 #define SPITZ_SCP_MUTE_R 5
1025 #define SPITZ_SCP_CF_POWER 6
1026 #define SPITZ_SCP_LED_ORANGE 7
1027 #define SPITZ_SCP_JK_A 8
1028 #define SPITZ_SCP_ADC_TEMP_ON 9
1029 #define SPITZ_SCP2_IR_ON 1
1030 #define SPITZ_SCP2_AKIN_PULLUP 2
1031 #define SPITZ_SCP2_BACKLIGHT_CONT 7
1032 #define SPITZ_SCP2_BACKLIGHT_ON 8
1033 #define SPITZ_SCP2_MIC_BIAS 9
1035 static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
1036 struct scoop_info_s *scp, int num)
1038 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
1040 scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]);
1041 scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]);
1042 scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]);
1043 scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]);
1046 scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
1047 scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
1050 scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
1053 #define SPITZ_GPIO_HSYNC 22
1054 #define SPITZ_GPIO_SD_DETECT 9
1055 #define SPITZ_GPIO_SD_WP 81
1056 #define SPITZ_GPIO_ON_RESET 89
1057 #define SPITZ_GPIO_BAT_COVER 90
1058 #define SPITZ_GPIO_CF1_IRQ 105
1059 #define SPITZ_GPIO_CF1_CD 94
1060 #define SPITZ_GPIO_CF2_IRQ 106
1061 #define SPITZ_GPIO_CF2_CD 93
1063 static int spitz_hsync;
1065 static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
1067 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
1068 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
1072 static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
1076 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
1077 * read to satisfy broken guests that poll-wait for hsync.
1078 * Simulating a real hsync event would be less practical and
1079 * wouldn't guarantee that a guest ever exits the loop.
1082 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
1083 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
1084 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
1087 pxa2xx_mmci_handlers(cpu->mmc,
1088 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
1089 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
1091 /* Battery lock always closed */
1092 qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
1095 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
1097 /* PCMCIA signals: card's IRQ and Card-Detect */
1099 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
1100 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
1101 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
1103 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
1104 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
1105 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
1107 /* Initialise the screen rotation related signals */
1108 spitz_gpio_invert[3] = 0; /* Always open */
1109 if (graphic_rotate) { /* Tablet mode */
1110 spitz_gpio_invert[4] = 0;
1111 } else { /* Portrait mode */
1112 spitz_gpio_invert[4] = 1;
1114 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
1115 spitz_gpio_invert[3]);
1116 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
1117 spitz_gpio_invert[4]);
1120 /* Write the bootloader parameters memory area. */
1122 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
1124 struct __attribute__ ((__packed__)) sl_param_info {
1125 uint32_t comadj_keyword;
1128 uint32_t uuid_keyword;
1131 uint32_t touch_keyword;
1137 uint32_t adadj_keyword;
1140 uint32_t phad_keyword;
1142 } spitz_bootparam = {
1143 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
1145 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
1147 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
1149 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
1151 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
1155 static void sl_bootparam_write(uint32_t ptr)
1157 memcpy(phys_ram_base + ptr, &spitz_bootparam,
1158 sizeof(struct sl_param_info));
1161 #define SL_PXA_PARAM_BASE 0xa0000a00
1164 enum spitz_model_e { spitz, akita, borzoi, terrier };
1166 static void spitz_common_init(int ram_size, int vga_ram_size,
1167 DisplayState *ds, const char *kernel_filename,
1168 const char *kernel_cmdline, const char *initrd_filename,
1169 const char *cpu_model, enum spitz_model_e model, int arm_id)
1171 uint32_t spitz_ram = 0x04000000;
1172 uint32_t spitz_rom = 0x00800000;
1173 struct pxa2xx_state_s *cpu;
1174 struct scoop_info_s *scp;
1177 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
1179 /* Setup CPU & memory */
1180 if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
1181 fprintf(stderr, "This platform requires %i bytes of memory\n",
1182 spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE);
1185 cpu = pxa270_init(spitz_ram, ds, cpu_model);
1187 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
1189 cpu_register_physical_memory(0, spitz_rom,
1190 qemu_ram_alloc(spitz_rom) | IO_MEM_ROM);
1192 /* Setup peripherals */
1193 spitz_keyboard_register(cpu);
1195 spitz_ssp_attach(cpu);
1197 scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
1199 spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
1201 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
1203 spitz_i2c_setup(cpu);
1206 spitz_akita_i2c_setup(cpu);
1208 if (model == terrier)
1209 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
1210 spitz_microdrive_attach(cpu);
1211 else if (model != akita)
1212 /* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
1213 spitz_microdrive_attach(cpu);
1215 /* Setup initial (reset) machine state */
1216 cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
1218 arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline,
1219 initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
1220 sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
1223 static void spitz_init(int ram_size, int vga_ram_size,
1224 const char *boot_device, DisplayState *ds,
1225 const char **fd_filename, int snapshot,
1226 const char *kernel_filename, const char *kernel_cmdline,
1227 const char *initrd_filename, const char *cpu_model)
1229 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1230 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
1233 static void borzoi_init(int ram_size, int vga_ram_size,
1234 const char *boot_device, DisplayState *ds,
1235 const char **fd_filename, int snapshot,
1236 const char *kernel_filename, const char *kernel_cmdline,
1237 const char *initrd_filename, const char *cpu_model)
1239 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1240 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
1243 static void akita_init(int ram_size, int vga_ram_size,
1244 const char *boot_device, DisplayState *ds,
1245 const char **fd_filename, int snapshot,
1246 const char *kernel_filename, const char *kernel_cmdline,
1247 const char *initrd_filename, const char *cpu_model)
1249 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1250 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
1253 static void terrier_init(int ram_size, int vga_ram_size,
1254 const char *boot_device, DisplayState *ds,
1255 const char **fd_filename, int snapshot,
1256 const char *kernel_filename, const char *kernel_cmdline,
1257 const char *initrd_filename, const char *cpu_model)
1259 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
1260 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
1263 QEMUMachine akitapda_machine = {
1265 "Akita PDA (PXA270)",
1269 QEMUMachine spitzpda_machine = {
1271 "Spitz PDA (PXA270)",
1275 QEMUMachine borzoipda_machine = {
1277 "Borzoi PDA (PXA270)",
1281 QEMUMachine terrierpda_machine = {
1283 "Terrier PDA (PXA270)",