2 * Luminary Micro Stellaris preipherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
12 #include "primecell.h"
14 #include "qemu-timer.h"
27 #define BP_OLED_I2C 0x01
28 #define BP_OLED_SSI 0x02
29 #define BP_GAMEPAD 0x04
31 typedef const struct {
41 } stellaris_board_info;
43 /* General purpose timer module. */
45 /* Multiplication factor to convert from GPTM timer ticks to qemu timer
47 static int stellaris_clock_scale;
49 typedef struct gptm_state {
58 uint32_t match_prescale[2];
61 struct gptm_state *opaque[2];
64 /* The timers have an alternate output used to trigger the ADC. */
69 static void gptm_update_irq(gptm_state *s)
72 level = (s->state & s->mask) != 0;
73 qemu_set_irq(s->irq, level);
76 static void gptm_stop(gptm_state *s, int n)
78 qemu_del_timer(s->timer[n]);
81 static void gptm_reload(gptm_state *s, int n, int reset)
85 tick = qemu_get_clock(vm_clock);
90 /* 32-bit CountDown. */
92 count = s->load[0] | (s->load[1] << 16);
93 tick += (int64_t)count * stellaris_clock_scale;
94 } else if (s->config == 1) {
95 /* 32-bit RTC. 1Hz tick. */
96 tick += ticks_per_sec;
97 } else if (s->mode[n] == 0xa) {
98 /* PWM mode. Not implemented. */
100 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
104 qemu_mod_timer(s->timer[n], tick);
107 static void gptm_tick(void *opaque)
109 gptm_state **p = (gptm_state **)opaque;
115 if (s->config == 0) {
117 if ((s->control & 0x20)) {
118 /* Output trigger. */
119 qemu_irq_raise(s->trigger);
120 qemu_irq_lower(s->trigger);
122 if (s->mode[0] & 1) {
127 gptm_reload(s, 0, 0);
129 } else if (s->config == 1) {
133 match = s->match[0] | (s->match[1] << 16);
139 gptm_reload(s, 0, 0);
140 } else if (s->mode[n] == 0xa) {
141 /* PWM mode. Not implemented. */
143 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
149 static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
151 gptm_state *s = (gptm_state *)opaque;
157 case 0x04: /* TAMR */
159 case 0x08: /* TBMR */
168 return s->state & s->mask;
171 case 0x28: /* TAILR */
172 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
173 case 0x2c: /* TBILR */
175 case 0x30: /* TAMARCHR */
176 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
177 case 0x34: /* TBMATCHR */
179 case 0x38: /* TAPR */
180 return s->prescale[0];
181 case 0x3c: /* TBPR */
182 return s->prescale[1];
183 case 0x40: /* TAPMR */
184 return s->match_prescale[0];
185 case 0x44: /* TBPMR */
186 return s->match_prescale[1];
191 cpu_abort(cpu_single_env, "TODO: Timer value read\n");
193 cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
198 static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
200 gptm_state *s = (gptm_state *)opaque;
204 /* The timers should be disabled before changing the configuration.
205 We take advantage of this and defer everything until the timer
211 case 0x04: /* TAMR */
214 case 0x08: /* TBMR */
220 /* TODO: Implement pause. */
221 if ((oldval ^ value) & 1) {
223 gptm_reload(s, 0, 1);
228 if (((oldval ^ value) & 0x100) && s->config >= 4) {
230 gptm_reload(s, 1, 1);
237 s->mask = value & 0x77;
243 case 0x28: /* TAILR */
244 s->load[0] = value & 0xffff;
246 s->load[1] = value >> 16;
249 case 0x2c: /* TBILR */
250 s->load[1] = value & 0xffff;
252 case 0x30: /* TAMARCHR */
253 s->match[0] = value & 0xffff;
255 s->match[1] = value >> 16;
258 case 0x34: /* TBMATCHR */
259 s->match[1] = value >> 16;
261 case 0x38: /* TAPR */
262 s->prescale[0] = value;
264 case 0x3c: /* TBPR */
265 s->prescale[1] = value;
267 case 0x40: /* TAPMR */
268 s->match_prescale[0] = value;
270 case 0x44: /* TBPMR */
271 s->match_prescale[0] = value;
274 cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
279 static CPUReadMemoryFunc *gptm_readfn[] = {
285 static CPUWriteMemoryFunc *gptm_writefn[] = {
291 static void stellaris_gptm_init(uint32_t base, qemu_irq irq, qemu_irq trigger)
296 s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
299 s->trigger = trigger;
300 s->opaque[0] = s->opaque[1] = s;
302 iomemtype = cpu_register_io_memory(0, gptm_readfn,
304 cpu_register_physical_memory(base, 0x00001000, iomemtype);
305 s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]);
306 s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]);
307 /* ??? Save/restore. */
311 /* System controller. */
327 stellaris_board_info *board;
330 static void ssys_update(ssys_state *s)
332 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
335 static uint32_t pllcfg_sandstorm[16] = {
337 0x1ae0, /* 1.8432 Mhz */
339 0xd573, /* 2.4576 Mhz */
340 0x37a6, /* 3.57954 Mhz */
341 0x1ae2, /* 3.6864 Mhz */
343 0x98bc, /* 4.906 Mhz */
344 0x935b, /* 4.9152 Mhz */
346 0x4dee, /* 5.12 Mhz */
348 0x75db, /* 6.144 Mhz */
349 0x1ae6, /* 7.3728 Mhz */
351 0x585b /* 8.192 Mhz */
354 static uint32_t pllcfg_fury[16] = {
356 0x1b20, /* 1.8432 Mhz */
358 0xf42b, /* 2.4576 Mhz */
359 0x37e3, /* 3.57954 Mhz */
360 0x1b21, /* 3.6864 Mhz */
362 0x98ee, /* 4.906 Mhz */
363 0xd5b4, /* 4.9152 Mhz */
365 0x4e27, /* 5.12 Mhz */
367 0xec1c, /* 6.144 Mhz */
368 0x1b23, /* 7.3728 Mhz */
370 0xb11c /* 8.192 Mhz */
373 static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
375 ssys_state *s = (ssys_state *)opaque;
379 case 0x000: /* DID0 */
380 return s->board->did0;
381 case 0x004: /* DID1 */
382 return s->board->did1;
383 case 0x008: /* DC0 */
384 return s->board->dc0;
385 case 0x010: /* DC1 */
386 return s->board->dc1;
387 case 0x014: /* DC2 */
388 return s->board->dc2;
389 case 0x018: /* DC3 */
390 return s->board->dc3;
391 case 0x01c: /* DC4 */
392 return s->board->dc4;
393 case 0x030: /* PBORCTL */
395 case 0x034: /* LDOPCTL */
397 case 0x040: /* SRCR0 */
399 case 0x044: /* SRCR1 */
401 case 0x048: /* SRCR2 */
403 case 0x050: /* RIS */
404 return s->int_status;
405 case 0x054: /* IMC */
407 case 0x058: /* MISC */
408 return s->int_status & s->int_mask;
409 case 0x05c: /* RESC */
411 case 0x060: /* RCC */
413 case 0x064: /* PLLCFG */
416 xtal = (s->rcc >> 6) & 0xf;
417 if (s->board->did0 & (1 << 16)) {
418 return pllcfg_fury[xtal];
420 return pllcfg_sandstorm[xtal];
423 case 0x100: /* RCGC0 */
425 case 0x104: /* RCGC1 */
427 case 0x108: /* RCGC2 */
429 case 0x110: /* SCGC0 */
431 case 0x114: /* SCGC1 */
433 case 0x118: /* SCGC2 */
435 case 0x120: /* DCGC0 */
437 case 0x124: /* DCGC1 */
439 case 0x128: /* DCGC2 */
441 case 0x150: /* CLKVCLR */
443 case 0x160: /* LDOARST */
446 cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
451 static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
453 ssys_state *s = (ssys_state *)opaque;
457 case 0x030: /* PBORCTL */
458 s->pborctl = value & 0xffff;
460 case 0x034: /* LDOPCTL */
461 s->ldopctl = value & 0x1f;
463 case 0x040: /* SRCR0 */
464 case 0x044: /* SRCR1 */
465 case 0x048: /* SRCR2 */
466 fprintf(stderr, "Peripheral reset not implemented\n");
468 case 0x054: /* IMC */
469 s->int_mask = value & 0x7f;
471 case 0x058: /* MISC */
472 s->int_status &= ~value;
474 case 0x05c: /* RESC */
475 s->resc = value & 0x3f;
477 case 0x060: /* RCC */
478 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
480 s->int_status |= (1 << 6);
483 stellaris_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
485 case 0x100: /* RCGC0 */
488 case 0x104: /* RCGC1 */
491 case 0x108: /* RCGC2 */
494 case 0x110: /* SCGC0 */
497 case 0x114: /* SCGC1 */
500 case 0x118: /* SCGC2 */
503 case 0x120: /* DCGC0 */
506 case 0x124: /* DCGC1 */
509 case 0x128: /* DCGC2 */
512 case 0x150: /* CLKVCLR */
515 case 0x160: /* LDOARST */
519 cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
524 static CPUReadMemoryFunc *ssys_readfn[] = {
530 static CPUWriteMemoryFunc *ssys_writefn[] = {
536 static void ssys_reset(void *opaque)
538 ssys_state *s = (ssys_state *)opaque;
547 static void stellaris_sys_init(uint32_t base, qemu_irq irq,
548 stellaris_board_info * board)
553 s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
558 iomemtype = cpu_register_io_memory(0, ssys_readfn,
560 cpu_register_physical_memory(base, 0x00001000, iomemtype);
562 /* ??? Save/restore. */
566 /* I2C controller. */
579 } stellaris_i2c_state;
581 #define STELLARIS_I2C_MCS_BUSY 0x01
582 #define STELLARIS_I2C_MCS_ERROR 0x02
583 #define STELLARIS_I2C_MCS_ADRACK 0x04
584 #define STELLARIS_I2C_MCS_DATACK 0x08
585 #define STELLARIS_I2C_MCS_ARBLST 0x10
586 #define STELLARIS_I2C_MCS_IDLE 0x20
587 #define STELLARIS_I2C_MCS_BUSBSY 0x40
589 static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
591 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
598 /* We don't emulate timing, so the controller is never busy. */
599 return s->mcs | STELLARIS_I2C_MCS_IDLE;
602 case 0x0c: /* MTPR */
604 case 0x10: /* MIMR */
606 case 0x14: /* MRIS */
608 case 0x18: /* MMIS */
609 return s->mris & s->mimr;
613 cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
619 static void stellaris_i2c_update(stellaris_i2c_state *s)
623 level = (s->mris & s->mimr) != 0;
624 qemu_set_irq(s->irq, level);
627 static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
630 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
635 s->msa = value & 0xff;
638 if ((s->mcr & 0x10) == 0) {
639 /* Disabled. Do nothing. */
642 /* Grab the bus if this is starting a transfer. */
643 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
644 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
645 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
647 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
648 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
651 /* If we don't have the bus then indicate an error. */
652 if (!i2c_bus_busy(s->bus)
653 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
654 s->mcs |= STELLARIS_I2C_MCS_ERROR;
657 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
659 /* Transfer a byte. */
660 /* TODO: Handle errors. */
663 s->mdr = i2c_recv(s->bus) & 0xff;
666 i2c_send(s->bus, s->mdr);
668 /* Raise an interrupt. */
672 /* Finish transfer. */
673 i2c_end_transfer(s->bus);
674 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
678 s->mdr = value & 0xff;
680 case 0x0c: /* MTPR */
681 s->mtpr = value & 0xff;
683 case 0x10: /* MIMR */
686 case 0x1c: /* MICR */
691 cpu_abort(cpu_single_env,
692 "stellaris_i2c_write: Loopback not implemented\n");
694 cpu_abort(cpu_single_env,
695 "stellaris_i2c_write: Slave mode not implemented\n");
696 s->mcr = value & 0x31;
699 cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
702 stellaris_i2c_update(s);
705 static void stellaris_i2c_reset(stellaris_i2c_state *s)
707 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
708 i2c_end_transfer(s->bus);
717 stellaris_i2c_update(s);
720 static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
726 static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
732 static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus)
734 stellaris_i2c_state *s;
737 s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
742 iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,
743 stellaris_i2c_writefn, s);
744 cpu_register_physical_memory(base, 0x00001000, iomemtype);
745 /* ??? For now we only implement the master interface. */
746 stellaris_i2c_reset(s);
749 /* Analogue to Digital Converter. This is only partially implemented,
750 enough for applications that use a combined ADC and timer tick. */
752 #define STELLARIS_ADC_EM_CONTROLLER 0
753 #define STELLARIS_ADC_EM_COMP 1
754 #define STELLARIS_ADC_EM_EXTERNAL 4
755 #define STELLARIS_ADC_EM_TIMER 5
756 #define STELLARIS_ADC_EM_PWM0 6
757 #define STELLARIS_ADC_EM_PWM1 7
758 #define STELLARIS_ADC_EM_PWM2 8
760 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
761 #define STELLARIS_ADC_FIFO_FULL 0x1000
781 } stellaris_adc_state;
783 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
787 tail = s->fifo[n].state & 0xf;
788 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
791 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
792 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
793 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
794 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
796 return s->fifo[n].data[tail];
799 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
804 head = (s->fifo[n].state >> 4) & 0xf;
805 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
809 s->fifo[n].data[head] = value;
810 head = (head + 1) & 0xf;
811 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
812 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
813 if ((s->fifo[n].state & 0xf) == head)
814 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
817 static void stellaris_adc_update(stellaris_adc_state *s)
821 level = (s->ris & s->im) != 0;
822 qemu_set_irq(s->irq, level);
825 static void stellaris_adc_trigger(void *opaque, int irq, int level)
827 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
828 /* Some applications use the ADC as a random number source, so introduce
829 some variation into the signal. */
830 static uint32_t noise = 0;
832 if ((s->actss & 1) == 0) {
836 noise = noise * 314159 + 1;
837 /* ??? actual inputs not implemented. Return an arbitrary value. */
838 stellaris_adc_fifo_write(s, 0, 0x200 + ((noise >> 16) & 7));
840 stellaris_adc_update(s);
843 static void stellaris_adc_reset(stellaris_adc_state *s)
847 for (n = 0; n < 4; n++) {
850 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
854 static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
856 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
858 /* TODO: Implement this. */
860 if (offset >= 0x40 && offset < 0xc0) {
862 n = (offset - 0x40) >> 5;
863 switch (offset & 0x1f) {
864 case 0x00: /* SSMUX */
866 case 0x04: /* SSCTL */
868 case 0x08: /* SSFIFO */
869 return stellaris_adc_fifo_read(s, n);
870 case 0x0c: /* SSFSTAT */
871 return s->fifo[n].state;
877 case 0x00: /* ACTSS */
884 return s->ris & s->im;
885 case 0x10: /* OSTAT */
887 case 0x14: /* EMUX */
889 case 0x18: /* USTAT */
891 case 0x20: /* SSPRI */
896 cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
902 static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
905 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
907 /* TODO: Implement this. */
909 if (offset >= 0x40 && offset < 0xc0) {
911 n = (offset - 0x40) >> 5;
912 switch (offset & 0x1f) {
913 case 0x00: /* SSMUX */
914 s->ssmux[n] = value & 0x33333333;
916 case 0x04: /* SSCTL */
918 cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
928 case 0x00: /* ACTSS */
929 s->actss = value & 0xf;
931 cpu_abort(cpu_single_env,
932 "Not implemented: ADC sequencers 1-3\n");
941 case 0x10: /* OSTAT */
944 case 0x14: /* EMUX */
947 case 0x18: /* USTAT */
950 case 0x20: /* SSPRI */
953 case 0x28: /* PSSI */
954 cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
960 cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
963 stellaris_adc_update(s);
966 static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
972 static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
978 static qemu_irq stellaris_adc_init(uint32_t base, qemu_irq irq)
980 stellaris_adc_state *s;
984 s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
988 iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
989 stellaris_adc_writefn, s);
990 cpu_register_physical_memory(base, 0x00001000, iomemtype);
991 stellaris_adc_reset(s);
992 qi = qemu_allocate_irqs(stellaris_adc_trigger, s, 1);
997 static stellaris_board_info stellaris_boards[] = {
1001 0x001f001f, /* dc0 */
1011 0x00ff007f, /* dc0 */
1016 BP_OLED_SSI | BP_GAMEPAD
1020 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1021 DisplayState *ds, stellaris_board_info *board)
1023 static const int uart_irq[] = {5, 6, 33, 34};
1024 static const int timer_irq[] = {19, 21, 23, 35};
1025 static const uint32_t gpio_addr[7] =
1026 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1027 0x40024000, 0x40025000, 0x40026000};
1028 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1031 qemu_irq *gpio_in[5];
1032 qemu_irq *gpio_out[5];
1039 flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1040 sram_size = (board->dc0 >> 18) + 1;
1041 pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
1043 if (board->dc1 & (1 << 16)) {
1044 adc = stellaris_adc_init(0x40038000, pic[14]);
1048 for (i = 0; i < 4; i++) {
1049 if (board->dc2 & (0x10000 << i)) {
1050 stellaris_gptm_init(0x40030000 + i * 0x1000,
1051 pic[timer_irq[i]], adc);
1055 stellaris_sys_init(0x400fe000, pic[28], board);
1057 for (i = 0; i < 7; i++) {
1058 if (board->dc4 & (1 << i)) {
1059 gpio_in[i] = pl061_init(gpio_addr[i], pic[gpio_irq[i]],
1064 if (board->dc2 & (1 << 12)) {
1065 i2c = i2c_init_bus();
1066 stellaris_i2c_init(0x40020000, pic[8], i2c);
1067 if (board->peripherals & BP_OLED_I2C) {
1068 ssd0303_init(ds, i2c, 0x3d);
1072 for (i = 0; i < 4; i++) {
1073 if (board->dc2 & (1 << i)) {
1074 pl011_init(0x4000c000 + i * 0x1000, pic[uart_irq[i]],
1075 serial_hds[i], PL011_LUMINARY);
1078 if (board->dc2 & (1 << 4)) {
1079 if (board->peripherals & BP_OLED_SSI) {
1081 /* FIXME: Implement chip select for OLED/MMC. */
1082 oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
1083 pl022_init(0x40008000, pic[7], ssd0323_xfer_ssi, oled);
1085 pl022_init(0x40008000, pic[7], NULL, NULL);
1088 if (board->peripherals & BP_GAMEPAD) {
1089 qemu_irq gpad_irq[5];
1090 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1092 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1093 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1094 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1095 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1096 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1098 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1102 /* FIXME: Figure out how to generate these from stellaris_boards. */
1103 static void lm3s811evb_init(int ram_size, int vga_ram_size,
1104 const char *boot_device, DisplayState *ds,
1105 const char *kernel_filename, const char *kernel_cmdline,
1106 const char *initrd_filename, const char *cpu_model)
1108 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
1111 static void lm3s6965evb_init(int ram_size, int vga_ram_size,
1112 const char *boot_device, DisplayState *ds,
1113 const char *kernel_filename, const char *kernel_cmdline,
1114 const char *initrd_filename, const char *cpu_model)
1116 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
1119 QEMUMachine lm3s811evb_machine = {
1121 "Stellaris LM3S811EVB",
1125 QEMUMachine lm3s6965evb_machine = {
1127 "Stellaris LM3S6965EVB",