2 * QEMU Sparc Sun4c interrupt controller emulation
4 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
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30 //#define DEBUG_IRQ_COUNT
34 #define DPRINTF(fmt, ...) \
35 do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
41 * Registers of interrupt controller in sun4c.
47 typedef struct Sun4c_INTCTLState {
49 #ifdef DEBUG_IRQ_COUNT
52 qemu_irq cpu_irqs[MAX_PILS];
53 const uint32_t *intbit_to_level;
61 static void sun4c_check_interrupts(void *opaque);
63 static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
65 Sun4c_INTCTLState *s = opaque;
69 DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
74 static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
77 Sun4c_INTCTLState *s = opaque;
79 DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
82 sun4c_check_interrupts(s);
85 static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = {
86 sun4c_intctl_mem_readb,
91 static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = {
92 sun4c_intctl_mem_writeb,
97 void sun4c_pic_info(Monitor *mon, void *opaque)
99 Sun4c_INTCTLState *s = opaque;
101 monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
105 void sun4c_irq_info(Monitor *mon, void *opaque)
107 #ifndef DEBUG_IRQ_COUNT
108 monitor_printf(mon, "irq statistic code not compiled.\n");
110 Sun4c_INTCTLState *s = opaque;
113 monitor_printf(mon, "IRQ statistics:\n");
114 count = s->irq_count;
116 monitor_printf(mon, " %" PRId64 "\n", count);
120 static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
122 static void sun4c_check_interrupts(void *opaque)
124 Sun4c_INTCTLState *s = opaque;
125 uint32_t pil_pending;
129 if (s->pending && !(s->reg & 0x80000000)) {
130 for (i = 0; i < 8; i++) {
131 if (s->pending & (1 << i))
132 pil_pending |= 1 << intbit_to_level[i];
136 for (i = 0; i < MAX_PILS; i++) {
137 if (pil_pending & (1 << i)) {
138 if (!(s->pil_out & (1 << i)))
139 qemu_irq_raise(s->cpu_irqs[i]);
141 if (s->pil_out & (1 << i))
142 qemu_irq_lower(s->cpu_irqs[i]);
145 s->pil_out = pil_pending;
149 * "irq" here is the bit number in the system interrupt register
151 static void sun4c_set_irq(void *opaque, int irq, int level)
153 Sun4c_INTCTLState *s = opaque;
154 uint32_t mask = 1 << irq;
155 uint32_t pil = intbit_to_level[irq];
157 DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
161 #ifdef DEBUG_IRQ_COUNT
168 sun4c_check_interrupts(s);
172 static void sun4c_intctl_save(QEMUFile *f, void *opaque)
174 Sun4c_INTCTLState *s = opaque;
176 qemu_put_8s(f, &s->reg);
177 qemu_put_8s(f, &s->pending);
180 static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
182 Sun4c_INTCTLState *s = opaque;
187 qemu_get_8s(f, &s->reg);
188 qemu_get_8s(f, &s->pending);
193 static void sun4c_intctl_reset(void *opaque)
195 Sun4c_INTCTLState *s = opaque;
201 static int sun4c_intctl_init1(SysBusDevice *dev)
203 Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
207 io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
208 sun4c_intctl_mem_write, s);
209 sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
210 qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
212 for (i = 0; i < MAX_PILS; i++) {
213 sysbus_init_irq(dev, &s->cpu_irqs[i]);
215 register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save,
216 sun4c_intctl_load, s);
217 qemu_register_reset(sun4c_intctl_reset, s);
218 sun4c_intctl_reset(s);
222 static SysBusDeviceInfo sun4c_intctl_info = {
223 .init = sun4c_intctl_init1,
224 .qdev.name = "sun4c_intctl",
225 .qdev.size = sizeof(Sun4c_INTCTLState),
228 static void sun4c_intctl_register_devices(void)
230 sysbus_register_withprop(&sun4c_intctl_info);
233 device_init(sun4c_intctl_register_devices)