2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-timer.h"
33 #include "firmware_abi.h"
40 #define DPRINTF(fmt, ...) \
41 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
43 #define DPRINTF(fmt, ...)
46 #define KERNEL_LOAD_ADDR 0x00404000
47 #define CMDLINE_ADDR 0x003ff000
48 #define INITRD_LOAD_ADDR 0x00300000
49 #define PROM_SIZE_MAX (4 * 1024 * 1024)
50 #define PROM_VADDR 0x000ffd00000ULL
51 #define APB_SPECIAL_BASE 0x1fe00000000ULL
52 #define APB_MEM_BASE 0x1ff00000000ULL
53 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
54 #define PROM_FILENAME "openbios-sparc64"
55 #define NVRAM_SIZE 0x2000
57 #define BIOS_CFG_IOPORT 0x510
58 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
59 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
60 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
64 #define TICK_INT_DIS 0x8000000000000000ULL
65 #define TICK_MAX 0x7fffffffffffffffULL
68 const char * const default_cpu_model;
71 uint64_t console_serial_base;
74 int DMA_get_channel_mode (int nchan)
78 int DMA_read_memory (int nchan, void *buf, int pos, int size)
82 int DMA_write_memory (int nchan, void *buf, int pos, int size)
86 void DMA_hold_DREQ (int nchan) {}
87 void DMA_release_DREQ (int nchan) {}
88 void DMA_schedule(int nchan) {}
89 void DMA_init (int high_page_enable) {}
90 void DMA_register_channel (int nchan,
91 DMA_transfer_handler transfer_handler,
96 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
98 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
102 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
105 const char *boot_devices,
106 uint32_t kernel_image, uint32_t kernel_size,
108 uint32_t initrd_image, uint32_t initrd_size,
109 uint32_t NVRAM_image,
110 int width, int height, int depth,
111 const uint8_t *macaddr)
115 uint8_t image[0x1ff0];
116 struct OpenBIOS_nvpart_v1 *part_header;
118 memset(image, '\0', sizeof(image));
122 // OpenBIOS nvram variables
123 // Variable partition
124 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
125 part_header->signature = OPENBIOS_PART_SYSTEM;
126 pstrcpy(part_header->name, sizeof(part_header->name), "system");
128 end = start + sizeof(struct OpenBIOS_nvpart_v1);
129 for (i = 0; i < nb_prom_envs; i++)
130 end = OpenBIOS_set_var(image, end, prom_envs[i]);
135 end = start + ((end - start + 15) & ~15);
136 OpenBIOS_finish_partition(part_header, end - start);
140 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
141 part_header->signature = OPENBIOS_PART_FREE;
142 pstrcpy(part_header->name, sizeof(part_header->name), "free");
145 OpenBIOS_finish_partition(part_header, end - start);
147 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
149 for (i = 0; i < sizeof(image); i++)
150 m48t59_write(nvram, i, image[i]);
154 static unsigned long sun4u_load_kernel(const char *kernel_filename,
155 const char *initrd_filename,
156 ram_addr_t RAM_size, long *initrd_size)
162 linux_boot = (kernel_filename != NULL);
166 kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
168 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
169 RAM_size - KERNEL_LOAD_ADDR);
171 kernel_size = load_image_targphys(kernel_filename,
173 RAM_size - KERNEL_LOAD_ADDR);
174 if (kernel_size < 0) {
175 fprintf(stderr, "qemu: could not load kernel '%s'\n",
182 if (initrd_filename) {
183 *initrd_size = load_image_targphys(initrd_filename,
185 RAM_size - INITRD_LOAD_ADDR);
186 if (*initrd_size < 0) {
187 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
192 if (*initrd_size > 0) {
193 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
194 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
195 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
196 stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
205 void pic_info(Monitor *mon)
209 void irq_info(Monitor *mon)
213 void cpu_check_irqs(CPUState *env)
215 uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
216 ((env->softint & SOFTINT_TIMER) << 14);
218 if (pil && (env->interrupt_index == 0 ||
219 (env->interrupt_index & ~15) == TT_EXTINT)) {
222 for (i = 15; i > 0; i--) {
223 if (pil & (1 << i)) {
224 int old_interrupt = env->interrupt_index;
226 env->interrupt_index = TT_EXTINT | i;
227 if (old_interrupt != env->interrupt_index) {
228 DPRINTF("Set CPU IRQ %d\n", i);
229 cpu_interrupt(env, CPU_INTERRUPT_HARD);
234 } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
235 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
236 env->interrupt_index = 0;
237 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
241 static void cpu_set_irq(void *opaque, int irq, int level)
243 CPUState *env = opaque;
246 DPRINTF("Raise CPU IRQ %d\n", irq);
248 env->pil_in |= 1 << irq;
251 DPRINTF("Lower CPU IRQ %d\n", irq);
252 env->pil_in &= ~(1 << irq);
257 typedef struct ResetData {
262 static void main_cpu_reset(void *opaque)
264 ResetData *s = (ResetData *)opaque;
265 CPUState *env = s->env;
268 env->tick_cmpr = TICK_INT_DIS | 0;
269 ptimer_set_limit(env->tick, TICK_MAX, 1);
270 ptimer_run(env->tick, 1);
271 env->stick_cmpr = TICK_INT_DIS | 0;
272 ptimer_set_limit(env->stick, TICK_MAX, 1);
273 ptimer_run(env->stick, 1);
274 env->hstick_cmpr = TICK_INT_DIS | 0;
275 ptimer_set_limit(env->hstick, TICK_MAX, 1);
276 ptimer_run(env->hstick, 1);
277 env->gregs[1] = 0; // Memory start
278 env->gregs[2] = ram_size; // Memory size
279 env->gregs[3] = 0; // Machine description XXX
280 env->pc = s->reset_addr;
281 env->npc = env->pc + 4;
284 static void tick_irq(void *opaque)
286 CPUState *env = opaque;
288 if (!(env->tick_cmpr & TICK_INT_DIS)) {
289 env->softint |= SOFTINT_TIMER;
290 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
294 static void stick_irq(void *opaque)
296 CPUState *env = opaque;
298 if (!(env->stick_cmpr & TICK_INT_DIS)) {
299 env->softint |= SOFTINT_STIMER;
300 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
304 static void hstick_irq(void *opaque)
306 CPUState *env = opaque;
308 if (!(env->hstick_cmpr & TICK_INT_DIS)) {
309 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
313 void cpu_tick_set_count(void *opaque, uint64_t count)
315 ptimer_set_count(opaque, -count);
318 uint64_t cpu_tick_get_count(void *opaque)
320 return -ptimer_get_count(opaque);
323 void cpu_tick_set_limit(void *opaque, uint64_t limit)
325 ptimer_set_limit(opaque, -limit, 0);
328 static const int ide_iobase[2] = { 0x1f0, 0x170 };
329 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
330 static const int ide_irq[2] = { 14, 15 };
332 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
333 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
335 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
336 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
338 static fdctrl_t *floppy_controller;
340 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
341 uint32_t addr, uint32_t size, int type)
343 DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
344 switch (region_num) {
346 isa_mmio_init(addr, 0x1000000);
349 isa_mmio_init(addr, 0x800000);
354 /* EBUS (Eight bit bus) bridge */
356 pci_ebus_init(PCIBus *bus, int devfn)
358 pci_create_simple(bus, devfn, "ebus");
362 pci_ebus_init1(PCIDevice *s)
364 isa_bus_new(&s->qdev);
366 pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
367 pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
368 s->config[0x04] = 0x06; // command = bus master, pci mem
369 s->config[0x05] = 0x00;
370 s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
371 s->config[0x07] = 0x03; // status = medium devsel
372 s->config[0x08] = 0x01; // revision
373 s->config[0x09] = 0x00; // programming i/f
374 pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
375 s->config[0x0D] = 0x0a; // latency_timer
376 s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
378 pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
380 pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
385 static PCIDeviceInfo ebus_info = {
387 .qdev.size = sizeof(PCIDevice),
388 .init = pci_ebus_init1,
391 static void pci_ebus_register(void)
393 pci_qdev_register(&ebus_info);
396 device_init(pci_ebus_register);
398 /* Boot PROM (OpenBIOS) */
399 static void prom_init(target_phys_addr_t addr, const char *bios_name)
406 dev = qdev_create(NULL, "openprom");
408 s = sysbus_from_qdev(dev);
410 sysbus_mmio_map(s, 0, addr);
413 if (bios_name == NULL) {
414 bios_name = PROM_FILENAME;
416 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
418 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
419 if (ret < 0 || ret > PROM_SIZE_MAX) {
420 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
426 if (ret < 0 || ret > PROM_SIZE_MAX) {
427 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
432 static int prom_init1(SysBusDevice *dev)
434 ram_addr_t prom_offset;
436 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
437 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
441 static SysBusDeviceInfo prom_info = {
443 .qdev.name = "openprom",
444 .qdev.size = sizeof(SysBusDevice),
445 .qdev.props = (Property[]) {
446 {/* end of property list */}
450 static void prom_register_devices(void)
452 sysbus_register_withprop(&prom_info);
455 device_init(prom_register_devices);
458 typedef struct RamDevice
465 static int ram_init1(SysBusDevice *dev)
467 ram_addr_t RAM_size, ram_offset;
468 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
472 ram_offset = qemu_ram_alloc(RAM_size);
473 sysbus_init_mmio(dev, RAM_size, ram_offset);
477 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
484 dev = qdev_create(NULL, "memory");
485 s = sysbus_from_qdev(dev);
487 d = FROM_SYSBUS(RamDevice, s);
491 sysbus_mmio_map(s, 0, addr);
494 static SysBusDeviceInfo ram_info = {
496 .qdev.name = "memory",
497 .qdev.size = sizeof(RamDevice),
498 .qdev.props = (Property[]) {
499 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
500 DEFINE_PROP_END_OF_LIST(),
504 static void ram_register_devices(void)
506 sysbus_register_withprop(&ram_info);
509 device_init(ram_register_devices);
511 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
515 ResetData *reset_info;
518 cpu_model = hwdef->default_cpu_model;
519 env = cpu_init(cpu_model);
521 fprintf(stderr, "Unable to find Sparc CPU definition\n");
524 bh = qemu_bh_new(tick_irq, env);
525 env->tick = ptimer_init(bh);
526 ptimer_set_period(env->tick, 1ULL);
528 bh = qemu_bh_new(stick_irq, env);
529 env->stick = ptimer_init(bh);
530 ptimer_set_period(env->stick, 1ULL);
532 bh = qemu_bh_new(hstick_irq, env);
533 env->hstick = ptimer_init(bh);
534 ptimer_set_period(env->hstick, 1ULL);
536 reset_info = qemu_mallocz(sizeof(ResetData));
537 reset_info->env = env;
538 reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
539 qemu_register_reset(main_cpu_reset, reset_info);
540 main_cpu_reset(reset_info);
541 // Override warm reset address with cold start address
542 env->pc = hwdef->prom_addr + 0x20ULL;
543 env->npc = env->pc + 4;
548 static void sun4uv_init(ram_addr_t RAM_size,
549 const char *boot_devices,
550 const char *kernel_filename, const char *kernel_cmdline,
551 const char *initrd_filename, const char *cpu_model,
552 const struct hwdef *hwdef)
557 long initrd_size, kernel_size;
558 PCIBus *pci_bus, *pci_bus2, *pci_bus3;
560 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
561 BlockDriverState *fd[MAX_FD];
566 env = cpu_devinit(cpu_model, hwdef);
569 ram_init(0, RAM_size);
571 prom_init(hwdef->prom_addr, bios_name);
574 irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
575 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
577 isa_mem_base = VGA_BASE;
578 pci_vga_init(pci_bus, 0, 0);
580 // XXX Should be pci_bus3
581 pci_ebus_init(pci_bus, -1);
584 if (hwdef->console_serial_base) {
585 serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
589 for(; i < MAX_SERIAL_PORTS; i++) {
591 serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
596 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
597 if (parallel_hds[i]) {
598 parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
603 for(i = 0; i < nb_nics; i++)
604 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
606 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
607 fprintf(stderr, "qemu: too many IDE bus\n");
610 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
611 dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS,
613 hd[i] = dinfo ? dinfo->bdrv : NULL;
616 pci_cmd646_ide_init(pci_bus, hd, 1);
618 /* FIXME: wire up interrupts. */
619 i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
620 for(i = 0; i < MAX_FD; i++) {
621 dinfo = drive_get(IF_FLOPPY, 0, i);
622 fd[i] = dinfo ? dinfo->bdrv : NULL;
624 floppy_controller = fdctrl_init_isa(6, 2, 0x3f0, fd);
625 nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
628 kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
629 ram_size, &initrd_size);
631 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
632 KERNEL_LOAD_ADDR, kernel_size,
634 INITRD_LOAD_ADDR, initrd_size,
635 /* XXX: need an option to load a NVRAM image */
637 graphic_width, graphic_height, graphic_depth,
638 (uint8_t *)&nd_table[0].macaddr);
640 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
641 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
642 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
643 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
644 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
645 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
646 if (kernel_cmdline) {
647 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
648 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
650 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
652 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
653 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
654 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
656 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
657 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
658 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
660 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
669 static const struct hwdef hwdefs[] = {
670 /* Sun4u generic PC-like machine */
672 .default_cpu_model = "TI UltraSparc II",
673 .machine_id = sun4u_id,
674 .prom_addr = 0x1fff0000000ULL,
675 .console_serial_base = 0,
677 /* Sun4v generic PC-like machine */
679 .default_cpu_model = "Sun UltraSparc T1",
680 .machine_id = sun4v_id,
681 .prom_addr = 0x1fff0000000ULL,
682 .console_serial_base = 0,
684 /* Sun4v generic Niagara machine */
686 .default_cpu_model = "Sun UltraSparc T1",
687 .machine_id = niagara_id,
688 .prom_addr = 0xfff0000000ULL,
689 .console_serial_base = 0xfff0c2c000ULL,
693 /* Sun4u hardware initialisation */
694 static void sun4u_init(ram_addr_t RAM_size,
695 const char *boot_devices,
696 const char *kernel_filename, const char *kernel_cmdline,
697 const char *initrd_filename, const char *cpu_model)
699 sun4uv_init(RAM_size, boot_devices, kernel_filename,
700 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
703 /* Sun4v hardware initialisation */
704 static void sun4v_init(ram_addr_t RAM_size,
705 const char *boot_devices,
706 const char *kernel_filename, const char *kernel_cmdline,
707 const char *initrd_filename, const char *cpu_model)
709 sun4uv_init(RAM_size, boot_devices, kernel_filename,
710 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
713 /* Niagara hardware initialisation */
714 static void niagara_init(ram_addr_t RAM_size,
715 const char *boot_devices,
716 const char *kernel_filename, const char *kernel_cmdline,
717 const char *initrd_filename, const char *cpu_model)
719 sun4uv_init(RAM_size, boot_devices, kernel_filename,
720 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
723 static QEMUMachine sun4u_machine = {
725 .desc = "Sun4u platform",
727 .max_cpus = 1, // XXX for now
731 static QEMUMachine sun4v_machine = {
733 .desc = "Sun4v platform",
735 .max_cpus = 1, // XXX for now
738 static QEMUMachine niagara_machine = {
740 .desc = "Sun4v platform, Niagara",
741 .init = niagara_init,
742 .max_cpus = 1, // XXX for now
745 static void sun4u_machine_init(void)
747 qemu_register_machine(&sun4u_machine);
748 qemu_register_machine(&sun4v_machine);
749 qemu_register_machine(&niagara_machine);
752 machine_init(sun4u_machine_init);