2 * Toshiba TC6393XB I/O Controller.
3 * Found in Sharp Zaurus SL-6000 (tosa) or some
4 * Toshiba e-Series PDAs.
6 * Most features are currently unsupported!!!
8 * This code is licensed under the GNU GPL v2.
15 #include "pixel_ops.h"
17 #define IRQ_TC6393_NAND 0
18 #define IRQ_TC6393_MMC 1
19 #define IRQ_TC6393_OHCI 2
20 #define IRQ_TC6393_SERIAL 3
21 #define IRQ_TC6393_FB 4
23 #define TC6393XB_NR_IRQS 8
25 #define TC6393XB_GPIOS 16
27 #define SCR_REVID 0x08 /* b Revision ID */
28 #define SCR_ISR 0x50 /* b Interrupt Status */
29 #define SCR_IMR 0x52 /* b Interrupt Mask */
30 #define SCR_IRR 0x54 /* b Interrupt Routing */
31 #define SCR_GPER 0x60 /* w GP Enable */
32 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
33 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
34 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
35 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
36 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
37 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
38 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
39 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
40 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
41 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
42 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
43 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
44 #define SCR_CCR 0x98 /* w Clock Control */
45 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
46 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
47 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
48 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
49 #define SCR_FER 0xe0 /* b Function Enable */
50 #define SCR_MCR 0xe4 /* w Mode Control */
51 #define SCR_CONFIG 0xfc /* b Configuration Control */
52 #define SCR_DEBUG 0xff /* b Debug */
54 #define NAND_CFG_COMMAND 0x04 /* w Command */
55 #define NAND_CFG_BASE 0x10 /* l Control Base Address */
56 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
57 #define NAND_CFG_INTE 0x48 /* b Int Enable */
58 #define NAND_CFG_EC 0x4a /* b Event Control */
59 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
60 #define NAND_CFG_ECCC 0x5b /* b ECC Control */
61 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
62 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
63 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
64 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
66 #define NAND_DATA 0x00 /* l Data */
67 #define NAND_MODE 0x04 /* b Mode */
68 #define NAND_STATUS 0x05 /* b Status */
69 #define NAND_ISR 0x06 /* b Interrupt Status */
70 #define NAND_IMR 0x07 /* b Interrupt Mask */
72 #define NAND_MODE_WP 0x80
73 #define NAND_MODE_CE 0x10
74 #define NAND_MODE_ALE 0x02
75 #define NAND_MODE_CLE 0x01
76 #define NAND_MODE_ECC_MASK 0x60
77 #define NAND_MODE_ECC_EN 0x20
78 #define NAND_MODE_ECC_READ 0x40
79 #define NAND_MODE_ECC_RST 0x60
111 qemu_irq handler[TC6393XB_GPIOS];
121 struct nand_flash_s *flash;
122 struct ecc_state_s ecc;
125 ram_addr_t vram_addr;
126 uint32_t scr_width, scr_height; /* in pixels */
132 qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
137 static void tc6393xb_gpio_set(void *opaque, int line, int level)
139 // struct tc6393xb_s *s = opaque;
141 if (line > TC6393XB_GPIOS) {
142 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
146 // FIXME: how does the chip reflect the GPIO input level change?
149 void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
152 if (line >= TC6393XB_GPIOS) {
153 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
157 s->handler[line] = handler;
160 static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
162 uint32_t level, diff;
165 level = s->gpio_level & s->gpio_dir;
167 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
169 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
172 s->prev_level = level;
175 qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
180 static void tc6393xb_l3v(void *opaque, int line, int level)
182 struct tc6393xb_s *s = opaque;
184 fprintf(stderr, "L3V: %d\n", level);
187 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
188 struct tc6393xb_s *s = opaque;
189 uint8_t isr = s->scr.ISR;
195 qemu_set_irq(s->irq, isr & s->scr.IMR);
198 #define SCR_REG_B(N) \
199 case SCR_ ##N: return s->scr.N
200 #define SCR_REG_W(N) \
201 case SCR_ ##N: return s->scr.N; \
202 case SCR_ ##N + 1: return s->scr.N >> 8;
203 #define SCR_REG_L(N) \
204 case SCR_ ##N: return s->scr.N; \
205 case SCR_ ##N + 1: return s->scr.N >> 8; \
206 case SCR_ ##N + 2: return s->scr.N >> 16; \
207 case SCR_ ##N + 3: return s->scr.N >> 24;
208 #define SCR_REG_A(N) \
209 case SCR_ ##N(0): return s->scr.N[0]; \
210 case SCR_ ##N(1): return s->scr.N[1]; \
211 case SCR_ ##N(2): return s->scr.N[2]
213 static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr)
231 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
232 case SCR_GPO_DOECR(0):
233 case SCR_GPO_DOECR(1):
234 case SCR_GPO_DOECR(2):
235 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
237 SCR_REG_A(GP_IARLCR);
239 SCR_REG_W(GPA_IARCR);
240 SCR_REG_W(GPA_IARLCR);
251 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
259 #define SCR_REG_B(N) \
260 case SCR_ ##N: s->scr.N = value; return;
261 #define SCR_REG_W(N) \
262 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
263 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
264 #define SCR_REG_L(N) \
265 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
266 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
267 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
268 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
269 #define SCR_REG_A(N) \
270 case SCR_ ##N(0): s->scr.N[0] = value; return; \
271 case SCR_ ##N(1): s->scr.N[1] = value; return; \
272 case SCR_ ##N(2): s->scr.N[2] = value; return
274 static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value)
288 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
289 tc6393xb_gpio_handler_update(s);
291 case SCR_GPO_DOECR(0):
292 case SCR_GPO_DOECR(1):
293 case SCR_GPO_DOECR(2):
294 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
295 tc6393xb_gpio_handler_update(s);
298 SCR_REG_A(GP_IARLCR);
300 SCR_REG_W(GPA_IARCR);
301 SCR_REG_W(GPA_IARLCR);
312 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
313 (uint32_t) addr, value & 0xff);
320 static void tc6393xb_nand_irq(struct tc6393xb_s *s) {
321 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
322 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
325 static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
327 case NAND_CFG_COMMAND:
328 return s->nand_enable ? 2 : 0;
330 case NAND_CFG_BASE + 1:
331 case NAND_CFG_BASE + 2:
332 case NAND_CFG_BASE + 3:
333 return s->nand_phys >> (addr - NAND_CFG_BASE);
335 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
338 static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
340 case NAND_CFG_COMMAND:
341 s->nand_enable = (value & 0x2);
344 case NAND_CFG_BASE + 1:
345 case NAND_CFG_BASE + 2:
346 case NAND_CFG_BASE + 3:
347 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
348 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
351 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
352 (uint32_t) addr, value & 0xff);
355 static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
361 return nand_getio(s->flash);
371 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
374 static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
375 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
376 // (uint32_t) addr, value & 0xff);
382 nand_setio(s->flash, value);
384 tc6393xb_nand_irq(s);
387 s->nand.mode = value;
388 nand_setpins(s->flash,
389 value & NAND_MODE_CLE,
390 value & NAND_MODE_ALE,
391 !(value & NAND_MODE_CE),
392 value & NAND_MODE_WP,
394 switch (value & NAND_MODE_ECC_MASK) {
395 case NAND_MODE_ECC_RST:
398 case NAND_MODE_ECC_READ:
401 case NAND_MODE_ECC_EN:
407 tc6393xb_nand_irq(s);
411 tc6393xb_nand_irq(s);
414 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
415 (uint32_t) addr, value & 0xff);
419 #include "tc6393xb_template.h"
421 #include "tc6393xb_template.h"
423 #include "tc6393xb_template.h"
425 #include "tc6393xb_template.h"
427 #include "tc6393xb_template.h"
429 static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update)
431 switch (ds_get_bits_per_pixel(s->ds)) {
433 tc6393xb_draw_graphic8(s);
436 tc6393xb_draw_graphic15(s);
439 tc6393xb_draw_graphic16(s);
442 tc6393xb_draw_graphic24(s);
445 tc6393xb_draw_graphic32(s);
448 printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
452 dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
455 static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update)
463 w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
464 d = ds_get_data(s->ds);
465 for(i = 0; i < s->scr_height; i++) {
467 d += ds_get_linesize(s->ds);
470 dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
473 static void tc6393xb_update_display(void *opaque)
475 struct tc6393xb_s *s = opaque;
478 if (s->scr_width == 0 || s->scr_height == 0)
482 if (s->blanked != s->blank) {
483 s->blanked = s->blank;
486 if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
487 qemu_console_resize(s->ds, s->scr_width, s->scr_height);
491 tc6393xb_draw_blank(s, full_update);
493 tc6393xb_draw_graphic(s, full_update);
497 static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
498 struct tc6393xb_s *s = opaque;
502 return tc6393xb_scr_readb(s, addr & 0xff);
504 return tc6393xb_nand_cfg_readb(s, addr & 0xff);
507 if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
508 // return tc6393xb_nand_readb(s, addr & 0xff);
509 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
510 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
514 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
518 static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
519 struct tc6393xb_s *s = opaque;
523 tc6393xb_scr_writeb(s, addr & 0xff, value);
526 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
530 if ((addr &~0xff) == s->nand_phys && s->nand_enable)
531 tc6393xb_nand_writeb(s, addr & 0xff, value);
533 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
534 (uint32_t) addr, value & 0xff);
537 static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr)
539 return (tc6393xb_readb(opaque, addr) & 0xff) |
540 (tc6393xb_readb(opaque, addr + 1) << 8);
543 static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr)
545 return (tc6393xb_readb(opaque, addr) & 0xff) |
546 ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) |
547 ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) |
548 ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24);
551 static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
553 tc6393xb_writeb(opaque, addr, value);
554 tc6393xb_writeb(opaque, addr + 1, value >> 8);
557 static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
559 tc6393xb_writeb(opaque, addr, value);
560 tc6393xb_writeb(opaque, addr + 1, value >> 8);
561 tc6393xb_writeb(opaque, addr + 2, value >> 16);
562 tc6393xb_writeb(opaque, addr + 3, value >> 24);
565 struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
568 struct tc6393xb_s *s;
569 CPUReadMemoryFunc *tc6393xb_readfn[] = {
574 CPUWriteMemoryFunc *tc6393xb_writefn[] = {
580 s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
582 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
584 s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
587 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
589 s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
591 iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
592 tc6393xb_writefn, s);
593 cpu_register_physical_memory(base, 0x10000, iomemtype);
595 s->vram_addr = qemu_ram_alloc(0x100000);
596 cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
599 s->ds = graphic_console_init(tc6393xb_update_display,
600 NULL, /* invalidate */
601 NULL, /* screen_dump */
602 NULL, /* text_update */