git.maemo.org Git - qemu/blob - hw/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27 #include "pixel_ops.h"
  28
  29 #define MAXX 1024
  30 #define MAXY 768
  31 #define TCX_DAC_NREGS 16
  32 #define TCX_THC_NREGS_8  0x081c
  33 #define TCX_THC_NREGS_24 0x1000
  34 #define TCX_TEC_NREGS    0x1000
  35
  36 typedef struct TCXState {
  37     target_phys_addr_t addr;
  38     DisplayState *ds;
  39     uint8_t *vram;
  40     uint32_t *vram24, *cplane;
  41     ram_addr_t vram_offset, vram24_offset, cplane_offset;
  42     uint16_t width, height, depth;
  43     uint8_t r[256], g[256], b[256];
  44     uint32_t palette[256];
  45     uint8_t dac_index, dac_state;
  46 } TCXState;
  47
  48 static void tcx_screen_dump(void *opaque, const char *filename);
  49 static void tcx24_screen_dump(void *opaque, const char *filename);
  50 static void tcx_invalidate_display(void *opaque);
  51 static void tcx24_invalidate_display(void *opaque);
  52
  53 static void update_palette_entries(TCXState *s, int start, int end)
  54 {
  55     int i;
  56     for(i = start; i < end; i++) {
  57         switch(ds_get_bits_per_pixel(s->ds)) {
  58         default:
  59         case 8:
  60             s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
  61             break;
  62         case 15:
  63             s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
  64             break;
  65         case 16:
  66             s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
  67             break;
  68         case 32:
  69             s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
  70             break;
  71         }
  72     }
  73     if (s->depth == 24)
  74         tcx24_invalidate_display(s);
  75     else
  76         tcx_invalidate_display(s);
  77 }
  78
  79 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
  80                             const uint8_t *s, int width)
  81 {
  82     int x;
  83     uint8_t val;
  84     uint32_t *p = (uint32_t *)d;
  85
  86     for(x = 0; x < width; x++) {
  87         val = *s++;
  88         *p++ = s1->palette[val];
  89     }
  90 }
  91
  92 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
  93                             const uint8_t *s, int width)
  94 {
  95     int x;
  96     uint8_t val;
  97     uint16_t *p = (uint16_t *)d;
  98
  99     for(x = 0; x < width; x++) {
 100         val = *s++;
 101         *p++ = s1->palette[val];
 102     }
 103 }
 104
 105 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
 106                            const uint8_t *s, int width)
 107 {
 108     int x;
 109     uint8_t val;
 110
 111     for(x = 0; x < width; x++) {
 112         val = *s++;
 113         *d++ = s1->palette[val];
 114     }
 115 }
 116
 117 /*
 118   XXX Could be much more optimal:
 119   * detect if line/page/whole screen is in 24 bit mode
 120   * if destination is also BGR, use memcpy
 121   */
 122 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 123                                      const uint8_t *s, int width,
 124                                      const uint32_t *cplane,
 125                                      const uint32_t *s24)
 126 {
 127     int x, r, g, b;
 128     uint8_t val, *p8;
 129     uint32_t *p = (uint32_t *)d;
 130     uint32_t dval;
 131
 132     for(x = 0; x < width; x++, s++, s24++) {
 133         if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
 134             // 24-bit direct, BGR order
 135             p8 = (uint8_t *)s24;
 136             p8++;
 137             b = *p8++;
 138             g = *p8++;
 139             r = *p8++;
 140             dval = rgb_to_pixel32(r, g, b);
 141         } else {
 142             val = *s;
 143             dval = s1->palette[val];
 144         }
 145         *p++ = dval;
 146     }
 147 }
 148
 149 static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
 150                               ram_addr_t cpage)
 151 {
 152     int ret;
 153     unsigned int off;
 154
 155     ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
 156     for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
 157         ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
 158         ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
 159     }
 160     return ret;
 161 }
 162
 163 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
 164                                ram_addr_t page_max, ram_addr_t page24,
 165                               ram_addr_t cpage)
 166 {
 167     cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 168                                     VGA_DIRTY_FLAG);
 169     page_min -= ts->vram_offset;
 170     page_max -= ts->vram_offset;
 171     cpu_physical_memory_reset_dirty(page24 + page_min * 4,
 172                                     page24 + page_max * 4 + TARGET_PAGE_SIZE,
 173                                     VGA_DIRTY_FLAG);
 174     cpu_physical_memory_reset_dirty(cpage + page_min * 4,
 175                                     cpage + page_max * 4 + TARGET_PAGE_SIZE,
 176                                     VGA_DIRTY_FLAG);
 177 }
 178
 179 /* Fixed line length 1024 allows us to do nice tricks not possible on
 180    VGA... */
 181 static void tcx_update_display(void *opaque)
 182 {
 183     TCXState *ts = opaque;
 184     ram_addr_t page, page_min, page_max;
 185     int y, y_start, dd, ds;
 186     uint8_t *d, *s;
 187     void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
 188
 189     if (ds_get_bits_per_pixel(ts->ds) == 0)
 190         return;
 191     page = ts->vram_offset;
 192     y_start = -1;
 193     page_min = 0xffffffff;
 194     page_max = 0;
 195     d = ds_get_data(ts->ds);
 196     s = ts->vram;
 197     dd = ds_get_linesize(ts->ds);
 198     ds = 1024;
 199
 200     switch (ds_get_bits_per_pixel(ts->ds)) {
 201     case 32:
 202         f = tcx_draw_line32;
 203         break;
 204     case 15:
 205     case 16:
 206         f = tcx_draw_line16;
 207         break;
 208     default:
 209     case 8:
 210         f = tcx_draw_line8;
 211         break;
 212     case 0:
 213         return;
 214     }
 215
 216     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
 217         if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
 218             if (y_start < 0)
 219                 y_start = y;
 220             if (page < page_min)
 221                 page_min = page;
 222             if (page > page_max)
 223                 page_max = page;
 224             f(ts, d, s, ts->width);
 225             d += dd;
 226             s += ds;
 227             f(ts, d, s, ts->width);
 228             d += dd;
 229             s += ds;
 230             f(ts, d, s, ts->width);
 231             d += dd;
 232             s += ds;
 233             f(ts, d, s, ts->width);
 234             d += dd;
 235             s += ds;
 236         } else {
 237             if (y_start >= 0) {
 238                 /* flush to display */
 239                 dpy_update(ts->ds, 0, y_start,
 240                            ts->width, y - y_start);
 241                 y_start = -1;
 242             }
 243             d += dd * 4;
 244             s += ds * 4;
 245         }
 246     }
 247     if (y_start >= 0) {
 248         /* flush to display */
 249         dpy_update(ts->ds, 0, y_start,
 250                    ts->width, y - y_start);
 251     }
 252     /* reset modified pages */
 253     if (page_min <= page_max) {
 254         cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 255                                         VGA_DIRTY_FLAG);
 256     }
 257 }
 258
 259 static void tcx24_update_display(void *opaque)
 260 {
 261     TCXState *ts = opaque;
 262     ram_addr_t page, page_min, page_max, cpage, page24;
 263     int y, y_start, dd, ds;
 264     uint8_t *d, *s;
 265     uint32_t *cptr, *s24;
 266
 267     if (ds_get_bits_per_pixel(ts->ds) != 32)
 268             return;
 269     page = ts->vram_offset;
 270     page24 = ts->vram24_offset;
 271     cpage = ts->cplane_offset;
 272     y_start = -1;
 273     page_min = 0xffffffff;
 274     page_max = 0;
 275     d = ds_get_data(ts->ds);
 276     s = ts->vram;
 277     s24 = ts->vram24;
 278     cptr = ts->cplane;
 279     dd = ds_get_linesize(ts->ds);
 280     ds = 1024;
 281
 282     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
 283             page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
 284         if (check_dirty(page, page24, cpage)) {
 285             if (y_start < 0)
 286                 y_start = y;
 287             if (page < page_min)
 288                 page_min = page;
 289             if (page > page_max)
 290                 page_max = page;
 291             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 292             d += dd;
 293             s += ds;
 294             cptr += ds;
 295             s24 += ds;
 296             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 297             d += dd;
 298             s += ds;
 299             cptr += ds;
 300             s24 += ds;
 301             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 302             d += dd;
 303             s += ds;
 304             cptr += ds;
 305             s24 += ds;
 306             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 307             d += dd;
 308             s += ds;
 309             cptr += ds;
 310             s24 += ds;
 311         } else {
 312             if (y_start >= 0) {
 313                 /* flush to display */
 314                 dpy_update(ts->ds, 0, y_start,
 315                            ts->width, y - y_start);
 316                 y_start = -1;
 317             }
 318             d += dd * 4;
 319             s += ds * 4;
 320             cptr += ds * 4;
 321             s24 += ds * 4;
 322         }
 323     }
 324     if (y_start >= 0) {
 325         /* flush to display */
 326         dpy_update(ts->ds, 0, y_start,
 327                    ts->width, y - y_start);
 328     }
 329     /* reset modified pages */
 330     if (page_min <= page_max) {
 331         reset_dirty(ts, page_min, page_max, page24, cpage);
 332     }
 333 }
 334
 335 static void tcx_invalidate_display(void *opaque)
 336 {
 337     TCXState *s = opaque;
 338     int i;
 339
 340     for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
 341         cpu_physical_memory_set_dirty(s->vram_offset + i);
 342     }
 343 }
 344
 345 static void tcx24_invalidate_display(void *opaque)
 346 {
 347     TCXState *s = opaque;
 348     int i;
 349
 350     tcx_invalidate_display(s);
 351     for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
 352         cpu_physical_memory_set_dirty(s->vram24_offset + i);
 353         cpu_physical_memory_set_dirty(s->cplane_offset + i);
 354     }
 355 }
 356
 357 static void tcx_save(QEMUFile *f, void *opaque)
 358 {
 359     TCXState *s = opaque;
 360
 361     qemu_put_be16s(f, &s->height);
 362     qemu_put_be16s(f, &s->width);
 363     qemu_put_be16s(f, &s->depth);
 364     qemu_put_buffer(f, s->r, 256);
 365     qemu_put_buffer(f, s->g, 256);
 366     qemu_put_buffer(f, s->b, 256);
 367     qemu_put_8s(f, &s->dac_index);
 368     qemu_put_8s(f, &s->dac_state);
 369 }
 370
 371 static int tcx_load(QEMUFile *f, void *opaque, int version_id)
 372 {
 373     TCXState *s = opaque;
 374     uint32_t dummy;
 375
 376     if (version_id != 3 && version_id != 4)
 377         return -EINVAL;
 378
 379     if (version_id == 3) {
 380         qemu_get_be32s(f, &dummy);
 381         qemu_get_be32s(f, &dummy);
 382         qemu_get_be32s(f, &dummy);
 383     }
 384     qemu_get_be16s(f, &s->height);
 385     qemu_get_be16s(f, &s->width);
 386     qemu_get_be16s(f, &s->depth);
 387     qemu_get_buffer(f, s->r, 256);
 388     qemu_get_buffer(f, s->g, 256);
 389     qemu_get_buffer(f, s->b, 256);
 390     qemu_get_8s(f, &s->dac_index);
 391     qemu_get_8s(f, &s->dac_state);
 392     update_palette_entries(s, 0, 256);
 393     if (s->depth == 24)
 394         tcx24_invalidate_display(s);
 395     else
 396         tcx_invalidate_display(s);
 397
 398     return 0;
 399 }
 400
 401 static void tcx_reset(void *opaque)
 402 {
 403     TCXState *s = opaque;
 404
 405     /* Initialize palette */
 406     memset(s->r, 0, 256);
 407     memset(s->g, 0, 256);
 408     memset(s->b, 0, 256);
 409     s->r[255] = s->g[255] = s->b[255] = 255;
 410     update_palette_entries(s, 0, 256);
 411     memset(s->vram, 0, MAXX*MAXY);
 412     cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
 413                                     MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
 414     s->dac_index = 0;
 415     s->dac_state = 0;
 416 }
 417
 418 static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
 419 {
 420     return 0;
 421 }
 422
 423 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 424 {
 425     TCXState *s = opaque;
 426
 427     switch (addr) {
 428     case 0:
 429         s->dac_index = val >> 24;
 430         s->dac_state = 0;
 431         break;
 432     case 4:
 433         switch (s->dac_state) {
 434         case 0:
 435             s->r[s->dac_index] = val >> 24;
 436             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 437             s->dac_state++;
 438             break;
 439         case 1:
 440             s->g[s->dac_index] = val >> 24;
 441             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 442             s->dac_state++;
 443             break;
 444         case 2:
 445             s->b[s->dac_index] = val >> 24;
 446             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 447             s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
 448         default:
 449             s->dac_state = 0;
 450             break;
 451         }
 452         break;
 453     default:
 454         break;
 455     }
 456     return;
 457 }
 458
 459 static CPUReadMemoryFunc *tcx_dac_read[3] = {
 460     NULL,
 461     NULL,
 462     tcx_dac_readl,
 463 };
 464
 465 static CPUWriteMemoryFunc *tcx_dac_write[3] = {
 466     NULL,
 467     NULL,
 468     tcx_dac_writel,
 469 };
 470
 471 static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
 472 {
 473     return 0;
 474 }
 475
 476 static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
 477                              uint32_t val)
 478 {
 479 }
 480
 481 static CPUReadMemoryFunc *tcx_dummy_read[3] = {
 482     NULL,
 483     NULL,
 484     tcx_dummy_readl,
 485 };
 486
 487 static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
 488     NULL,
 489     NULL,
 490     tcx_dummy_writel,
 491 };
 492
 493 void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
 494               unsigned long vram_offset, int vram_size, int width, int height,
 495               int depth)
 496 {
 497     TCXState *s;
 498     int io_memory, dummy_memory;
 499     int size;
 500
 501     s = qemu_mallocz(sizeof(TCXState));
 502     s->addr = addr;
 503     s->vram_offset = vram_offset;
 504     s->width = width;
 505     s->height = height;
 506     s->depth = depth;
 507
 508     // 8-bit plane
 509     s->vram = vram_base;
 510     size = vram_size;
 511     cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
 512     vram_offset += size;
 513     vram_base += size;
 514
 515     io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
 516     cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
 517                                  io_memory);
 518
 519     dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
 520                                           s);
 521     cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
 522                                  dummy_memory);
 523     if (depth == 24) {
 524         // 24-bit plane
 525         size = vram_size * 4;
 526         s->vram24 = (uint32_t *)vram_base;
 527         s->vram24_offset = vram_offset;
 528         cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
 529         vram_offset += size;
 530         vram_base += size;
 531
 532         // Control plane
 533         size = vram_size * 4;
 534         s->cplane = (uint32_t *)vram_base;
 535         s->cplane_offset = vram_offset;
 536         cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
 537         s->ds = graphic_console_init(tcx24_update_display,
 538                                      tcx24_invalidate_display,
 539                                      tcx24_screen_dump, NULL, s);
 540     } else {
 541         cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
 542                                      dummy_memory);
 543         s->ds = graphic_console_init(tcx_update_display,
 544                                      tcx_invalidate_display,
 545                                      tcx_screen_dump, NULL, s);
 546     }
 547     // NetBSD writes here even with 8-bit display
 548     cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
 549                                  dummy_memory);
 550
 551     register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
 552     qemu_register_reset(tcx_reset, s);
 553     tcx_reset(s);
 554     qemu_console_resize(s->ds, width, height);
 555 }
 556
 557 static void tcx_screen_dump(void *opaque, const char *filename)
 558 {
 559     TCXState *s = opaque;
 560     FILE *f;
 561     uint8_t *d, *d1, v;
 562     int y, x;
 563
 564     f = fopen(filename, "wb");
 565     if (!f)
 566         return;
 567     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 568     d1 = s->vram;
 569     for(y = 0; y < s->height; y++) {
 570         d = d1;
 571         for(x = 0; x < s->width; x++) {
 572             v = *d;
 573             fputc(s->r[v], f);
 574             fputc(s->g[v], f);
 575             fputc(s->b[v], f);
 576             d++;
 577         }
 578         d1 += MAXX;
 579     }
 580     fclose(f);
 581     return;
 582 }
 583
 584 static void tcx24_screen_dump(void *opaque, const char *filename)
 585 {
 586     TCXState *s = opaque;
 587     FILE *f;
 588     uint8_t *d, *d1, v;
 589     uint32_t *s24, *cptr, dval;
 590     int y, x;
 591
 592     f = fopen(filename, "wb");
 593     if (!f)
 594         return;
 595     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 596     d1 = s->vram;
 597     s24 = s->vram24;
 598     cptr = s->cplane;
 599     for(y = 0; y < s->height; y++) {
 600         d = d1;
 601         for(x = 0; x < s->width; x++, d++, s24++) {
 602             if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
 603                 dval = *s24 & 0x00ffffff;
 604                 fputc((dval >> 16) & 0xff, f);
 605                 fputc((dval >> 8) & 0xff, f);
 606                 fputc(dval & 0xff, f);
 607             } else {
 608                 v = *d;
 609                 fputc(s->r[v], f);
 610                 fputc(s->g[v], f);
 611                 fputc(s->b[v], f);
 612             }
 613         }
 614         d1 += MAXX;
 615     }
 616     fclose(f);
 617     return;
 618 }