git.maemo.org Git - qemu/blob - hw/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27 #include "pixel_ops.h"
  28
  29 #define MAXX 1024
  30 #define MAXY 768
  31 #define TCX_DAC_NREGS 16
  32 #define TCX_THC_NREGS_8  0x081c
  33 #define TCX_THC_NREGS_24 0x1000
  34 #define TCX_TEC_NREGS    0x1000
  35
  36 typedef struct TCXState {
  37     target_phys_addr_t addr;
  38     DisplayState *ds;
  39     QEMUConsole *console;
  40     uint8_t *vram;
  41     uint32_t *vram24, *cplane;
  42     ram_addr_t vram_offset, vram24_offset, cplane_offset;
  43     uint16_t width, height, depth;
  44     uint8_t r[256], g[256], b[256];
  45     uint32_t palette[256];
  46     uint8_t dac_index, dac_state;
  47 } TCXState;
  48
  49 static void tcx_screen_dump(void *opaque, const char *filename);
  50 static void tcx24_screen_dump(void *opaque, const char *filename);
  51 static void tcx_invalidate_display(void *opaque);
  52 static void tcx24_invalidate_display(void *opaque);
  53
  54 static void update_palette_entries(TCXState *s, int start, int end)
  55 {
  56     int i;
  57     for(i = start; i < end; i++) {
  58         switch(ds_get_bits_per_pixel(s->ds)) {
  59         default:
  60         case 8:
  61             s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
  62             break;
  63         case 15:
  64             s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
  65             break;
  66         case 16:
  67             s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
  68             break;
  69         case 32:
  70             s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
  71             break;
  72         }
  73     }
  74     if (s->depth == 24)
  75         tcx24_invalidate_display(s);
  76     else
  77         tcx_invalidate_display(s);
  78 }
  79
  80 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
  81                             const uint8_t *s, int width)
  82 {
  83     int x;
  84     uint8_t val;
  85     uint32_t *p = (uint32_t *)d;
  86
  87     for(x = 0; x < width; x++) {
  88         val = *s++;
  89         *p++ = s1->palette[val];
  90     }
  91 }
  92
  93 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
  94                             const uint8_t *s, int width)
  95 {
  96     int x;
  97     uint8_t val;
  98     uint16_t *p = (uint16_t *)d;
  99
 100     for(x = 0; x < width; x++) {
 101         val = *s++;
 102         *p++ = s1->palette[val];
 103     }
 104 }
 105
 106 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
 107                            const uint8_t *s, int width)
 108 {
 109     int x;
 110     uint8_t val;
 111
 112     for(x = 0; x < width; x++) {
 113         val = *s++;
 114         *d++ = s1->palette[val];
 115     }
 116 }
 117
 118 /*
 119   XXX Could be much more optimal:
 120   * detect if line/page/whole screen is in 24 bit mode
 121   * if destination is also BGR, use memcpy
 122   */
 123 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 124                                      const uint8_t *s, int width,
 125                                      const uint32_t *cplane,
 126                                      const uint32_t *s24)
 127 {
 128     int x, r, g, b;
 129     uint8_t val, *p8;
 130     uint32_t *p = (uint32_t *)d;
 131     uint32_t dval;
 132
 133     for(x = 0; x < width; x++, s++, s24++) {
 134         if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
 135             // 24-bit direct, BGR order
 136             p8 = (uint8_t *)s24;
 137             p8++;
 138             b = *p8++;
 139             g = *p8++;
 140             r = *p8++;
 141             dval = rgb_to_pixel32(r, g, b);
 142         } else {
 143             val = *s;
 144             dval = s1->palette[val];
 145         }
 146         *p++ = dval;
 147     }
 148 }
 149
 150 static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
 151                               ram_addr_t cpage)
 152 {
 153     int ret;
 154     unsigned int off;
 155
 156     ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
 157     for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
 158         ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
 159         ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
 160     }
 161     return ret;
 162 }
 163
 164 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
 165                                ram_addr_t page_max, ram_addr_t page24,
 166                               ram_addr_t cpage)
 167 {
 168     cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 169                                     VGA_DIRTY_FLAG);
 170     page_min -= ts->vram_offset;
 171     page_max -= ts->vram_offset;
 172     cpu_physical_memory_reset_dirty(page24 + page_min * 4,
 173                                     page24 + page_max * 4 + TARGET_PAGE_SIZE,
 174                                     VGA_DIRTY_FLAG);
 175     cpu_physical_memory_reset_dirty(cpage + page_min * 4,
 176                                     cpage + page_max * 4 + TARGET_PAGE_SIZE,
 177                                     VGA_DIRTY_FLAG);
 178 }
 179
 180 /* Fixed line length 1024 allows us to do nice tricks not possible on
 181    VGA... */
 182 static void tcx_update_display(void *opaque)
 183 {
 184     TCXState *ts = opaque;
 185     ram_addr_t page, page_min, page_max;
 186     int y, y_start, dd, ds;
 187     uint8_t *d, *s;
 188     void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
 189
 190     if (ds_get_bits_per_pixel(ts->ds) == 0)
 191         return;
 192     page = ts->vram_offset;
 193     y_start = -1;
 194     page_min = 0xffffffff;
 195     page_max = 0;
 196     d = ds_get_data(ts->ds);
 197     s = ts->vram;
 198     dd = ds_get_linesize(ts->ds);
 199     ds = 1024;
 200
 201     switch (ds_get_bits_per_pixel(ts->ds)) {
 202     case 32:
 203         f = tcx_draw_line32;
 204         break;
 205     case 15:
 206     case 16:
 207         f = tcx_draw_line16;
 208         break;
 209     default:
 210     case 8:
 211         f = tcx_draw_line8;
 212         break;
 213     case 0:
 214         return;
 215     }
 216
 217     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
 218         if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
 219             if (y_start < 0)
 220                 y_start = y;
 221             if (page < page_min)
 222                 page_min = page;
 223             if (page > page_max)
 224                 page_max = page;
 225             f(ts, d, s, ts->width);
 226             d += dd;
 227             s += ds;
 228             f(ts, d, s, ts->width);
 229             d += dd;
 230             s += ds;
 231             f(ts, d, s, ts->width);
 232             d += dd;
 233             s += ds;
 234             f(ts, d, s, ts->width);
 235             d += dd;
 236             s += ds;
 237         } else {
 238             if (y_start >= 0) {
 239                 /* flush to display */
 240                 dpy_update(ts->ds, 0, y_start,
 241                            ts->width, y - y_start);
 242                 y_start = -1;
 243             }
 244             d += dd * 4;
 245             s += ds * 4;
 246         }
 247     }
 248     if (y_start >= 0) {
 249         /* flush to display */
 250         dpy_update(ts->ds, 0, y_start,
 251                    ts->width, y - y_start);
 252     }
 253     /* reset modified pages */
 254     if (page_min <= page_max) {
 255         cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 256                                         VGA_DIRTY_FLAG);
 257     }
 258 }
 259
 260 static void tcx24_update_display(void *opaque)
 261 {
 262     TCXState *ts = opaque;
 263     ram_addr_t page, page_min, page_max, cpage, page24;
 264     int y, y_start, dd, ds;
 265     uint8_t *d, *s;
 266     uint32_t *cptr, *s24;
 267
 268     if (ds_get_bits_per_pixel(ts->ds) != 32)
 269             return;
 270     page = ts->vram_offset;
 271     page24 = ts->vram24_offset;
 272     cpage = ts->cplane_offset;
 273     y_start = -1;
 274     page_min = 0xffffffff;
 275     page_max = 0;
 276     d = ds_get_data(ts->ds);
 277     s = ts->vram;
 278     s24 = ts->vram24;
 279     cptr = ts->cplane;
 280     dd = ds_get_linesize(ts->ds);
 281     ds = 1024;
 282
 283     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
 284             page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
 285         if (check_dirty(page, page24, cpage)) {
 286             if (y_start < 0)
 287                 y_start = y;
 288             if (page < page_min)
 289                 page_min = page;
 290             if (page > page_max)
 291                 page_max = page;
 292             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 293             d += dd;
 294             s += ds;
 295             cptr += ds;
 296             s24 += ds;
 297             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 298             d += dd;
 299             s += ds;
 300             cptr += ds;
 301             s24 += ds;
 302             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 303             d += dd;
 304             s += ds;
 305             cptr += ds;
 306             s24 += ds;
 307             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 308             d += dd;
 309             s += ds;
 310             cptr += ds;
 311             s24 += ds;
 312         } else {
 313             if (y_start >= 0) {
 314                 /* flush to display */
 315                 dpy_update(ts->ds, 0, y_start,
 316                            ts->width, y - y_start);
 317                 y_start = -1;
 318             }
 319             d += dd * 4;
 320             s += ds * 4;
 321             cptr += ds * 4;
 322             s24 += ds * 4;
 323         }
 324     }
 325     if (y_start >= 0) {
 326         /* flush to display */
 327         dpy_update(ts->ds, 0, y_start,
 328                    ts->width, y - y_start);
 329     }
 330     /* reset modified pages */
 331     if (page_min <= page_max) {
 332         reset_dirty(ts, page_min, page_max, page24, cpage);
 333     }
 334 }
 335
 336 static void tcx_invalidate_display(void *opaque)
 337 {
 338     TCXState *s = opaque;
 339     int i;
 340
 341     for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
 342         cpu_physical_memory_set_dirty(s->vram_offset + i);
 343     }
 344 }
 345
 346 static void tcx24_invalidate_display(void *opaque)
 347 {
 348     TCXState *s = opaque;
 349     int i;
 350
 351     tcx_invalidate_display(s);
 352     for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
 353         cpu_physical_memory_set_dirty(s->vram24_offset + i);
 354         cpu_physical_memory_set_dirty(s->cplane_offset + i);
 355     }
 356 }
 357
 358 static void tcx_save(QEMUFile *f, void *opaque)
 359 {
 360     TCXState *s = opaque;
 361
 362     qemu_put_be16s(f, &s->height);
 363     qemu_put_be16s(f, &s->width);
 364     qemu_put_be16s(f, &s->depth);
 365     qemu_put_buffer(f, s->r, 256);
 366     qemu_put_buffer(f, s->g, 256);
 367     qemu_put_buffer(f, s->b, 256);
 368     qemu_put_8s(f, &s->dac_index);
 369     qemu_put_8s(f, &s->dac_state);
 370 }
 371
 372 static int tcx_load(QEMUFile *f, void *opaque, int version_id)
 373 {
 374     TCXState *s = opaque;
 375     uint32_t dummy;
 376
 377     if (version_id != 3 && version_id != 4)
 378         return -EINVAL;
 379
 380     if (version_id == 3) {
 381         qemu_get_be32s(f, &dummy);
 382         qemu_get_be32s(f, &dummy);
 383         qemu_get_be32s(f, &dummy);
 384     }
 385     qemu_get_be16s(f, &s->height);
 386     qemu_get_be16s(f, &s->width);
 387     qemu_get_be16s(f, &s->depth);
 388     qemu_get_buffer(f, s->r, 256);
 389     qemu_get_buffer(f, s->g, 256);
 390     qemu_get_buffer(f, s->b, 256);
 391     qemu_get_8s(f, &s->dac_index);
 392     qemu_get_8s(f, &s->dac_state);
 393     update_palette_entries(s, 0, 256);
 394     if (s->depth == 24)
 395         tcx24_invalidate_display(s);
 396     else
 397         tcx_invalidate_display(s);
 398
 399     return 0;
 400 }
 401
 402 static void tcx_reset(void *opaque)
 403 {
 404     TCXState *s = opaque;
 405
 406     /* Initialize palette */
 407     memset(s->r, 0, 256);
 408     memset(s->g, 0, 256);
 409     memset(s->b, 0, 256);
 410     s->r[255] = s->g[255] = s->b[255] = 255;
 411     update_palette_entries(s, 0, 256);
 412     memset(s->vram, 0, MAXX*MAXY);
 413     cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
 414                                     MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
 415     s->dac_index = 0;
 416     s->dac_state = 0;
 417 }
 418
 419 static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
 420 {
 421     return 0;
 422 }
 423
 424 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 425 {
 426     TCXState *s = opaque;
 427
 428     switch (addr) {
 429     case 0:
 430         s->dac_index = val >> 24;
 431         s->dac_state = 0;
 432         break;
 433     case 4:
 434         switch (s->dac_state) {
 435         case 0:
 436             s->r[s->dac_index] = val >> 24;
 437             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 438             s->dac_state++;
 439             break;
 440         case 1:
 441             s->g[s->dac_index] = val >> 24;
 442             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 443             s->dac_state++;
 444             break;
 445         case 2:
 446             s->b[s->dac_index] = val >> 24;
 447             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 448             s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
 449         default:
 450             s->dac_state = 0;
 451             break;
 452         }
 453         break;
 454     default:
 455         break;
 456     }
 457     return;
 458 }
 459
 460 static CPUReadMemoryFunc *tcx_dac_read[3] = {
 461     NULL,
 462     NULL,
 463     tcx_dac_readl,
 464 };
 465
 466 static CPUWriteMemoryFunc *tcx_dac_write[3] = {
 467     NULL,
 468     NULL,
 469     tcx_dac_writel,
 470 };
 471
 472 static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
 473 {
 474     return 0;
 475 }
 476
 477 static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
 478                              uint32_t val)
 479 {
 480 }
 481
 482 static CPUReadMemoryFunc *tcx_dummy_read[3] = {
 483     NULL,
 484     NULL,
 485     tcx_dummy_readl,
 486 };
 487
 488 static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
 489     NULL,
 490     NULL,
 491     tcx_dummy_writel,
 492 };
 493
 494 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
 495               unsigned long vram_offset, int vram_size, int width, int height,
 496               int depth)
 497 {
 498     TCXState *s;
 499     int io_memory, dummy_memory;
 500     int size;
 501
 502     s = qemu_mallocz(sizeof(TCXState));
 503     if (!s)
 504         return;
 505     s->ds = ds;
 506     s->addr = addr;
 507     s->vram_offset = vram_offset;
 508     s->width = width;
 509     s->height = height;
 510     s->depth = depth;
 511
 512     // 8-bit plane
 513     s->vram = vram_base;
 514     size = vram_size;
 515     cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
 516     vram_offset += size;
 517     vram_base += size;
 518
 519     io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
 520     cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
 521                                  io_memory);
 522
 523     dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
 524                                           s);
 525     cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
 526                                  dummy_memory);
 527     if (depth == 24) {
 528         // 24-bit plane
 529         size = vram_size * 4;
 530         s->vram24 = (uint32_t *)vram_base;
 531         s->vram24_offset = vram_offset;
 532         cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
 533         vram_offset += size;
 534         vram_base += size;
 535
 536         // Control plane
 537         size = vram_size * 4;
 538         s->cplane = (uint32_t *)vram_base;
 539         s->cplane_offset = vram_offset;
 540         cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
 541         s->console = graphic_console_init(s->ds, tcx24_update_display,
 542                                           tcx24_invalidate_display,
 543                                           tcx24_screen_dump, NULL, s);
 544     } else {
 545         cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
 546                                      dummy_memory);
 547         s->console = graphic_console_init(s->ds, tcx_update_display,
 548                                           tcx_invalidate_display,
 549                                           tcx_screen_dump, NULL, s);
 550     }
 551     // NetBSD writes here even with 8-bit display
 552     cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
 553                                  dummy_memory);
 554
 555     register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
 556     qemu_register_reset(tcx_reset, s);
 557     tcx_reset(s);
 558     qemu_console_resize(s->console, width, height);
 559 }
 560
 561 static void tcx_screen_dump(void *opaque, const char *filename)
 562 {
 563     TCXState *s = opaque;
 564     FILE *f;
 565     uint8_t *d, *d1, v;
 566     int y, x;
 567
 568     f = fopen(filename, "wb");
 569     if (!f)
 570         return;
 571     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 572     d1 = s->vram;
 573     for(y = 0; y < s->height; y++) {
 574         d = d1;
 575         for(x = 0; x < s->width; x++) {
 576             v = *d;
 577             fputc(s->r[v], f);
 578             fputc(s->g[v], f);
 579             fputc(s->b[v], f);
 580             d++;
 581         }
 582         d1 += MAXX;
 583     }
 584     fclose(f);
 585     return;
 586 }
 587
 588 static void tcx24_screen_dump(void *opaque, const char *filename)
 589 {
 590     TCXState *s = opaque;
 591     FILE *f;
 592     uint8_t *d, *d1, v;
 593     uint32_t *s24, *cptr, dval;
 594     int y, x;
 595
 596     f = fopen(filename, "wb");
 597     if (!f)
 598         return;
 599     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 600     d1 = s->vram;
 601     s24 = s->vram24;
 602     cptr = s->cplane;
 603     for(y = 0; y < s->height; y++) {
 604         d = d1;
 605         for(x = 0; x < s->width; x++, d++, s24++) {
 606             if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
 607                 dval = *s24 & 0x00ffffff;
 608                 fputc((dval >> 16) & 0xff, f);
 609                 fputc((dval >> 8) & 0xff, f);
 610                 fputc(dval & 0xff, f);
 611             } else {
 612                 v = *d;
 613                 fputc(s->r[v], f);
 614                 fputc(s->g[v], f);
 615                 fputc(s->b[v], f);
 616             }
 617         }
 618         d1 += MAXX;
 619     }
 620     fclose(f);
 621     return;
 622 }