2 * Texas Instruments TUSB6010 emulation.
3 * Based on reverse-engineering of a linux driver.
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "qemu-common.h"
23 #include "qemu-timer.h"
29 #define OMAP3_HSUSB_DEBUG
31 #ifdef OMAP3_HSUSB_DEBUG
32 #define TRACE(fmt,...) fprintf(stderr, "%s: " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
66 uint32_t rx_config[15];
67 uint32_t tx_config[15];
70 uint32_t control_config;
71 uint32_t otg_timer_val;
74 #define TUSB_DEVCLOCK 60000000 /* 60 MHz */
76 #define TUSB_VLYNQ_CTRL 0x004
78 /* Mentor Graphics OTG core registers. */
79 #define TUSB_BASE_OFFSET 0x400
81 /* FIFO registers, 32-bit. */
82 #define TUSB_FIFO_BASE 0x600
84 /* Device System & Control registers, 32-bit. */
85 #define TUSB_SYS_REG_BASE 0x800
87 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
88 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
89 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
90 #define TUSB_DEV_CONF_SOFT_ID (1 << 1)
91 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
93 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
94 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
95 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
96 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23)
97 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
98 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
99 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
100 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
101 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
102 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
103 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
104 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
105 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
106 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
107 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
108 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
109 #define TUSB_PHY_OTG_CTRL_PD (1 << 6)
110 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
111 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
112 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
113 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
114 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
115 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
117 /* OTG status register */
118 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
119 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
120 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
121 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
122 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
123 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
124 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
125 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
126 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
127 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
128 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
130 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
131 #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
132 #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
133 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
135 /* PRCM configuration register */
136 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
137 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
138 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
140 /* PRCM management register */
141 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
142 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25)
143 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
144 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
145 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
146 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
147 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
148 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
149 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
150 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
151 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
152 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
153 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
154 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
155 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
157 /* Wake-up source clear and mask registers */
158 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
159 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
160 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
161 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
162 #define TUSB_PRCM_WGPIO_7 (1 << 12)
163 #define TUSB_PRCM_WGPIO_6 (1 << 11)
164 #define TUSB_PRCM_WGPIO_5 (1 << 10)
165 #define TUSB_PRCM_WGPIO_4 (1 << 9)
166 #define TUSB_PRCM_WGPIO_3 (1 << 8)
167 #define TUSB_PRCM_WGPIO_2 (1 << 7)
168 #define TUSB_PRCM_WGPIO_1 (1 << 6)
169 #define TUSB_PRCM_WGPIO_0 (1 << 5)
170 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
171 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
172 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
173 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
174 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
176 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
177 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
178 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
179 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
180 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
181 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
182 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
183 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
184 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
185 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
186 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
187 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
188 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
189 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
190 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
191 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
193 /* NOR flash interrupt source registers */
194 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
195 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
196 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
197 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
198 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
199 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
200 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
201 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
202 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
203 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
204 #define TUSB_INT_SRC_DEV_READY (1 << 12)
205 #define TUSB_INT_SRC_USB_IP_TX (1 << 9)
206 #define TUSB_INT_SRC_USB_IP_RX (1 << 8)
207 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
208 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
209 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
210 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
211 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
212 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
213 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
214 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
216 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
217 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
218 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
219 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
220 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
221 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c)
222 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
223 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c)
224 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188)
225 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
226 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
227 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
229 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
230 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
232 /* Device System & Control register bitfields */
233 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
234 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
235 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
236 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
237 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
238 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20)
239 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
240 #define TUSB_EP0_CONFIG_SW_EN (1 << 8)
241 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
242 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
243 #define TUSB_EP_CONFIG_SW_EN (1 << 31)
244 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
245 #define TUSB_PROD_TEST_RESET_VAL 0xa596
247 int tusb6010_sync_io(TUSBState *s)
249 return s->iomemtype[0];
252 int tusb6010_async_io(TUSBState *s)
254 return s->iomemtype[1];
257 static void tusb_intr_update(TUSBState *s)
259 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
260 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
262 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
265 static void tusb_usbip_intr_update(TUSBState *s)
267 /* TX interrupt in the MUSB */
268 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
269 s->intr |= TUSB_INT_SRC_USB_IP_TX;
271 s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
273 /* RX interrupt in the MUSB */
274 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
275 s->intr |= TUSB_INT_SRC_USB_IP_RX;
277 s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
279 /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
284 static void tusb_dma_intr_update(TUSBState *s)
286 if (s->dma_intr & ~s->dma_mask)
287 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
289 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
294 static void tusb_gpio_intr_update(TUSBState *s)
296 /* TODO: How is this signalled? */
299 extern CPUReadMemoryFunc *musb_read[];
300 extern CPUWriteMemoryFunc *musb_write[];
302 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
304 TUSBState *s = (TUSBState *) opaque;
306 switch (addr & 0xfff) {
307 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
308 return musb_read[0](s->musb, addr & 0x1ff);
310 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
311 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
314 printf("%s: unknown register at %03x\n",
315 __FUNCTION__, (int) (addr & 0xfff));
319 static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
321 TUSBState *s = (TUSBState *) opaque;
323 switch (addr & 0xfff) {
324 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
325 return musb_read[1](s->musb, addr & 0x1ff);
327 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
328 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
331 printf("%s: unknown register at %03x\n",
332 __FUNCTION__, (int) (addr & 0xfff));
336 static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
338 TUSBState *s = (TUSBState *) opaque;
339 int offset = addr & 0xfff;
345 return s->dev_config;
347 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
348 return musb_read[2](s->musb, offset & 0x1ff);
350 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
351 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
353 case TUSB_PHY_OTG_CTRL_ENABLE:
354 case TUSB_PHY_OTG_CTRL:
355 return 0x00; /* TODO */
357 case TUSB_DEV_OTG_STAT:
360 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
361 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
364 case TUSB_DEV_OTG_TIMER:
365 return s->otg_timer_val;
370 return s->prcm_config;
371 case TUSB_PRCM_MNGMT:
372 return s->prcm_mngmt;
373 case TUSB_PRCM_WAKEUP_SOURCE:
374 case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */
376 case TUSB_PRCM_WAKEUP_MASK:
379 case TUSB_PULLUP_1_CTRL:
381 case TUSB_PULLUP_2_CTRL:
384 case TUSB_INT_CTRL_REV:
386 case TUSB_INT_CTRL_CONF:
387 return s->control_config;
389 case TUSB_USBIP_INT_SRC:
390 case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */
391 case TUSB_USBIP_INT_CLEAR:
392 return s->usbip_intr;
393 case TUSB_USBIP_INT_MASK:
394 return s->usbip_mask;
396 case TUSB_DMA_INT_SRC:
397 case TUSB_DMA_INT_SET: /* TODO: What do these two return? */
398 case TUSB_DMA_INT_CLEAR:
400 case TUSB_DMA_INT_MASK:
403 case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */
404 case TUSB_GPIO_INT_SET:
405 case TUSB_GPIO_INT_CLEAR:
407 case TUSB_GPIO_INT_MASK:
411 case TUSB_INT_SRC_SET: /* TODO: What do these two return? */
412 case TUSB_INT_SRC_CLEAR:
420 return s->gpio_config;
422 case TUSB_DMA_CTRL_REV:
424 case TUSB_DMA_REQ_CONF:
425 return s->dma_config;
427 return s->ep0_config;
428 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
429 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
430 return s->tx_config[epnum];
431 case TUSB_DMA_EP_MAP:
433 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
434 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
435 return s->rx_config[epnum];
436 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
437 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
438 epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
439 return 0x00000000; /* TODO */
440 case TUSB_WAIT_COUNT:
441 return 0x00; /* TODO */
443 case TUSB_SCRATCH_PAD:
446 case TUSB_PROD_TEST_RESET:
447 return s->test_reset;
456 printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
460 static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
463 TUSBState *s = (TUSBState *) opaque;
465 switch (addr & 0xfff) {
466 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
467 musb_write[0](s->musb, addr & 0x1ff, value);
470 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
471 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
475 printf("%s: unknown register at %03x\n",
476 __FUNCTION__, (int) (addr & 0xfff));
481 static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
484 TUSBState *s = (TUSBState *) opaque;
486 switch (addr & 0xfff) {
487 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
488 musb_write[1](s->musb, addr & 0x1ff, value);
491 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
492 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
496 printf("%s: unknown register at %03x\n",
497 __FUNCTION__, (int) (addr & 0xfff));
502 static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
505 TUSBState *s = (TUSBState *) opaque;
506 int offset = addr & 0xfff;
510 case TUSB_VLYNQ_CTRL:
513 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
514 musb_write[2](s->musb, offset & 0x1ff, value);
517 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
518 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
522 s->dev_config = value;
523 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
524 if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
525 hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
528 case TUSB_PHY_OTG_CTRL_ENABLE:
529 case TUSB_PHY_OTG_CTRL:
531 case TUSB_DEV_OTG_TIMER:
532 s->otg_timer_val = value;
533 if (value & TUSB_DEV_OTG_TIMER_ENABLE)
534 qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) +
535 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
536 ticks_per_sec, TUSB_DEVCLOCK));
538 qemu_del_timer(s->otg_timer);
542 s->prcm_config = value;
544 case TUSB_PRCM_MNGMT:
545 s->prcm_mngmt = value;
547 case TUSB_PRCM_WAKEUP_CLEAR:
549 case TUSB_PRCM_WAKEUP_MASK:
550 s->wkup_mask = value;
553 case TUSB_PULLUP_1_CTRL:
554 s->pullup[0] = value;
556 case TUSB_PULLUP_2_CTRL:
557 s->pullup[1] = value;
559 case TUSB_INT_CTRL_CONF:
560 s->control_config = value;
564 case TUSB_USBIP_INT_SET:
565 s->usbip_intr |= value;
566 tusb_usbip_intr_update(s);
568 case TUSB_USBIP_INT_CLEAR:
569 s->usbip_intr &= ~value;
570 tusb_usbip_intr_update(s);
571 musb_core_intr_clear(s->musb, ~value);
573 case TUSB_USBIP_INT_MASK:
574 s->usbip_mask = value;
575 tusb_usbip_intr_update(s);
578 case TUSB_DMA_INT_SET:
579 s->dma_intr |= value;
580 tusb_dma_intr_update(s);
582 case TUSB_DMA_INT_CLEAR:
583 s->dma_intr &= ~value;
584 tusb_dma_intr_update(s);
586 case TUSB_DMA_INT_MASK:
588 tusb_dma_intr_update(s);
591 case TUSB_GPIO_INT_SET:
592 s->gpio_intr |= value;
593 tusb_gpio_intr_update(s);
595 case TUSB_GPIO_INT_CLEAR:
596 s->gpio_intr &= ~value;
597 tusb_gpio_intr_update(s);
599 case TUSB_GPIO_INT_MASK:
600 s->gpio_mask = value;
601 tusb_gpio_intr_update(s);
604 case TUSB_INT_SRC_SET:
608 case TUSB_INT_SRC_CLEAR:
618 s->gpio_config = value;
620 case TUSB_DMA_REQ_CONF:
621 s->dma_config = value;
624 s->ep0_config = value & 0x1ff;
625 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
626 value & TUSB_EP0_CONFIG_DIR_TX);
628 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
629 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
630 s->tx_config[epnum] = value;
631 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
633 case TUSB_DMA_EP_MAP:
636 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
637 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
638 s->rx_config[epnum] = value;
639 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
641 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
642 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
643 epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
645 case TUSB_WAIT_COUNT:
648 case TUSB_SCRATCH_PAD:
652 case TUSB_PROD_TEST_RESET:
653 s->test_reset = value;
657 printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
662 static CPUReadMemoryFunc *tusb_async_readfn[] = {
668 static CPUWriteMemoryFunc *tusb_async_writefn[] = {
674 static void tusb_otg_tick(void *opaque)
676 TUSBState *s = (TUSBState *) opaque;
678 s->otg_timer_val = 0;
679 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
683 static void tusb_power_tick(void *opaque)
685 TUSBState *s = (TUSBState *) opaque;
693 static void tusb_musb_core_intr(void *opaque, int source, int level)
695 TUSBState *s = (TUSBState *) opaque;
696 uint16_t otg_status = s->otg_status;
697 TRACE("intr 0x%08x, 0x%08x, 0x%08x", source, level, musb_core_intr_get(s->musb));
701 TRACE("dealing with VBUS");
703 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
705 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
707 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
708 /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
709 if (s->otg_status != otg_status) {
710 s->otg_status = otg_status;
711 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
716 case musb_set_session:
717 TRACE("dealing with SESSION");
718 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
719 /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
721 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
722 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
724 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
725 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
728 /* XXX: some IRQ or anything? */
734 s->usbip_intr = musb_core_intr_get(s->musb);
738 s->intr |= 1 << source;
740 s->intr &= ~(1 << source);
746 TUSBState *tusb6010_init(qemu_irq intr)
748 TUSBState *s = qemu_mallocz(sizeof(*s));
750 s->test_reset = TUSB_PROD_TEST_RESET_VAL;
753 s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
755 s->mask = 0xffffffff;
756 s->intr = 0x00000000;
757 s->otg_timer_val = 0;
758 s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn,
759 tusb_async_writefn, s);
761 s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s);
762 s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s);
763 s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s,
769 void tusb6010_power(TUSBState *s, int on)
773 else if (!s->power && on) {
776 /* Pull the interrupt down after TUSB6010 comes up. */
779 qemu_mod_timer(s->pwr_timer,
780 qemu_get_clock(vm_clock) + ticks_per_sec / 2);