2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
12 #include "primecell.h"
19 /* Primary interrupt controller. */
21 typedef struct vpb_sic_state
31 static void vpb_sic_update(vpb_sic_state *s)
35 flags = s->level & s->mask;
36 qemu_set_irq(s->parent[s->irq], flags != 0);
39 static void vpb_sic_update_pic(vpb_sic_state *s)
44 for (i = 21; i <= 30; i++) {
46 if (!(s->pic_enable & mask))
48 qemu_set_irq(s->parent[i], (s->level & mask) != 0);
52 static void vpb_sic_set_irq(void *opaque, int irq, int level)
54 vpb_sic_state *s = (vpb_sic_state *)opaque;
56 s->level |= 1u << irq;
58 s->level &= ~(1u << irq);
59 if (s->pic_enable & (1u << irq))
60 qemu_set_irq(s->parent[irq], level);
64 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
66 vpb_sic_state *s = (vpb_sic_state *)opaque;
69 switch (offset >> 2) {
71 return s->level & s->mask;
78 case 8: /* PICENABLE */
81 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
86 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
89 vpb_sic_state *s = (vpb_sic_state *)opaque;
92 switch (offset >> 2) {
99 case 4: /* SOFTINTSET */
103 case 5: /* SOFTINTCLR */
107 case 8: /* PICENSET */
108 s->pic_enable |= (value & 0x7fe00000);
109 vpb_sic_update_pic(s);
111 case 9: /* PICENCLR */
112 s->pic_enable &= ~value;
113 vpb_sic_update_pic(s);
116 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
122 static CPUReadMemoryFunc *vpb_sic_readfn[] = {
128 static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
134 static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
140 s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
143 qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
147 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
149 cpu_register_physical_memory(base, 0x00001000, iomemtype);
150 /* ??? Save/restore. */
156 /* The AB and PB boards both use the same core, just with different
157 peripherans and expansion busses. For now we emulate a subset of the
158 PB peripherals and just change the board ID. */
160 static void versatile_init(int ram_size, int vga_ram_size,
161 const char *boot_device, DisplayState *ds,
162 const char *kernel_filename, const char *kernel_cmdline,
163 const char *initrd_filename, const char *cpu_model,
176 cpu_model = "arm926";
177 env = cpu_init(cpu_model);
179 fprintf(stderr, "Unable to find CPU definition\n");
182 /* ??? RAM shoud repeat to fill physical memory space. */
183 /* SDRAM at address zero. */
184 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
186 arm_sysctl_init(0x10000000, 0x41007004);
187 pic = arm_pic_init_cpu(env);
188 pic = pl190_init(0x10140000, pic[0], pic[1]);
189 sic = vpb_sic_init(0x10003000, pic, 31);
190 pl050_init(0x10006000, sic[3], 0);
191 pl050_init(0x10007000, sic[4], 1);
193 pci_bus = pci_vpb_init(sic, 27, 0);
194 /* The Versatile PCI bridge does not provide access to PCI IO space,
195 so many of the qemu PCI devices are not useable. */
196 for(n = 0; n < nb_nics; n++) {
199 nd->model = done_smc ? "rtl8139" : "smc91c111";
200 if (strcmp(nd->model, "smc91c111") == 0) {
201 smc91c111_init(nd, 0x10010000, sic[25]);
203 pci_nic_init(pci_bus, nd, -1);
207 usb_ohci_init_pci(pci_bus, 3, -1);
209 scsi_hba = lsi_scsi_init(pci_bus, -1);
210 for (n = 0; n < MAX_DISKS; n++) {
212 lsi_scsi_attach(scsi_hba, bs_table[n], n);
216 pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM);
217 pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM);
218 pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM);
219 pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM);
221 pl080_init(0x10130000, pic[17], 8);
222 sp804_init(0x101e2000, pic[4]);
223 sp804_init(0x101e3000, pic[5]);
225 /* The versatile/PB actually has a modified Color LCD controller
226 that includes hardware cursor support from the PL111. */
227 pl110_init(ds, 0x10120000, pic[16], 1);
229 pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
231 /* Disabled because there's no way of specifying a block device. */
232 pl181_init(0x1000b000, NULL, sic, 23, 2);
235 /* Add PL031 Real Time Clock. */
236 pl031_init(0x101e8000,pic[10]);
238 /* Memory map for Versatile/PB: */
239 /* 0x10000000 System registers. */
240 /* 0x10001000 PCI controller config registers. */
241 /* 0x10002000 Serial bus interface. */
242 /* 0x10003000 Secondary interrupt controller. */
243 /* 0x10004000 AACI (audio). */
244 /* 0x10005000 MMCI0. */
245 /* 0x10006000 KMI0 (keyboard). */
246 /* 0x10007000 KMI1 (mouse). */
247 /* 0x10008000 Character LCD Interface. */
248 /* 0x10009000 UART3. */
249 /* 0x1000a000 Smart card 1. */
250 /* 0x1000b000 MMCI1. */
251 /* 0x10010000 Ethernet. */
252 /* 0x10020000 USB. */
253 /* 0x10100000 SSMC. */
254 /* 0x10110000 MPMC. */
255 /* 0x10120000 CLCD Controller. */
256 /* 0x10130000 DMA Controller. */
257 /* 0x10140000 Vectored interrupt controller. */
258 /* 0x101d0000 AHB Monitor Interface. */
259 /* 0x101e0000 System Controller. */
260 /* 0x101e1000 Watchdog Interface. */
261 /* 0x101e2000 Timer 0/1. */
262 /* 0x101e3000 Timer 2/3. */
263 /* 0x101e4000 GPIO port 0. */
264 /* 0x101e5000 GPIO port 1. */
265 /* 0x101e6000 GPIO port 2. */
266 /* 0x101e7000 GPIO port 3. */
267 /* 0x101e8000 RTC. */
268 /* 0x101f0000 Smart card 0. */
269 /* 0x101f1000 UART0. */
270 /* 0x101f2000 UART1. */
271 /* 0x101f3000 UART2. */
272 /* 0x101f4000 SSPI. */
274 arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
275 initrd_filename, board_id, 0x0);
278 static void vpb_init(int ram_size, int vga_ram_size,
279 const char *boot_device, DisplayState *ds,
280 const char *kernel_filename, const char *kernel_cmdline,
281 const char *initrd_filename, const char *cpu_model)
283 versatile_init(ram_size, vga_ram_size,
285 kernel_filename, kernel_cmdline,
286 initrd_filename, cpu_model, 0x183);
289 static void vab_init(int ram_size, int vga_ram_size,
290 const char *boot_device, DisplayState *ds,
291 const char *kernel_filename, const char *kernel_cmdline,
292 const char *initrd_filename, const char *cpu_model)
294 versatile_init(ram_size, vga_ram_size,
296 kernel_filename, kernel_cmdline,
297 initrd_filename, cpu_model, 0x25e);
300 QEMUMachine versatilepb_machine = {
302 "ARM Versatile/PB (ARM926EJ-S)",
306 QEMUMachine versatileab_machine = {
308 "ARM Versatile/AB (ARM926EJ-S)",