4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
33 //#define DEBUG_VGA_MEM
34 //#define DEBUG_VGA_REG
36 //#define DEBUG_BOCHS_VBE
38 /* force some bits to zero */
39 const uint8_t sr_mask[8] = {
50 const uint8_t gr_mask[16] = {
51 (uint8_t)~0xf0, /* 0x00 */
52 (uint8_t)~0xf0, /* 0x01 */
53 (uint8_t)~0xf0, /* 0x02 */
54 (uint8_t)~0xe0, /* 0x03 */
55 (uint8_t)~0xfc, /* 0x04 */
56 (uint8_t)~0x84, /* 0x05 */
57 (uint8_t)~0xf0, /* 0x06 */
58 (uint8_t)~0xf0, /* 0x07 */
59 (uint8_t)~0x00, /* 0x08 */
60 (uint8_t)~0xff, /* 0x09 */
61 (uint8_t)~0xff, /* 0x0a */
62 (uint8_t)~0xff, /* 0x0b */
63 (uint8_t)~0xff, /* 0x0c */
64 (uint8_t)~0xff, /* 0x0d */
65 (uint8_t)~0xff, /* 0x0e */
66 (uint8_t)~0xff, /* 0x0f */
69 #define cbswap_32(__x) \
71 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
72 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
73 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
74 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
76 #ifdef WORDS_BIGENDIAN
77 #define PAT(x) cbswap_32(x)
82 #ifdef WORDS_BIGENDIAN
88 #ifdef WORDS_BIGENDIAN
89 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
91 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 static const uint32_t mask16[16] = {
115 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) cbswap_32(x)
121 static const uint32_t dmask16[16] = {
140 static const uint32_t dmask4[4] = {
147 static uint32_t expand4[256];
148 static uint16_t expand2[256];
149 static uint8_t expand4to8[16];
151 static void vga_screen_dump(void *opaque, const char *filename);
153 static void vga_dumb_update_retrace_info(VGAState *s)
158 static void vga_precise_update_retrace_info(VGAState *s)
161 int hretr_start_char;
162 int hretr_skew_chars;
166 int vretr_start_line;
169 int div2, sldiv2, dots;
172 const int hz[] = {25175000, 28322000, 25175000, 25175000};
173 int64_t chars_per_sec;
174 struct vga_precise_retrace *r = &s->retrace_info.precise;
176 htotal_chars = s->cr[0x00] + 5;
177 hretr_start_char = s->cr[0x04];
178 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
179 hretr_end_char = s->cr[0x05] & 0x1f;
181 vtotal_lines = (s->cr[0x06]
182 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
184 vretr_start_line = s->cr[0x10]
185 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
187 vretr_end_line = s->cr[0x11] & 0xf;
190 div2 = (s->cr[0x17] >> 2) & 1;
191 sldiv2 = (s->cr[0x17] >> 3) & 1;
193 clocking_mode = (s->sr[0x01] >> 3) & 1;
194 clock_sel = (s->msr >> 2) & 3;
195 dots = (s->msr & 1) ? 9 : 8;
197 chars_per_sec = hz[clock_sel] / dots;
199 htotal_chars <<= clocking_mode;
201 r->total_chars = vtotal_lines * htotal_chars;
202 r->total_chars = (vretr_start_line + vretr_end_line + 1) * htotal_chars;
204 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 r->ticks_per_char = ticks_per_sec / chars_per_sec;
209 r->vstart = vretr_start_line;
210 r->vend = r->vstart + vretr_end_line + 1;
212 r->hstart = hretr_start_char + hretr_skew_chars;
213 r->hend = r->hstart + hretr_end_char + 1;
214 r->htotal = htotal_chars;
217 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars));
218 #if 0 /* def DEBUG_RETRACE */
220 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars));
229 "div2 = %d sldiv2 = %d\n"
230 "clocking_mode = %d\n"
231 "clock_sel = %d %d\n"
233 "ticks/char = %lld\n"
252 static uint8_t vga_precise_retrace(VGAState *s)
254 struct vga_precise_retrace *r = &s->retrace_info.precise;
255 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
257 if (r->total_chars) {
258 int cur_line, cur_line_char, cur_char;
261 cur_tick = qemu_get_clock(vm_clock);
263 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
264 cur_line = cur_char / r->htotal;
266 if (cur_line >= r->vstart && cur_line <= r->vend) {
267 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
270 cur_line_char = cur_char % r->htotal;
271 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
272 val |= ST01_DISP_ENABLE;
277 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
281 static uint8_t vga_dumb_retrace(VGAState *s)
283 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
286 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
288 VGAState *s = opaque;
291 /* check port range access depending on color/monochrome mode */
292 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
293 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
298 if (s->ar_flip_flop == 0) {
305 index = s->ar_index & 0x1f;
318 val = s->sr[s->sr_index];
320 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
327 val = s->dac_write_index;
330 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
331 if (++s->dac_sub_index == 3) {
332 s->dac_sub_index = 0;
346 val = s->gr[s->gr_index];
348 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
357 val = s->cr[s->cr_index];
359 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
364 /* just toggle to fool polling */
365 val = s->st01 = s->retrace(s);
373 #if defined(DEBUG_VGA)
374 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
379 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
381 VGAState *s = opaque;
384 /* check port range access depending on color/monochrome mode */
385 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
386 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
390 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
395 if (s->ar_flip_flop == 0) {
399 index = s->ar_index & 0x1f;
402 s->ar[index] = val & 0x3f;
405 s->ar[index] = val & ~0x10;
411 s->ar[index] = val & ~0xc0;
414 s->ar[index] = val & ~0xf0;
417 s->ar[index] = val & ~0xf0;
423 s->ar_flip_flop ^= 1;
426 s->msr = val & ~0x10;
427 s->update_retrace_info(s);
430 s->sr_index = val & 7;
434 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
436 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
437 if (s->sr_index == 1) s->update_retrace_info(s);
440 s->dac_read_index = val;
441 s->dac_sub_index = 0;
445 s->dac_write_index = val;
446 s->dac_sub_index = 0;
450 s->dac_cache[s->dac_sub_index] = val;
451 if (++s->dac_sub_index == 3) {
452 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
453 s->dac_sub_index = 0;
454 s->dac_write_index++;
458 s->gr_index = val & 0x0f;
462 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
464 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
473 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
475 /* handle CR0-7 protection */
476 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
477 /* can always write bit 4 of CR7 */
478 if (s->cr_index == 7)
479 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
482 switch(s->cr_index) {
483 case 0x01: /* horizontal display end */
488 case 0x12: /* vertical display end */
489 s->cr[s->cr_index] = val;
492 s->cr[s->cr_index] = val;
496 switch(s->cr_index) {
504 s->update_retrace_info(s);
515 #ifdef CONFIG_BOCHS_VBE
516 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
518 VGAState *s = opaque;
524 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
526 VGAState *s = opaque;
529 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
530 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
531 switch(s->vbe_index) {
532 /* XXX: do not hardcode ? */
533 case VBE_DISPI_INDEX_XRES:
534 val = VBE_DISPI_MAX_XRES;
536 case VBE_DISPI_INDEX_YRES:
537 val = VBE_DISPI_MAX_YRES;
539 case VBE_DISPI_INDEX_BPP:
540 val = VBE_DISPI_MAX_BPP;
543 val = s->vbe_regs[s->vbe_index];
547 val = s->vbe_regs[s->vbe_index];
552 #ifdef DEBUG_BOCHS_VBE
553 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
558 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
560 VGAState *s = opaque;
564 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
566 VGAState *s = opaque;
568 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
569 #ifdef DEBUG_BOCHS_VBE
570 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
572 switch(s->vbe_index) {
573 case VBE_DISPI_INDEX_ID:
574 if (val == VBE_DISPI_ID0 ||
575 val == VBE_DISPI_ID1 ||
576 val == VBE_DISPI_ID2 ||
577 val == VBE_DISPI_ID3 ||
578 val == VBE_DISPI_ID4) {
579 s->vbe_regs[s->vbe_index] = val;
582 case VBE_DISPI_INDEX_XRES:
583 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
584 s->vbe_regs[s->vbe_index] = val;
587 case VBE_DISPI_INDEX_YRES:
588 if (val <= VBE_DISPI_MAX_YRES) {
589 s->vbe_regs[s->vbe_index] = val;
592 case VBE_DISPI_INDEX_BPP:
595 if (val == 4 || val == 8 || val == 15 ||
596 val == 16 || val == 24 || val == 32) {
597 s->vbe_regs[s->vbe_index] = val;
600 case VBE_DISPI_INDEX_BANK:
601 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
602 val &= (s->vbe_bank_mask >> 2);
604 val &= s->vbe_bank_mask;
606 s->vbe_regs[s->vbe_index] = val;
607 s->bank_offset = (val << 16);
609 case VBE_DISPI_INDEX_ENABLE:
610 if ((val & VBE_DISPI_ENABLED) &&
611 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
612 int h, shift_control;
614 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
615 s->vbe_regs[VBE_DISPI_INDEX_XRES];
616 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
617 s->vbe_regs[VBE_DISPI_INDEX_YRES];
618 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
619 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
621 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
622 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
624 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
625 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
626 s->vbe_start_addr = 0;
628 /* clear the screen (should be done in BIOS) */
629 if (!(val & VBE_DISPI_NOCLEARMEM)) {
630 memset(s->vram_ptr, 0,
631 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
634 /* we initialize the VGA graphic mode (should be done
636 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
637 s->cr[0x17] |= 3; /* no CGA modes */
638 s->cr[0x13] = s->vbe_line_offset >> 3;
640 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
641 /* height (only meaningful if < 1024) */
642 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
644 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
645 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
646 /* line compare to 1023 */
651 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
653 s->sr[0x01] &= ~8; /* no double line */
656 s->sr[4] |= 0x08; /* set chain 4 mode */
657 s->sr[2] |= 0x0f; /* activate all planes */
659 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
660 s->cr[0x09] &= ~0x9f; /* no double scan */
662 /* XXX: the bios should do that */
665 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
666 s->vbe_regs[s->vbe_index] = val;
668 case VBE_DISPI_INDEX_VIRT_WIDTH:
670 int w, h, line_offset;
672 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
675 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
676 line_offset = w >> 1;
678 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
679 h = s->vram_size / line_offset;
680 /* XXX: support weird bochs semantics ? */
681 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
684 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
685 s->vbe_line_offset = line_offset;
688 case VBE_DISPI_INDEX_X_OFFSET:
689 case VBE_DISPI_INDEX_Y_OFFSET:
692 s->vbe_regs[s->vbe_index] = val;
693 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
694 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
695 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
696 s->vbe_start_addr += x >> 1;
698 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
699 s->vbe_start_addr >>= 2;
709 /* called for accesses between 0xa0000 and 0xc0000 */
710 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
712 VGAState *s = opaque;
713 int memory_map_mode, plane;
716 /* convert to VGA memory offset */
717 memory_map_mode = (s->gr[6] >> 2) & 3;
719 switch(memory_map_mode) {
725 addr += s->bank_offset;
740 if (s->sr[4] & 0x08) {
741 /* chain 4 mode : simplest access */
742 ret = s->vram_ptr[addr];
743 } else if (s->gr[5] & 0x10) {
744 /* odd/even mode (aka text mode mapping) */
745 plane = (s->gr[4] & 2) | (addr & 1);
746 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
748 /* standard VGA latched access */
749 s->latch = ((uint32_t *)s->vram_ptr)[addr];
751 if (!(s->gr[5] & 0x08)) {
754 ret = GET_PLANE(s->latch, plane);
757 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
766 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
769 #ifdef TARGET_WORDS_BIGENDIAN
770 v = vga_mem_readb(opaque, addr) << 8;
771 v |= vga_mem_readb(opaque, addr + 1);
773 v = vga_mem_readb(opaque, addr);
774 v |= vga_mem_readb(opaque, addr + 1) << 8;
779 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
782 #ifdef TARGET_WORDS_BIGENDIAN
783 v = vga_mem_readb(opaque, addr) << 24;
784 v |= vga_mem_readb(opaque, addr + 1) << 16;
785 v |= vga_mem_readb(opaque, addr + 2) << 8;
786 v |= vga_mem_readb(opaque, addr + 3);
788 v = vga_mem_readb(opaque, addr);
789 v |= vga_mem_readb(opaque, addr + 1) << 8;
790 v |= vga_mem_readb(opaque, addr + 2) << 16;
791 v |= vga_mem_readb(opaque, addr + 3) << 24;
796 /* called for accesses between 0xa0000 and 0xc0000 */
797 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
799 VGAState *s = opaque;
800 int memory_map_mode, plane, write_mode, b, func_select, mask;
801 uint32_t write_mask, bit_mask, set_mask;
804 printf("vga: [0x%x] = 0x%02x\n", addr, val);
806 /* convert to VGA memory offset */
807 memory_map_mode = (s->gr[6] >> 2) & 3;
809 switch(memory_map_mode) {
815 addr += s->bank_offset;
830 if (s->sr[4] & 0x08) {
831 /* chain 4 mode : simplest access */
834 if (s->sr[2] & mask) {
835 s->vram_ptr[addr] = val;
837 printf("vga: chain4: [0x%x]\n", addr);
839 s->plane_updated |= mask; /* only used to detect font change */
840 cpu_physical_memory_set_dirty(s->vram_offset + addr);
842 } else if (s->gr[5] & 0x10) {
843 /* odd/even mode (aka text mode mapping) */
844 plane = (s->gr[4] & 2) | (addr & 1);
846 if (s->sr[2] & mask) {
847 addr = ((addr & ~1) << 1) | plane;
848 s->vram_ptr[addr] = val;
850 printf("vga: odd/even: [0x%x]\n", addr);
852 s->plane_updated |= mask; /* only used to detect font change */
853 cpu_physical_memory_set_dirty(s->vram_offset + addr);
856 /* standard VGA latched access */
857 write_mode = s->gr[5] & 3;
863 val = ((val >> b) | (val << (8 - b))) & 0xff;
867 /* apply set/reset mask */
868 set_mask = mask16[s->gr[1]];
869 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
876 val = mask16[val & 0x0f];
882 val = (val >> b) | (val << (8 - b));
884 bit_mask = s->gr[8] & val;
885 val = mask16[s->gr[0]];
889 /* apply logical operation */
890 func_select = s->gr[3] >> 3;
891 switch(func_select) {
911 bit_mask |= bit_mask << 8;
912 bit_mask |= bit_mask << 16;
913 val = (val & bit_mask) | (s->latch & ~bit_mask);
916 /* mask data according to sr[2] */
918 s->plane_updated |= mask; /* only used to detect font change */
919 write_mask = mask16[mask];
920 ((uint32_t *)s->vram_ptr)[addr] =
921 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
924 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
925 addr * 4, write_mask, val);
927 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
931 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
933 #ifdef TARGET_WORDS_BIGENDIAN
934 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
935 vga_mem_writeb(opaque, addr + 1, val & 0xff);
937 vga_mem_writeb(opaque, addr, val & 0xff);
938 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
942 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
944 #ifdef TARGET_WORDS_BIGENDIAN
945 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
946 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
947 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
948 vga_mem_writeb(opaque, addr + 3, val & 0xff);
950 vga_mem_writeb(opaque, addr, val & 0xff);
951 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
952 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
953 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
957 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
958 const uint8_t *font_ptr, int h,
959 uint32_t fgcol, uint32_t bgcol);
960 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
961 const uint8_t *font_ptr, int h,
962 uint32_t fgcol, uint32_t bgcol, int dup9);
963 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
964 const uint8_t *s, int width);
967 #include "vga_template.h"
970 #include "vga_template.h"
974 #include "vga_template.h"
977 #include "vga_template.h"
981 #include "vga_template.h"
984 #include "vga_template.h"
988 #include "vga_template.h"
990 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
993 col = rgb_to_pixel8(r, g, b);
999 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1002 col = rgb_to_pixel15(r, g, b);
1007 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1011 col = rgb_to_pixel15bgr(r, g, b);
1016 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1019 col = rgb_to_pixel16(r, g, b);
1024 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1028 col = rgb_to_pixel16bgr(r, g, b);
1033 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1036 col = rgb_to_pixel32(r, g, b);
1040 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1043 col = rgb_to_pixel32bgr(r, g, b);
1047 /* return true if the palette was modified */
1048 static int update_palette16(VGAState *s)
1051 uint32_t v, col, *palette;
1054 palette = s->last_palette;
1055 for(i = 0; i < 16; i++) {
1057 if (s->ar[0x10] & 0x80)
1058 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1060 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1062 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1063 c6_to_8(s->palette[v + 1]),
1064 c6_to_8(s->palette[v + 2]));
1065 if (col != palette[i]) {
1073 /* return true if the palette was modified */
1074 static int update_palette256(VGAState *s)
1077 uint32_t v, col, *palette;
1080 palette = s->last_palette;
1082 for(i = 0; i < 256; i++) {
1084 col = s->rgb_to_pixel(s->palette[v],
1088 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1089 c6_to_8(s->palette[v + 1]),
1090 c6_to_8(s->palette[v + 2]));
1092 if (col != palette[i]) {
1101 static void vga_get_offsets(VGAState *s,
1102 uint32_t *pline_offset,
1103 uint32_t *pstart_addr,
1104 uint32_t *pline_compare)
1106 uint32_t start_addr, line_offset, line_compare;
1107 #ifdef CONFIG_BOCHS_VBE
1108 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1109 line_offset = s->vbe_line_offset;
1110 start_addr = s->vbe_start_addr;
1111 line_compare = 65535;
1115 /* compute line_offset in bytes */
1116 line_offset = s->cr[0x13];
1119 /* starting address */
1120 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1123 line_compare = s->cr[0x18] |
1124 ((s->cr[0x07] & 0x10) << 4) |
1125 ((s->cr[0x09] & 0x40) << 3);
1127 *pline_offset = line_offset;
1128 *pstart_addr = start_addr;
1129 *pline_compare = line_compare;
1132 /* update start_addr and line_offset. Return TRUE if modified */
1133 static int update_basic_params(VGAState *s)
1136 uint32_t start_addr, line_offset, line_compare;
1140 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1142 if (line_offset != s->line_offset ||
1143 start_addr != s->start_addr ||
1144 line_compare != s->line_compare) {
1145 s->line_offset = line_offset;
1146 s->start_addr = start_addr;
1147 s->line_compare = line_compare;
1155 static inline int get_depth_index(DisplayState *s)
1179 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1189 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1191 vga_draw_glyph16_16,
1192 vga_draw_glyph16_16,
1193 vga_draw_glyph16_32,
1194 vga_draw_glyph16_32,
1195 vga_draw_glyph16_16,
1196 vga_draw_glyph16_16,
1199 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1209 static const uint8_t cursor_glyph[32 * 4] = {
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1220 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1221 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 static void vga_draw_text(VGAState *s, int full_update)
1238 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1239 int cx_min, cx_max, linesize, x_incr;
1240 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1241 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1242 const uint8_t *font_ptr, *font_base[2];
1243 int dup9, line_offset, depth_index;
1245 uint32_t *ch_attr_ptr;
1246 vga_draw_glyph8_func *vga_draw_glyph8;
1247 vga_draw_glyph9_func *vga_draw_glyph9;
1249 full_update |= update_palette16(s);
1250 palette = s->last_palette;
1252 /* compute font data address (in plane 2) */
1254 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1255 if (offset != s->font_offsets[0]) {
1256 s->font_offsets[0] = offset;
1259 font_base[0] = s->vram_ptr + offset;
1261 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1262 font_base[1] = s->vram_ptr + offset;
1263 if (offset != s->font_offsets[1]) {
1264 s->font_offsets[1] = offset;
1267 if (s->plane_updated & (1 << 2)) {
1268 /* if the plane 2 was modified since the last display, it
1269 indicates the font may have been modified */
1270 s->plane_updated = 0;
1273 full_update |= update_basic_params(s);
1275 line_offset = s->line_offset;
1276 s1 = s->vram_ptr + (s->start_addr * 4);
1278 /* total width & height */
1279 cheight = (s->cr[9] & 0x1f) + 1;
1281 if (!(s->sr[1] & 0x01))
1283 if (s->sr[1] & 0x08)
1284 cw = 16; /* NOTE: no 18 pixel wide */
1285 x_incr = cw * ((s->ds->depth + 7) >> 3);
1286 width = (s->cr[0x01] + 1);
1287 if (s->cr[0x06] == 100) {
1288 /* ugly hack for CGA 160x100x16 - explain me the logic */
1291 height = s->cr[0x12] |
1292 ((s->cr[0x07] & 0x02) << 7) |
1293 ((s->cr[0x07] & 0x40) << 3);
1294 height = (height + 1) / cheight;
1296 if ((height * width) > CH_ATTR_SIZE) {
1297 /* better than nothing: exit if transient size is too big */
1301 if (width != s->last_width || height != s->last_height ||
1302 cw != s->last_cw || cheight != s->last_ch) {
1303 s->last_scr_width = width * cw;
1304 s->last_scr_height = height * cheight;
1305 qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
1306 s->last_width = width;
1307 s->last_height = height;
1308 s->last_ch = cheight;
1312 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1313 if (cursor_offset != s->cursor_offset ||
1314 s->cr[0xa] != s->cursor_start ||
1315 s->cr[0xb] != s->cursor_end) {
1316 /* if the cursor position changed, we update the old and new
1318 if (s->cursor_offset < CH_ATTR_SIZE)
1319 s->last_ch_attr[s->cursor_offset] = -1;
1320 if (cursor_offset < CH_ATTR_SIZE)
1321 s->last_ch_attr[cursor_offset] = -1;
1322 s->cursor_offset = cursor_offset;
1323 s->cursor_start = s->cr[0xa];
1324 s->cursor_end = s->cr[0xb];
1326 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1328 depth_index = get_depth_index(s->ds);
1330 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1332 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1333 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1336 linesize = s->ds->linesize;
1337 ch_attr_ptr = s->last_ch_attr;
1338 for(cy = 0; cy < height; cy++) {
1343 for(cx = 0; cx < width; cx++) {
1344 ch_attr = *(uint16_t *)src;
1345 if (full_update || ch_attr != *ch_attr_ptr) {
1350 *ch_attr_ptr = ch_attr;
1351 #ifdef WORDS_BIGENDIAN
1353 cattr = ch_attr & 0xff;
1355 ch = ch_attr & 0xff;
1356 cattr = ch_attr >> 8;
1358 font_ptr = font_base[(cattr >> 3) & 1];
1359 font_ptr += 32 * 4 * ch;
1360 bgcol = palette[cattr >> 4];
1361 fgcol = palette[cattr & 0x0f];
1363 vga_draw_glyph8(d1, linesize,
1364 font_ptr, cheight, fgcol, bgcol);
1367 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1369 vga_draw_glyph9(d1, linesize,
1370 font_ptr, cheight, fgcol, bgcol, dup9);
1372 if (src == cursor_ptr &&
1373 !(s->cr[0x0a] & 0x20)) {
1374 int line_start, line_last, h;
1375 /* draw the cursor */
1376 line_start = s->cr[0x0a] & 0x1f;
1377 line_last = s->cr[0x0b] & 0x1f;
1378 /* XXX: check that */
1379 if (line_last > cheight - 1)
1380 line_last = cheight - 1;
1381 if (line_last >= line_start && line_start < cheight) {
1382 h = line_last - line_start + 1;
1383 d = d1 + linesize * line_start;
1385 vga_draw_glyph8(d, linesize,
1386 cursor_glyph, h, fgcol, bgcol);
1388 vga_draw_glyph9(d, linesize,
1389 cursor_glyph, h, fgcol, bgcol, 1);
1399 dpy_update(s->ds, cx_min * cw, cy * cheight,
1400 (cx_max - cx_min + 1) * cw, cheight);
1402 dest += linesize * cheight;
1421 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1431 vga_draw_line2d2_16,
1432 vga_draw_line2d2_16,
1433 vga_draw_line2d2_32,
1434 vga_draw_line2d2_32,
1435 vga_draw_line2d2_16,
1436 vga_draw_line2d2_16,
1447 vga_draw_line4d2_16,
1448 vga_draw_line4d2_16,
1449 vga_draw_line4d2_32,
1450 vga_draw_line4d2_32,
1451 vga_draw_line4d2_16,
1452 vga_draw_line4d2_16,
1455 vga_draw_line8d2_16,
1456 vga_draw_line8d2_16,
1457 vga_draw_line8d2_32,
1458 vga_draw_line8d2_32,
1459 vga_draw_line8d2_16,
1460 vga_draw_line8d2_16,
1474 vga_draw_line15_32bgr,
1475 vga_draw_line15_15bgr,
1476 vga_draw_line15_16bgr,
1482 vga_draw_line16_32bgr,
1483 vga_draw_line16_15bgr,
1484 vga_draw_line16_16bgr,
1490 vga_draw_line24_32bgr,
1491 vga_draw_line24_15bgr,
1492 vga_draw_line24_16bgr,
1498 vga_draw_line32_32bgr,
1499 vga_draw_line32_15bgr,
1500 vga_draw_line32_16bgr,
1503 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1505 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1510 rgb_to_pixel32bgr_dup,
1511 rgb_to_pixel15bgr_dup,
1512 rgb_to_pixel16bgr_dup,
1515 static int vga_get_bpp(VGAState *s)
1518 #ifdef CONFIG_BOCHS_VBE
1519 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1520 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1529 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1533 #ifdef CONFIG_BOCHS_VBE
1534 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1535 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1536 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1540 width = (s->cr[0x01] + 1) * 8;
1541 height = s->cr[0x12] |
1542 ((s->cr[0x07] & 0x02) << 7) |
1543 ((s->cr[0x07] & 0x40) << 3);
1544 height = (height + 1);
1550 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1553 if (y1 >= VGA_MAX_HEIGHT)
1555 if (y2 >= VGA_MAX_HEIGHT)
1556 y2 = VGA_MAX_HEIGHT;
1557 for(y = y1; y < y2; y++) {
1558 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1565 static void vga_draw_graphic(VGAState *s, int full_update)
1567 int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask;
1568 int width, height, shift_control, line_offset, page0, page1, bwidth, bits;
1569 int disp_width, multi_scan, multi_run;
1571 uint32_t v, addr1, addr;
1572 vga_draw_line_func *vga_draw_line;
1574 full_update |= update_basic_params(s);
1576 s->get_resolution(s, &width, &height);
1579 shift_control = (s->gr[0x05] >> 5) & 3;
1580 double_scan = (s->cr[0x09] >> 7);
1581 if (shift_control != 1) {
1582 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1584 /* in CGA modes, multi_scan is ignored */
1585 /* XXX: is it correct ? */
1586 multi_scan = double_scan;
1588 multi_run = multi_scan;
1589 if (shift_control != s->shift_control ||
1590 double_scan != s->double_scan) {
1592 s->shift_control = shift_control;
1593 s->double_scan = double_scan;
1596 if (shift_control == 0) {
1597 full_update |= update_palette16(s);
1598 if (s->sr[0x01] & 8) {
1599 v = VGA_DRAW_LINE4D2;
1605 } else if (shift_control == 1) {
1606 full_update |= update_palette16(s);
1607 if (s->sr[0x01] & 8) {
1608 v = VGA_DRAW_LINE2D2;
1615 switch(s->get_bpp(s)) {
1618 full_update |= update_palette256(s);
1619 v = VGA_DRAW_LINE8D2;
1623 full_update |= update_palette256(s);
1628 v = VGA_DRAW_LINE15;
1632 v = VGA_DRAW_LINE16;
1636 v = VGA_DRAW_LINE24;
1640 v = VGA_DRAW_LINE32;
1645 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1647 if (disp_width != s->last_width ||
1648 height != s->last_height) {
1649 qemu_console_resize(s->console, disp_width, height);
1650 s->last_scr_width = disp_width;
1651 s->last_scr_height = height;
1652 s->last_width = disp_width;
1653 s->last_height = height;
1656 if (s->cursor_invalidate)
1657 s->cursor_invalidate(s);
1659 line_offset = s->line_offset;
1661 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1662 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1664 addr1 = (s->start_addr * 4);
1665 bwidth = (width * bits + 7) / 8;
1667 page_min = 0x7fffffff;
1670 linesize = s->ds->linesize;
1672 for(y = 0; y < height; y++) {
1674 if (!(s->cr[0x17] & 1)) {
1676 /* CGA compatibility handling */
1677 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1678 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1680 if (!(s->cr[0x17] & 2)) {
1681 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1683 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1684 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1685 update = full_update |
1686 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1687 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1688 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1689 /* if wide line, can use another page */
1690 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1693 /* explicit invalidation for the hardware cursor */
1694 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1698 if (page0 < page_min)
1700 if (page1 > page_max)
1702 vga_draw_line(s, d, s->vram_ptr + addr, width);
1703 if (s->cursor_draw_line)
1704 s->cursor_draw_line(s, d, y);
1707 /* flush to display */
1708 dpy_update(s->ds, 0, y_start,
1709 disp_width, y - y_start);
1714 mask = (s->cr[0x17] & 3) ^ 3;
1715 if ((y1 & mask) == mask)
1716 addr1 += line_offset;
1718 multi_run = multi_scan;
1722 /* line compare acts on the displayed lines */
1723 if (y == s->line_compare)
1728 /* flush to display */
1729 dpy_update(s->ds, 0, y_start,
1730 disp_width, y - y_start);
1732 /* reset modified pages */
1733 if (page_max != -1) {
1734 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1737 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1740 static void vga_draw_blank(VGAState *s, int full_update)
1747 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1749 if (s->ds->depth == 8)
1750 val = s->rgb_to_pixel(0, 0, 0);
1753 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
1755 for(i = 0; i < s->last_scr_height; i++) {
1757 d += s->ds->linesize;
1759 dpy_update(s->ds, 0, 0,
1760 s->last_scr_width, s->last_scr_height);
1763 #define GMODE_TEXT 0
1764 #define GMODE_GRAPH 1
1765 #define GMODE_BLANK 2
1767 static void vga_update_display(void *opaque)
1769 VGAState *s = (VGAState *)opaque;
1770 int full_update, graphic_mode;
1772 if (s->ds->depth == 0) {
1776 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1779 if (!(s->ar_index & 0x20)) {
1780 graphic_mode = GMODE_BLANK;
1782 graphic_mode = s->gr[6] & 1;
1784 if (graphic_mode != s->graphic_mode) {
1785 s->graphic_mode = graphic_mode;
1788 switch(graphic_mode) {
1790 vga_draw_text(s, full_update);
1793 vga_draw_graphic(s, full_update);
1797 vga_draw_blank(s, full_update);
1803 /* force a full display refresh */
1804 static void vga_invalidate_display(void *opaque)
1806 VGAState *s = (VGAState *)opaque;
1809 s->last_height = -1;
1812 static void vga_reset(VGAState *s)
1814 memset(s, 0, sizeof(VGAState));
1815 s->graphic_mode = -1; /* force full update */
1818 #define TEXTMODE_X(x) ((x) % width)
1819 #define TEXTMODE_Y(x) ((x) / width)
1820 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1821 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1822 /* relay text rendering to the display driver
1823 * instead of doing a full vga_update_display() */
1824 static void vga_update_text(void *opaque, console_ch_t *chardata)
1826 VGAState *s = (VGAState *) opaque;
1827 int graphic_mode, i, cursor_offset, cursor_visible;
1828 int cw, cheight, width, height, size, c_min, c_max;
1830 console_ch_t *dst, val;
1831 char msg_buffer[80];
1832 int full_update = 0;
1834 if (!(s->ar_index & 0x20)) {
1835 graphic_mode = GMODE_BLANK;
1837 graphic_mode = s->gr[6] & 1;
1839 if (graphic_mode != s->graphic_mode) {
1840 s->graphic_mode = graphic_mode;
1843 if (s->last_width == -1) {
1848 switch (graphic_mode) {
1850 /* TODO: update palette */
1851 full_update |= update_basic_params(s);
1853 /* total width & height */
1854 cheight = (s->cr[9] & 0x1f) + 1;
1856 if (!(s->sr[1] & 0x01))
1858 if (s->sr[1] & 0x08)
1859 cw = 16; /* NOTE: no 18 pixel wide */
1860 width = (s->cr[0x01] + 1);
1861 if (s->cr[0x06] == 100) {
1862 /* ugly hack for CGA 160x100x16 - explain me the logic */
1865 height = s->cr[0x12] |
1866 ((s->cr[0x07] & 0x02) << 7) |
1867 ((s->cr[0x07] & 0x40) << 3);
1868 height = (height + 1) / cheight;
1871 size = (height * width);
1872 if (size > CH_ATTR_SIZE) {
1876 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1881 if (width != s->last_width || height != s->last_height ||
1882 cw != s->last_cw || cheight != s->last_ch) {
1883 s->last_scr_width = width * cw;
1884 s->last_scr_height = height * cheight;
1885 qemu_console_resize(s->console, width, height);
1886 s->last_width = width;
1887 s->last_height = height;
1888 s->last_ch = cheight;
1893 /* Update "hardware" cursor */
1894 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1895 if (cursor_offset != s->cursor_offset ||
1896 s->cr[0xa] != s->cursor_start ||
1897 s->cr[0xb] != s->cursor_end || full_update) {
1898 cursor_visible = !(s->cr[0xa] & 0x20);
1899 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1901 TEXTMODE_X(cursor_offset),
1902 TEXTMODE_Y(cursor_offset));
1904 dpy_cursor(s->ds, -1, -1);
1905 s->cursor_offset = cursor_offset;
1906 s->cursor_start = s->cr[0xa];
1907 s->cursor_end = s->cr[0xb];
1910 src = (uint32_t *) s->vram_ptr + s->start_addr;
1914 for (i = 0; i < size; src ++, dst ++, i ++)
1915 console_write_ch(dst, VMEM2CHTYPE(*src));
1917 dpy_update(s->ds, 0, 0, width, height);
1921 for (i = 0; i < size; src ++, dst ++, i ++) {
1922 console_write_ch(&val, VMEM2CHTYPE(*src));
1930 for (; i < size; src ++, dst ++, i ++) {
1931 console_write_ch(&val, VMEM2CHTYPE(*src));
1938 if (c_min <= c_max) {
1939 i = TEXTMODE_Y(c_min);
1940 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1949 s->get_resolution(s, &width, &height);
1950 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
1958 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
1962 /* Display a message */
1964 s->last_height = height = 3;
1965 dpy_cursor(s->ds, -1, -1);
1966 qemu_console_resize(s->console, s->last_width, height);
1968 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
1969 console_write_ch(dst ++, ' ');
1971 size = strlen(msg_buffer);
1972 width = (s->last_width - size) / 2;
1973 dst = chardata + s->last_width + width;
1974 for (i = 0; i < size; i ++)
1975 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
1977 dpy_update(s->ds, 0, 0, s->last_width, height);
1980 static CPUReadMemoryFunc *vga_mem_read[3] = {
1986 static CPUWriteMemoryFunc *vga_mem_write[3] = {
1992 static void vga_save(QEMUFile *f, void *opaque)
1994 VGAState *s = opaque;
1998 pci_device_save(s->pci_dev, f);
2000 qemu_put_be32s(f, &s->latch);
2001 qemu_put_8s(f, &s->sr_index);
2002 qemu_put_buffer(f, s->sr, 8);
2003 qemu_put_8s(f, &s->gr_index);
2004 qemu_put_buffer(f, s->gr, 16);
2005 qemu_put_8s(f, &s->ar_index);
2006 qemu_put_buffer(f, s->ar, 21);
2007 qemu_put_be32(f, s->ar_flip_flop);
2008 qemu_put_8s(f, &s->cr_index);
2009 qemu_put_buffer(f, s->cr, 256);
2010 qemu_put_8s(f, &s->msr);
2011 qemu_put_8s(f, &s->fcr);
2012 qemu_put_byte(f, s->st00);
2013 qemu_put_8s(f, &s->st01);
2015 qemu_put_8s(f, &s->dac_state);
2016 qemu_put_8s(f, &s->dac_sub_index);
2017 qemu_put_8s(f, &s->dac_read_index);
2018 qemu_put_8s(f, &s->dac_write_index);
2019 qemu_put_buffer(f, s->dac_cache, 3);
2020 qemu_put_buffer(f, s->palette, 768);
2022 qemu_put_be32(f, s->bank_offset);
2023 #ifdef CONFIG_BOCHS_VBE
2024 qemu_put_byte(f, 1);
2025 qemu_put_be16s(f, &s->vbe_index);
2026 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2027 qemu_put_be16s(f, &s->vbe_regs[i]);
2028 qemu_put_be32s(f, &s->vbe_start_addr);
2029 qemu_put_be32s(f, &s->vbe_line_offset);
2030 qemu_put_be32s(f, &s->vbe_bank_mask);
2032 qemu_put_byte(f, 0);
2036 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2038 VGAState *s = opaque;
2044 if (s->pci_dev && version_id >= 2) {
2045 ret = pci_device_load(s->pci_dev, f);
2050 qemu_get_be32s(f, &s->latch);
2051 qemu_get_8s(f, &s->sr_index);
2052 qemu_get_buffer(f, s->sr, 8);
2053 qemu_get_8s(f, &s->gr_index);
2054 qemu_get_buffer(f, s->gr, 16);
2055 qemu_get_8s(f, &s->ar_index);
2056 qemu_get_buffer(f, s->ar, 21);
2057 s->ar_flip_flop=qemu_get_be32(f);
2058 qemu_get_8s(f, &s->cr_index);
2059 qemu_get_buffer(f, s->cr, 256);
2060 qemu_get_8s(f, &s->msr);
2061 qemu_get_8s(f, &s->fcr);
2062 qemu_get_8s(f, &s->st00);
2063 qemu_get_8s(f, &s->st01);
2065 qemu_get_8s(f, &s->dac_state);
2066 qemu_get_8s(f, &s->dac_sub_index);
2067 qemu_get_8s(f, &s->dac_read_index);
2068 qemu_get_8s(f, &s->dac_write_index);
2069 qemu_get_buffer(f, s->dac_cache, 3);
2070 qemu_get_buffer(f, s->palette, 768);
2072 s->bank_offset=qemu_get_be32(f);
2073 is_vbe = qemu_get_byte(f);
2074 #ifdef CONFIG_BOCHS_VBE
2077 qemu_get_be16s(f, &s->vbe_index);
2078 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2079 qemu_get_be16s(f, &s->vbe_regs[i]);
2080 qemu_get_be32s(f, &s->vbe_start_addr);
2081 qemu_get_be32s(f, &s->vbe_line_offset);
2082 qemu_get_be32s(f, &s->vbe_bank_mask);
2089 s->graphic_mode = -1;
2093 typedef struct PCIVGAState {
2098 static void vga_map(PCIDevice *pci_dev, int region_num,
2099 uint32_t addr, uint32_t size, int type)
2101 PCIVGAState *d = (PCIVGAState *)pci_dev;
2102 VGAState *s = &d->vga_state;
2103 if (region_num == PCI_ROM_SLOT) {
2104 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2106 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2110 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2111 unsigned long vga_ram_offset, int vga_ram_size)
2115 for(i = 0;i < 256; i++) {
2117 for(j = 0; j < 8; j++) {
2118 v |= ((i >> j) & 1) << (j * 4);
2123 for(j = 0; j < 4; j++) {
2124 v |= ((i >> (2 * j)) & 3) << (j * 4);
2128 for(i = 0; i < 16; i++) {
2130 for(j = 0; j < 4; j++) {
2133 v |= b << (2 * j + 1);
2140 s->vram_ptr = vga_ram_base;
2141 s->vram_offset = vga_ram_offset;
2142 s->vram_size = vga_ram_size;
2144 s->get_bpp = vga_get_bpp;
2145 s->get_offsets = vga_get_offsets;
2146 s->get_resolution = vga_get_resolution;
2147 s->update = vga_update_display;
2148 s->invalidate = vga_invalidate_display;
2149 s->screen_dump = vga_screen_dump;
2150 s->text_update = vga_update_text;
2151 switch (vga_retrace_method) {
2152 case VGA_RETRACE_DUMB:
2153 s->retrace = vga_dumb_retrace;
2154 s->update_retrace_info = vga_dumb_update_retrace_info;
2157 case VGA_RETRACE_PRECISE:
2158 s->retrace = vga_precise_retrace;
2159 s->update_retrace_info = vga_precise_update_retrace_info;
2160 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
2165 /* used by both ISA and PCI */
2166 void vga_init(VGAState *s)
2170 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2172 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2174 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2175 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2176 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2177 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2179 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2181 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2182 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2183 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2184 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2187 #ifdef CONFIG_BOCHS_VBE
2188 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2189 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2190 #if defined (TARGET_I386)
2191 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2192 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2194 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2195 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2197 /* old Bochs IO ports */
2198 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2199 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2201 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2202 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2204 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2205 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2207 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2208 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2210 #endif /* CONFIG_BOCHS_VBE */
2212 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2213 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2217 /* Memory mapped interface */
2218 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2220 VGAState *s = opaque;
2222 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xff;
2225 static void vga_mm_writeb (void *opaque,
2226 target_phys_addr_t addr, uint32_t value)
2228 VGAState *s = opaque;
2230 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xff);
2233 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2235 VGAState *s = opaque;
2237 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xffff;
2240 static void vga_mm_writew (void *opaque,
2241 target_phys_addr_t addr, uint32_t value)
2243 VGAState *s = opaque;
2245 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xffff);
2248 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2250 VGAState *s = opaque;
2252 return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift);
2255 static void vga_mm_writel (void *opaque,
2256 target_phys_addr_t addr, uint32_t value)
2258 VGAState *s = opaque;
2260 vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value);
2263 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2269 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2275 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2276 target_phys_addr_t ctrl_base, int it_shift)
2278 int s_ioport_ctrl, vga_io_memory;
2280 s->base_ctrl = ctrl_base;
2281 s->it_shift = it_shift;
2282 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2283 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2285 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2287 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2289 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2292 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2293 unsigned long vga_ram_offset, int vga_ram_size)
2297 s = qemu_mallocz(sizeof(VGAState));
2301 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2304 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2305 s->screen_dump, s->text_update, s);
2307 #ifdef CONFIG_BOCHS_VBE
2308 /* XXX: use optimized standard vga accesses */
2309 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2310 vga_ram_size, vga_ram_offset);
2315 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
2316 unsigned long vga_ram_offset, int vga_ram_size,
2317 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2322 s = qemu_mallocz(sizeof(VGAState));
2326 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2327 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2329 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2330 s->screen_dump, s->text_update, s);
2332 #ifdef CONFIG_BOCHS_VBE
2333 /* XXX: use optimized standard vga accesses */
2334 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2335 vga_ram_size, vga_ram_offset);
2340 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2341 unsigned long vga_ram_offset, int vga_ram_size,
2342 unsigned long vga_bios_offset, int vga_bios_size)
2348 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2349 sizeof(PCIVGAState),
2355 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2358 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2359 s->screen_dump, s->text_update, s);
2361 s->pci_dev = &d->dev;
2363 pci_conf = d->dev.config;
2364 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2365 pci_conf[0x01] = 0x12;
2366 pci_conf[0x02] = 0x11;
2367 pci_conf[0x03] = 0x11;
2368 pci_conf[0x0a] = 0x00; // VGA controller
2369 pci_conf[0x0b] = 0x03;
2370 pci_conf[0x0e] = 0x00; // header_type
2372 /* XXX: vga_ram_size must be a power of two */
2373 pci_register_io_region(&d->dev, 0, vga_ram_size,
2374 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2375 if (vga_bios_size != 0) {
2376 unsigned int bios_total_size;
2377 s->bios_offset = vga_bios_offset;
2378 s->bios_size = vga_bios_size;
2379 /* must be a power of two */
2380 bios_total_size = 1;
2381 while (bios_total_size < vga_bios_size)
2382 bios_total_size <<= 1;
2383 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2384 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2389 /********************************************************/
2390 /* vga screen dump */
2392 static int vga_save_w, vga_save_h;
2394 static void vga_save_dpy_update(DisplayState *s,
2395 int x, int y, int w, int h)
2399 static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2401 s->linesize = w * 4;
2402 s->data = qemu_malloc(h * s->linesize);
2407 static void vga_save_dpy_refresh(DisplayState *s)
2411 int ppm_save(const char *filename, uint8_t *data,
2412 int w, int h, int linesize)
2419 f = fopen(filename, "wb");
2422 fprintf(f, "P6\n%d %d\n%d\n",
2425 for(y = 0; y < h; y++) {
2427 for(x = 0; x < w; x++) {
2429 fputc((v >> 16) & 0xff, f);
2430 fputc((v >> 8) & 0xff, f);
2431 fputc((v) & 0xff, f);
2440 /* save the vga display in a PPM image even if no display is
2442 static void vga_screen_dump(void *opaque, const char *filename)
2444 VGAState *s = (VGAState *)opaque;
2445 DisplayState *saved_ds, ds1, *ds = &ds1;
2447 /* XXX: this is a little hackish */
2448 vga_invalidate_display(s);
2451 memset(ds, 0, sizeof(DisplayState));
2452 ds->dpy_update = vga_save_dpy_update;
2453 ds->dpy_resize = vga_save_dpy_resize;
2454 ds->dpy_refresh = vga_save_dpy_refresh;
2458 s->graphic_mode = -1;
2459 vga_update_display(s);
2462 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2464 qemu_free(ds->data);