4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
34 //#define DEBUG_VGA_MEM
35 //#define DEBUG_VGA_REG
37 //#define DEBUG_BOCHS_VBE
39 /* force some bits to zero */
40 const uint8_t sr_mask[8] = {
51 const uint8_t gr_mask[16] = {
70 #define cbswap_32(__x) \
72 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
73 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
74 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
75 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77 #ifdef WORDS_BIGENDIAN
78 #define PAT(x) cbswap_32(x)
83 #ifdef WORDS_BIGENDIAN
89 #ifdef WORDS_BIGENDIAN
90 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
95 static const uint32_t mask16[16] = {
116 #ifdef WORDS_BIGENDIAN
119 #define PAT(x) cbswap_32(x)
122 static const uint32_t dmask16[16] = {
141 static const uint32_t dmask4[4] = {
148 static uint32_t expand4[256];
149 static uint16_t expand2[256];
150 static uint8_t expand4to8[16];
152 static void vga_screen_dump(void *opaque, const char *filename);
154 static void vga_dumb_update_retrace_info(VGAState *s)
159 static void vga_precise_update_retrace_info(VGAState *s)
162 int hretr_start_char;
163 int hretr_skew_chars;
167 int vretr_start_line;
170 int div2, sldiv2, dots;
173 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
174 int64_t chars_per_sec;
175 struct vga_precise_retrace *r = &s->retrace_info.precise;
177 htotal_chars = s->cr[0x00] + 5;
178 hretr_start_char = s->cr[0x04];
179 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
180 hretr_end_char = s->cr[0x05] & 0x1f;
182 vtotal_lines = (s->cr[0x06]
183 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
185 vretr_start_line = s->cr[0x10]
186 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
188 vretr_end_line = s->cr[0x11] & 0xf;
191 div2 = (s->cr[0x17] >> 2) & 1;
192 sldiv2 = (s->cr[0x17] >> 3) & 1;
194 clocking_mode = (s->sr[0x01] >> 3) & 1;
195 clock_sel = (s->msr >> 2) & 3;
196 dots = (s->msr & 1) ? 8 : 9;
198 chars_per_sec = clk_hz[clock_sel] / dots;
200 htotal_chars <<= clocking_mode;
202 r->total_chars = vtotal_lines * htotal_chars;
204 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 r->ticks_per_char = ticks_per_sec / chars_per_sec;
209 r->vstart = vretr_start_line;
210 r->vend = r->vstart + vretr_end_line + 1;
212 r->hstart = hretr_start_char + hretr_skew_chars;
213 r->hend = r->hstart + hretr_end_char + 1;
214 r->htotal = htotal_chars;
226 "div2 = %d sldiv2 = %d\n"
227 "clocking_mode = %d\n"
228 "clock_sel = %d %d\n"
230 "ticks/char = %lld\n"
232 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
250 static uint8_t vga_precise_retrace(VGAState *s)
252 struct vga_precise_retrace *r = &s->retrace_info.precise;
253 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255 if (r->total_chars) {
256 int cur_line, cur_line_char, cur_char;
259 cur_tick = qemu_get_clock(vm_clock);
261 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
262 cur_line = cur_char / r->htotal;
264 if (cur_line >= r->vstart && cur_line <= r->vend) {
265 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
267 cur_line_char = cur_char % r->htotal;
268 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
269 val |= ST01_DISP_ENABLE;
275 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
279 static uint8_t vga_dumb_retrace(VGAState *s)
281 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
284 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
286 VGAState *s = opaque;
289 /* check port range access depending on color/monochrome mode */
290 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
291 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
296 if (s->ar_flip_flop == 0) {
303 index = s->ar_index & 0x1f;
316 val = s->sr[s->sr_index];
318 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
325 val = s->dac_write_index;
328 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
329 if (++s->dac_sub_index == 3) {
330 s->dac_sub_index = 0;
344 val = s->gr[s->gr_index];
346 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
355 val = s->cr[s->cr_index];
357 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
362 /* just toggle to fool polling */
363 val = s->st01 = s->retrace(s);
371 #if defined(DEBUG_VGA)
372 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
377 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
379 VGAState *s = opaque;
382 /* check port range access depending on color/monochrome mode */
383 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
384 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
388 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
393 if (s->ar_flip_flop == 0) {
397 index = s->ar_index & 0x1f;
400 s->ar[index] = val & 0x3f;
403 s->ar[index] = val & ~0x10;
409 s->ar[index] = val & ~0xc0;
412 s->ar[index] = val & ~0xf0;
415 s->ar[index] = val & ~0xf0;
421 s->ar_flip_flop ^= 1;
424 s->msr = val & ~0x10;
425 s->update_retrace_info(s);
428 s->sr_index = val & 7;
432 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
435 if (s->sr_index == 1) s->update_retrace_info(s);
438 s->dac_read_index = val;
439 s->dac_sub_index = 0;
443 s->dac_write_index = val;
444 s->dac_sub_index = 0;
448 s->dac_cache[s->dac_sub_index] = val;
449 if (++s->dac_sub_index == 3) {
450 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
451 s->dac_sub_index = 0;
452 s->dac_write_index++;
456 s->gr_index = val & 0x0f;
460 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
471 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473 /* handle CR0-7 protection */
474 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
475 /* can always write bit 4 of CR7 */
476 if (s->cr_index == 7)
477 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
480 switch(s->cr_index) {
481 case 0x01: /* horizontal display end */
486 case 0x12: /* vertical display end */
487 s->cr[s->cr_index] = val;
490 s->cr[s->cr_index] = val;
494 switch(s->cr_index) {
502 s->update_retrace_info(s);
513 #ifdef CONFIG_BOCHS_VBE
514 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
516 VGAState *s = opaque;
522 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524 VGAState *s = opaque;
527 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
528 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
529 switch(s->vbe_index) {
530 /* XXX: do not hardcode ? */
531 case VBE_DISPI_INDEX_XRES:
532 val = VBE_DISPI_MAX_XRES;
534 case VBE_DISPI_INDEX_YRES:
535 val = VBE_DISPI_MAX_YRES;
537 case VBE_DISPI_INDEX_BPP:
538 val = VBE_DISPI_MAX_BPP;
541 val = s->vbe_regs[s->vbe_index];
545 val = s->vbe_regs[s->vbe_index];
550 #ifdef DEBUG_BOCHS_VBE
551 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
556 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558 VGAState *s = opaque;
562 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
564 VGAState *s = opaque;
566 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
567 #ifdef DEBUG_BOCHS_VBE
568 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570 switch(s->vbe_index) {
571 case VBE_DISPI_INDEX_ID:
572 if (val == VBE_DISPI_ID0 ||
573 val == VBE_DISPI_ID1 ||
574 val == VBE_DISPI_ID2 ||
575 val == VBE_DISPI_ID3 ||
576 val == VBE_DISPI_ID4) {
577 s->vbe_regs[s->vbe_index] = val;
580 case VBE_DISPI_INDEX_XRES:
581 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
582 s->vbe_regs[s->vbe_index] = val;
585 case VBE_DISPI_INDEX_YRES:
586 if (val <= VBE_DISPI_MAX_YRES) {
587 s->vbe_regs[s->vbe_index] = val;
590 case VBE_DISPI_INDEX_BPP:
593 if (val == 4 || val == 8 || val == 15 ||
594 val == 16 || val == 24 || val == 32) {
595 s->vbe_regs[s->vbe_index] = val;
598 case VBE_DISPI_INDEX_BANK:
599 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
600 val &= (s->vbe_bank_mask >> 2);
602 val &= s->vbe_bank_mask;
604 s->vbe_regs[s->vbe_index] = val;
605 s->bank_offset = (val << 16);
607 case VBE_DISPI_INDEX_ENABLE:
608 if ((val & VBE_DISPI_ENABLED) &&
609 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
610 int h, shift_control;
612 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
613 s->vbe_regs[VBE_DISPI_INDEX_XRES];
614 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
615 s->vbe_regs[VBE_DISPI_INDEX_YRES];
616 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
617 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
619 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
620 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
623 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
624 s->vbe_start_addr = 0;
626 /* clear the screen (should be done in BIOS) */
627 if (!(val & VBE_DISPI_NOCLEARMEM)) {
628 memset(s->vram_ptr, 0,
629 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
632 /* we initialize the VGA graphic mode (should be done
634 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
635 s->cr[0x17] |= 3; /* no CGA modes */
636 s->cr[0x13] = s->vbe_line_offset >> 3;
638 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
639 /* height (only meaningful if < 1024) */
640 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
643 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
644 /* line compare to 1023 */
649 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 s->sr[0x01] &= ~8; /* no double line */
654 s->sr[4] |= 0x08; /* set chain 4 mode */
655 s->sr[2] |= 0x0f; /* activate all planes */
657 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
658 s->cr[0x09] &= ~0x9f; /* no double scan */
660 /* XXX: the bios should do that */
663 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
664 s->vbe_regs[s->vbe_index] = val;
666 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 int w, h, line_offset;
670 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
673 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
674 line_offset = w >> 1;
676 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
677 h = s->vram_size / line_offset;
678 /* XXX: support weird bochs semantics ? */
679 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
683 s->vbe_line_offset = line_offset;
686 case VBE_DISPI_INDEX_X_OFFSET:
687 case VBE_DISPI_INDEX_Y_OFFSET:
690 s->vbe_regs[s->vbe_index] = val;
691 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
692 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
693 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
694 s->vbe_start_addr += x >> 1;
696 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
697 s->vbe_start_addr >>= 2;
707 /* called for accesses between 0xa0000 and 0xc0000 */
708 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
710 VGAState *s = opaque;
711 int memory_map_mode, plane;
714 /* convert to VGA memory offset */
715 memory_map_mode = (s->gr[6] >> 2) & 3;
717 switch(memory_map_mode) {
723 addr += s->bank_offset;
738 if (s->sr[4] & 0x08) {
739 /* chain 4 mode : simplest access */
740 ret = s->vram_ptr[addr];
741 } else if (s->gr[5] & 0x10) {
742 /* odd/even mode (aka text mode mapping) */
743 plane = (s->gr[4] & 2) | (addr & 1);
744 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 /* standard VGA latched access */
747 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749 if (!(s->gr[5] & 0x08)) {
752 ret = GET_PLANE(s->latch, plane);
755 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
764 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
767 #ifdef TARGET_WORDS_BIGENDIAN
768 v = vga_mem_readb(opaque, addr) << 8;
769 v |= vga_mem_readb(opaque, addr + 1);
771 v = vga_mem_readb(opaque, addr);
772 v |= vga_mem_readb(opaque, addr + 1) << 8;
777 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
780 #ifdef TARGET_WORDS_BIGENDIAN
781 v = vga_mem_readb(opaque, addr) << 24;
782 v |= vga_mem_readb(opaque, addr + 1) << 16;
783 v |= vga_mem_readb(opaque, addr + 2) << 8;
784 v |= vga_mem_readb(opaque, addr + 3);
786 v = vga_mem_readb(opaque, addr);
787 v |= vga_mem_readb(opaque, addr + 1) << 8;
788 v |= vga_mem_readb(opaque, addr + 2) << 16;
789 v |= vga_mem_readb(opaque, addr + 3) << 24;
794 /* called for accesses between 0xa0000 and 0xc0000 */
795 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
797 VGAState *s = opaque;
798 int memory_map_mode, plane, write_mode, b, func_select, mask;
799 uint32_t write_mask, bit_mask, set_mask;
802 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804 /* convert to VGA memory offset */
805 memory_map_mode = (s->gr[6] >> 2) & 3;
807 switch(memory_map_mode) {
813 addr += s->bank_offset;
828 if (s->sr[4] & 0x08) {
829 /* chain 4 mode : simplest access */
832 if (s->sr[2] & mask) {
833 s->vram_ptr[addr] = val;
835 printf("vga: chain4: [0x%x]\n", addr);
837 s->plane_updated |= mask; /* only used to detect font change */
838 cpu_physical_memory_set_dirty(s->vram_offset + addr);
840 } else if (s->gr[5] & 0x10) {
841 /* odd/even mode (aka text mode mapping) */
842 plane = (s->gr[4] & 2) | (addr & 1);
844 if (s->sr[2] & mask) {
845 addr = ((addr & ~1) << 1) | plane;
846 s->vram_ptr[addr] = val;
848 printf("vga: odd/even: [0x%x]\n", addr);
850 s->plane_updated |= mask; /* only used to detect font change */
851 cpu_physical_memory_set_dirty(s->vram_offset + addr);
854 /* standard VGA latched access */
855 write_mode = s->gr[5] & 3;
861 val = ((val >> b) | (val << (8 - b))) & 0xff;
865 /* apply set/reset mask */
866 set_mask = mask16[s->gr[1]];
867 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
874 val = mask16[val & 0x0f];
880 val = (val >> b) | (val << (8 - b));
882 bit_mask = s->gr[8] & val;
883 val = mask16[s->gr[0]];
887 /* apply logical operation */
888 func_select = s->gr[3] >> 3;
889 switch(func_select) {
909 bit_mask |= bit_mask << 8;
910 bit_mask |= bit_mask << 16;
911 val = (val & bit_mask) | (s->latch & ~bit_mask);
914 /* mask data according to sr[2] */
916 s->plane_updated |= mask; /* only used to detect font change */
917 write_mask = mask16[mask];
918 ((uint32_t *)s->vram_ptr)[addr] =
919 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
922 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
923 addr * 4, write_mask, val);
925 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
929 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
931 #ifdef TARGET_WORDS_BIGENDIAN
932 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
933 vga_mem_writeb(opaque, addr + 1, val & 0xff);
935 vga_mem_writeb(opaque, addr, val & 0xff);
936 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
940 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 #ifdef TARGET_WORDS_BIGENDIAN
943 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
944 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
945 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
946 vga_mem_writeb(opaque, addr + 3, val & 0xff);
948 vga_mem_writeb(opaque, addr, val & 0xff);
949 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
950 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
951 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
955 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
956 const uint8_t *font_ptr, int h,
957 uint32_t fgcol, uint32_t bgcol);
958 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
959 const uint8_t *font_ptr, int h,
960 uint32_t fgcol, uint32_t bgcol, int dup9);
961 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
962 const uint8_t *s, int width);
965 #include "vga_template.h"
968 #include "vga_template.h"
972 #include "vga_template.h"
975 #include "vga_template.h"
979 #include "vga_template.h"
982 #include "vga_template.h"
986 #include "vga_template.h"
988 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
991 col = rgb_to_pixel8(r, g, b);
997 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1000 col = rgb_to_pixel15(r, g, b);
1005 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1009 col = rgb_to_pixel15bgr(r, g, b);
1014 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1017 col = rgb_to_pixel16(r, g, b);
1022 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1026 col = rgb_to_pixel16bgr(r, g, b);
1031 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1034 col = rgb_to_pixel32(r, g, b);
1038 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1041 col = rgb_to_pixel32bgr(r, g, b);
1045 /* return true if the palette was modified */
1046 static int update_palette16(VGAState *s)
1049 uint32_t v, col, *palette;
1052 palette = s->last_palette;
1053 for(i = 0; i < 16; i++) {
1055 if (s->ar[0x10] & 0x80)
1056 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1061 c6_to_8(s->palette[v + 1]),
1062 c6_to_8(s->palette[v + 2]));
1063 if (col != palette[i]) {
1071 /* return true if the palette was modified */
1072 static int update_palette256(VGAState *s)
1075 uint32_t v, col, *palette;
1078 palette = s->last_palette;
1080 for(i = 0; i < 256; i++) {
1082 col = s->rgb_to_pixel(s->palette[v],
1086 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1087 c6_to_8(s->palette[v + 1]),
1088 c6_to_8(s->palette[v + 2]));
1090 if (col != palette[i]) {
1099 static void vga_get_offsets(VGAState *s,
1100 uint32_t *pline_offset,
1101 uint32_t *pstart_addr,
1102 uint32_t *pline_compare)
1104 uint32_t start_addr, line_offset, line_compare;
1105 #ifdef CONFIG_BOCHS_VBE
1106 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1107 line_offset = s->vbe_line_offset;
1108 start_addr = s->vbe_start_addr;
1109 line_compare = 65535;
1113 /* compute line_offset in bytes */
1114 line_offset = s->cr[0x13];
1117 /* starting address */
1118 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1121 line_compare = s->cr[0x18] |
1122 ((s->cr[0x07] & 0x10) << 4) |
1123 ((s->cr[0x09] & 0x40) << 3);
1125 *pline_offset = line_offset;
1126 *pstart_addr = start_addr;
1127 *pline_compare = line_compare;
1130 /* update start_addr and line_offset. Return TRUE if modified */
1131 static int update_basic_params(VGAState *s)
1134 uint32_t start_addr, line_offset, line_compare;
1138 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1140 if (line_offset != s->line_offset ||
1141 start_addr != s->start_addr ||
1142 line_compare != s->line_compare) {
1143 s->line_offset = line_offset;
1144 s->start_addr = start_addr;
1145 s->line_compare = line_compare;
1153 static inline int get_depth_index(DisplayState *s)
1155 switch(ds_get_bits_per_pixel(s)) {
1164 if (is_surface_bgr(s->surface))
1171 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1181 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1183 vga_draw_glyph16_16,
1184 vga_draw_glyph16_16,
1185 vga_draw_glyph16_32,
1186 vga_draw_glyph16_32,
1187 vga_draw_glyph16_16,
1188 vga_draw_glyph16_16,
1191 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1201 static const uint8_t cursor_glyph[32 * 4] = {
1202 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1203 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1204 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1220 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1221 int *pcwidth, int *pcheight)
1223 int width, cwidth, height, cheight;
1225 /* total width & height */
1226 cheight = (s->cr[9] & 0x1f) + 1;
1228 if (!(s->sr[1] & 0x01))
1230 if (s->sr[1] & 0x08)
1231 cwidth = 16; /* NOTE: no 18 pixel wide */
1232 width = (s->cr[0x01] + 1);
1233 if (s->cr[0x06] == 100) {
1234 /* ugly hack for CGA 160x100x16 - explain me the logic */
1237 height = s->cr[0x12] |
1238 ((s->cr[0x07] & 0x02) << 7) |
1239 ((s->cr[0x07] & 0x40) << 3);
1240 height = (height + 1) / cheight;
1246 *pcheight = cheight;
1249 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1251 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1256 rgb_to_pixel32bgr_dup,
1257 rgb_to_pixel15bgr_dup,
1258 rgb_to_pixel16bgr_dup,
1269 static void vga_draw_text(VGAState *s, int full_update)
1271 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1272 int cx_min, cx_max, linesize, x_incr;
1273 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1274 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1275 const uint8_t *font_ptr, *font_base[2];
1276 int dup9, line_offset, depth_index;
1278 uint32_t *ch_attr_ptr;
1279 vga_draw_glyph8_func *vga_draw_glyph8;
1280 vga_draw_glyph9_func *vga_draw_glyph9;
1282 vga_dirty_log_stop(s);
1284 /* compute font data address (in plane 2) */
1286 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1287 if (offset != s->font_offsets[0]) {
1288 s->font_offsets[0] = offset;
1291 font_base[0] = s->vram_ptr + offset;
1293 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1294 font_base[1] = s->vram_ptr + offset;
1295 if (offset != s->font_offsets[1]) {
1296 s->font_offsets[1] = offset;
1299 if (s->plane_updated & (1 << 2)) {
1300 /* if the plane 2 was modified since the last display, it
1301 indicates the font may have been modified */
1302 s->plane_updated = 0;
1305 full_update |= update_basic_params(s);
1307 line_offset = s->line_offset;
1308 s1 = s->vram_ptr + (s->start_addr * 4);
1310 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1311 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1312 if ((height * width) > CH_ATTR_SIZE) {
1313 /* better than nothing: exit if transient size is too big */
1317 if (width != s->last_width || height != s->last_height ||
1318 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1319 s->last_scr_width = width * cw;
1320 s->last_scr_height = height * cheight;
1321 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1323 s->last_width = width;
1324 s->last_height = height;
1325 s->last_ch = cheight;
1330 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1331 full_update |= update_palette16(s);
1332 palette = s->last_palette;
1333 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1335 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1336 if (cursor_offset != s->cursor_offset ||
1337 s->cr[0xa] != s->cursor_start ||
1338 s->cr[0xb] != s->cursor_end) {
1339 /* if the cursor position changed, we update the old and new
1341 if (s->cursor_offset < CH_ATTR_SIZE)
1342 s->last_ch_attr[s->cursor_offset] = -1;
1343 if (cursor_offset < CH_ATTR_SIZE)
1344 s->last_ch_attr[cursor_offset] = -1;
1345 s->cursor_offset = cursor_offset;
1346 s->cursor_start = s->cr[0xa];
1347 s->cursor_end = s->cr[0xb];
1349 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1351 depth_index = get_depth_index(s->ds);
1353 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1355 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1356 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1358 dest = ds_get_data(s->ds);
1359 linesize = ds_get_linesize(s->ds);
1360 ch_attr_ptr = s->last_ch_attr;
1361 for(cy = 0; cy < height; cy++) {
1366 for(cx = 0; cx < width; cx++) {
1367 ch_attr = *(uint16_t *)src;
1368 if (full_update || ch_attr != *ch_attr_ptr) {
1373 *ch_attr_ptr = ch_attr;
1374 #ifdef WORDS_BIGENDIAN
1376 cattr = ch_attr & 0xff;
1378 ch = ch_attr & 0xff;
1379 cattr = ch_attr >> 8;
1381 font_ptr = font_base[(cattr >> 3) & 1];
1382 font_ptr += 32 * 4 * ch;
1383 bgcol = palette[cattr >> 4];
1384 fgcol = palette[cattr & 0x0f];
1386 vga_draw_glyph8(d1, linesize,
1387 font_ptr, cheight, fgcol, bgcol);
1390 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1392 vga_draw_glyph9(d1, linesize,
1393 font_ptr, cheight, fgcol, bgcol, dup9);
1395 if (src == cursor_ptr &&
1396 !(s->cr[0x0a] & 0x20)) {
1397 int line_start, line_last, h;
1398 /* draw the cursor */
1399 line_start = s->cr[0x0a] & 0x1f;
1400 line_last = s->cr[0x0b] & 0x1f;
1401 /* XXX: check that */
1402 if (line_last > cheight - 1)
1403 line_last = cheight - 1;
1404 if (line_last >= line_start && line_start < cheight) {
1405 h = line_last - line_start + 1;
1406 d = d1 + linesize * line_start;
1408 vga_draw_glyph8(d, linesize,
1409 cursor_glyph, h, fgcol, bgcol);
1411 vga_draw_glyph9(d, linesize,
1412 cursor_glyph, h, fgcol, bgcol, 1);
1422 dpy_update(s->ds, cx_min * cw, cy * cheight,
1423 (cx_max - cx_min + 1) * cw, cheight);
1425 dest += linesize * cheight;
1444 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1454 vga_draw_line2d2_16,
1455 vga_draw_line2d2_16,
1456 vga_draw_line2d2_32,
1457 vga_draw_line2d2_32,
1458 vga_draw_line2d2_16,
1459 vga_draw_line2d2_16,
1470 vga_draw_line4d2_16,
1471 vga_draw_line4d2_16,
1472 vga_draw_line4d2_32,
1473 vga_draw_line4d2_32,
1474 vga_draw_line4d2_16,
1475 vga_draw_line4d2_16,
1478 vga_draw_line8d2_16,
1479 vga_draw_line8d2_16,
1480 vga_draw_line8d2_32,
1481 vga_draw_line8d2_32,
1482 vga_draw_line8d2_16,
1483 vga_draw_line8d2_16,
1497 vga_draw_line15_32bgr,
1498 vga_draw_line15_15bgr,
1499 vga_draw_line15_16bgr,
1505 vga_draw_line16_32bgr,
1506 vga_draw_line16_15bgr,
1507 vga_draw_line16_16bgr,
1513 vga_draw_line24_32bgr,
1514 vga_draw_line24_15bgr,
1515 vga_draw_line24_16bgr,
1521 vga_draw_line32_32bgr,
1522 vga_draw_line32_15bgr,
1523 vga_draw_line32_16bgr,
1526 static int vga_get_bpp(VGAState *s)
1529 #ifdef CONFIG_BOCHS_VBE
1530 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1531 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1540 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1544 #ifdef CONFIG_BOCHS_VBE
1545 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1546 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1547 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1551 width = (s->cr[0x01] + 1) * 8;
1552 height = s->cr[0x12] |
1553 ((s->cr[0x07] & 0x02) << 7) |
1554 ((s->cr[0x07] & 0x40) << 3);
1555 height = (height + 1);
1561 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1564 if (y1 >= VGA_MAX_HEIGHT)
1566 if (y2 >= VGA_MAX_HEIGHT)
1567 y2 = VGA_MAX_HEIGHT;
1568 for(y = y1; y < y2; y++) {
1569 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1573 static void vga_sync_dirty_bitmap(VGAState *s)
1576 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1578 if (s->lfb_vram_mapped) {
1579 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1580 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1582 vga_dirty_log_start(s);
1588 static void vga_draw_graphic(VGAState *s, int full_update)
1590 int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask, depth;
1591 int width, height, shift_control, line_offset, page0, page1, bwidth, bits;
1592 int disp_width, multi_scan, multi_run;
1594 uint32_t v, addr1, addr;
1595 vga_draw_line_func *vga_draw_line;
1597 full_update |= update_basic_params(s);
1600 vga_sync_dirty_bitmap(s);
1602 s->get_resolution(s, &width, &height);
1605 shift_control = (s->gr[0x05] >> 5) & 3;
1606 double_scan = (s->cr[0x09] >> 7);
1607 if (shift_control != 1) {
1608 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1610 /* in CGA modes, multi_scan is ignored */
1611 /* XXX: is it correct ? */
1612 multi_scan = double_scan;
1614 multi_run = multi_scan;
1615 if (shift_control != s->shift_control ||
1616 double_scan != s->double_scan) {
1618 s->shift_control = shift_control;
1619 s->double_scan = double_scan;
1622 depth = s->get_bpp(s);
1623 if (s->line_offset != s->last_line_offset ||
1624 disp_width != s->last_width ||
1625 height != s->last_height ||
1626 s->last_depth != depth) {
1627 #if defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1628 if (depth == 16 || depth == 32) {
1632 if (is_graphic_console()) {
1633 qemu_free_displaysurface(s->ds);
1634 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1636 s->vram_ptr + (s->start_addr * 4));
1637 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1638 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1642 qemu_console_resize(s->ds, disp_width, height);
1645 qemu_console_resize(s->ds, disp_width, height);
1647 s->last_scr_width = disp_width;
1648 s->last_scr_height = height;
1649 s->last_width = disp_width;
1650 s->last_height = height;
1651 s->last_line_offset = s->line_offset;
1652 s->last_depth = depth;
1654 } else if (is_graphic_console() && is_buffer_shared(s->ds->surface) &&
1655 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1656 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1661 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1663 if (shift_control == 0) {
1664 full_update |= update_palette16(s);
1665 if (s->sr[0x01] & 8) {
1666 v = VGA_DRAW_LINE4D2;
1672 } else if (shift_control == 1) {
1673 full_update |= update_palette16(s);
1674 if (s->sr[0x01] & 8) {
1675 v = VGA_DRAW_LINE2D2;
1682 switch(s->get_bpp(s)) {
1685 full_update |= update_palette256(s);
1686 v = VGA_DRAW_LINE8D2;
1690 full_update |= update_palette256(s);
1695 v = VGA_DRAW_LINE15;
1699 v = VGA_DRAW_LINE16;
1703 v = VGA_DRAW_LINE24;
1707 v = VGA_DRAW_LINE32;
1712 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1714 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1715 s->cursor_invalidate(s);
1717 line_offset = s->line_offset;
1719 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1720 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1722 addr1 = (s->start_addr * 4);
1723 bwidth = (width * bits + 7) / 8;
1725 page_min = 0x7fffffff;
1727 d = ds_get_data(s->ds);
1728 linesize = ds_get_linesize(s->ds);
1730 for(y = 0; y < height; y++) {
1732 if (!(s->cr[0x17] & 1)) {
1734 /* CGA compatibility handling */
1735 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1736 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1738 if (!(s->cr[0x17] & 2)) {
1739 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1741 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1742 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1743 update = full_update |
1744 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1745 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1746 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1747 /* if wide line, can use another page */
1748 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1751 /* explicit invalidation for the hardware cursor */
1752 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1756 if (page0 < page_min)
1758 if (page1 > page_max)
1760 if (!(is_buffer_shared(s->ds->surface))) {
1761 vga_draw_line(s, d, s->vram_ptr + addr, width);
1762 if (s->cursor_draw_line)
1763 s->cursor_draw_line(s, d, y);
1767 /* flush to display */
1768 dpy_update(s->ds, 0, y_start,
1769 disp_width, y - y_start);
1774 mask = (s->cr[0x17] & 3) ^ 3;
1775 if ((y1 & mask) == mask)
1776 addr1 += line_offset;
1778 multi_run = multi_scan;
1782 /* line compare acts on the displayed lines */
1783 if (y == s->line_compare)
1788 /* flush to display */
1789 dpy_update(s->ds, 0, y_start,
1790 disp_width, y - y_start);
1792 /* reset modified pages */
1793 if (page_max != -1) {
1794 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1797 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1800 static void vga_draw_blank(VGAState *s, int full_update)
1807 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1809 vga_dirty_log_stop(s);
1812 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1813 if (ds_get_bits_per_pixel(s->ds) == 8)
1814 val = s->rgb_to_pixel(0, 0, 0);
1817 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1818 d = ds_get_data(s->ds);
1819 for(i = 0; i < s->last_scr_height; i++) {
1821 d += ds_get_linesize(s->ds);
1823 dpy_update(s->ds, 0, 0,
1824 s->last_scr_width, s->last_scr_height);
1827 #define GMODE_TEXT 0
1828 #define GMODE_GRAPH 1
1829 #define GMODE_BLANK 2
1831 static void vga_update_display(void *opaque)
1833 VGAState *s = (VGAState *)opaque;
1834 int full_update, graphic_mode;
1836 if (ds_get_bits_per_pixel(s->ds) == 0) {
1840 if (!(s->ar_index & 0x20)) {
1841 graphic_mode = GMODE_BLANK;
1843 graphic_mode = s->gr[6] & 1;
1845 if (graphic_mode != s->graphic_mode) {
1846 s->graphic_mode = graphic_mode;
1849 switch(graphic_mode) {
1851 vga_draw_text(s, full_update);
1854 vga_draw_graphic(s, full_update);
1858 vga_draw_blank(s, full_update);
1864 /* force a full display refresh */
1865 static void vga_invalidate_display(void *opaque)
1867 VGAState *s = (VGAState *)opaque;
1870 s->last_height = -1;
1873 void vga_reset(void *opaque)
1875 VGAState *s = (VGAState *) opaque;
1881 s->lfb_vram_mapped = 0;
1885 memset(s->sr, '\0', sizeof(s->sr));
1887 memset(s->gr, '\0', sizeof(s->gr));
1889 memset(s->ar, '\0', sizeof(s->ar));
1890 s->ar_flip_flop = 0;
1892 memset(s->cr, '\0', sizeof(s->cr));
1898 s->dac_sub_index = 0;
1899 s->dac_read_index = 0;
1900 s->dac_write_index = 0;
1901 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1903 memset(s->palette, '\0', sizeof(s->palette));
1905 #ifdef CONFIG_BOCHS_VBE
1907 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1908 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1909 s->vbe_start_addr = 0;
1910 s->vbe_line_offset = 0;
1911 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1913 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1914 s->graphic_mode = -1; /* force full update */
1915 s->shift_control = 0;
1918 s->line_compare = 0;
1920 s->plane_updated = 0;
1925 s->last_scr_width = 0;
1926 s->last_scr_height = 0;
1927 s->cursor_start = 0;
1929 s->cursor_offset = 0;
1930 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1931 memset(s->last_palette, '\0', sizeof(s->last_palette));
1932 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1933 switch (vga_retrace_method) {
1934 case VGA_RETRACE_DUMB:
1936 case VGA_RETRACE_PRECISE:
1937 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1942 #define TEXTMODE_X(x) ((x) % width)
1943 #define TEXTMODE_Y(x) ((x) / width)
1944 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1945 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1946 /* relay text rendering to the display driver
1947 * instead of doing a full vga_update_display() */
1948 static void vga_update_text(void *opaque, console_ch_t *chardata)
1950 VGAState *s = (VGAState *) opaque;
1951 int graphic_mode, i, cursor_offset, cursor_visible;
1952 int cw, cheight, width, height, size, c_min, c_max;
1954 console_ch_t *dst, val;
1955 char msg_buffer[80];
1956 int full_update = 0;
1958 if (!(s->ar_index & 0x20)) {
1959 graphic_mode = GMODE_BLANK;
1961 graphic_mode = s->gr[6] & 1;
1963 if (graphic_mode != s->graphic_mode) {
1964 s->graphic_mode = graphic_mode;
1967 if (s->last_width == -1) {
1972 switch (graphic_mode) {
1974 /* TODO: update palette */
1975 full_update |= update_basic_params(s);
1977 /* total width & height */
1978 cheight = (s->cr[9] & 0x1f) + 1;
1980 if (!(s->sr[1] & 0x01))
1982 if (s->sr[1] & 0x08)
1983 cw = 16; /* NOTE: no 18 pixel wide */
1984 width = (s->cr[0x01] + 1);
1985 if (s->cr[0x06] == 100) {
1986 /* ugly hack for CGA 160x100x16 - explain me the logic */
1989 height = s->cr[0x12] |
1990 ((s->cr[0x07] & 0x02) << 7) |
1991 ((s->cr[0x07] & 0x40) << 3);
1992 height = (height + 1) / cheight;
1995 size = (height * width);
1996 if (size > CH_ATTR_SIZE) {
2000 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2005 if (width != s->last_width || height != s->last_height ||
2006 cw != s->last_cw || cheight != s->last_ch) {
2007 s->last_scr_width = width * cw;
2008 s->last_scr_height = height * cheight;
2009 s->ds->surface->width = width;
2010 s->ds->surface->height = height;
2012 s->last_width = width;
2013 s->last_height = height;
2014 s->last_ch = cheight;
2019 /* Update "hardware" cursor */
2020 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
2021 if (cursor_offset != s->cursor_offset ||
2022 s->cr[0xa] != s->cursor_start ||
2023 s->cr[0xb] != s->cursor_end || full_update) {
2024 cursor_visible = !(s->cr[0xa] & 0x20);
2025 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2027 TEXTMODE_X(cursor_offset),
2028 TEXTMODE_Y(cursor_offset));
2030 dpy_cursor(s->ds, -1, -1);
2031 s->cursor_offset = cursor_offset;
2032 s->cursor_start = s->cr[0xa];
2033 s->cursor_end = s->cr[0xb];
2036 src = (uint32_t *) s->vram_ptr + s->start_addr;
2040 for (i = 0; i < size; src ++, dst ++, i ++)
2041 console_write_ch(dst, VMEM2CHTYPE(*src));
2043 dpy_update(s->ds, 0, 0, width, height);
2047 for (i = 0; i < size; src ++, dst ++, i ++) {
2048 console_write_ch(&val, VMEM2CHTYPE(*src));
2056 for (; i < size; src ++, dst ++, i ++) {
2057 console_write_ch(&val, VMEM2CHTYPE(*src));
2064 if (c_min <= c_max) {
2065 i = TEXTMODE_Y(c_min);
2066 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2075 s->get_resolution(s, &width, &height);
2076 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2084 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2088 /* Display a message */
2090 s->last_height = height = 3;
2091 dpy_cursor(s->ds, -1, -1);
2092 s->ds->surface->width = s->last_width;
2093 s->ds->surface->height = height;
2096 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2097 console_write_ch(dst ++, ' ');
2099 size = strlen(msg_buffer);
2100 width = (s->last_width - size) / 2;
2101 dst = chardata + s->last_width + width;
2102 for (i = 0; i < size; i ++)
2103 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2105 dpy_update(s->ds, 0, 0, s->last_width, height);
2108 static CPUReadMemoryFunc *vga_mem_read[3] = {
2114 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2120 static void vga_save(QEMUFile *f, void *opaque)
2122 VGAState *s = opaque;
2126 pci_device_save(s->pci_dev, f);
2128 qemu_put_be32s(f, &s->latch);
2129 qemu_put_8s(f, &s->sr_index);
2130 qemu_put_buffer(f, s->sr, 8);
2131 qemu_put_8s(f, &s->gr_index);
2132 qemu_put_buffer(f, s->gr, 16);
2133 qemu_put_8s(f, &s->ar_index);
2134 qemu_put_buffer(f, s->ar, 21);
2135 qemu_put_be32(f, s->ar_flip_flop);
2136 qemu_put_8s(f, &s->cr_index);
2137 qemu_put_buffer(f, s->cr, 256);
2138 qemu_put_8s(f, &s->msr);
2139 qemu_put_8s(f, &s->fcr);
2140 qemu_put_byte(f, s->st00);
2141 qemu_put_8s(f, &s->st01);
2143 qemu_put_8s(f, &s->dac_state);
2144 qemu_put_8s(f, &s->dac_sub_index);
2145 qemu_put_8s(f, &s->dac_read_index);
2146 qemu_put_8s(f, &s->dac_write_index);
2147 qemu_put_buffer(f, s->dac_cache, 3);
2148 qemu_put_buffer(f, s->palette, 768);
2150 qemu_put_be32(f, s->bank_offset);
2151 #ifdef CONFIG_BOCHS_VBE
2152 qemu_put_byte(f, 1);
2153 qemu_put_be16s(f, &s->vbe_index);
2154 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2155 qemu_put_be16s(f, &s->vbe_regs[i]);
2156 qemu_put_be32s(f, &s->vbe_start_addr);
2157 qemu_put_be32s(f, &s->vbe_line_offset);
2158 qemu_put_be32s(f, &s->vbe_bank_mask);
2160 qemu_put_byte(f, 0);
2164 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2166 VGAState *s = opaque;
2172 if (s->pci_dev && version_id >= 2) {
2173 ret = pci_device_load(s->pci_dev, f);
2178 qemu_get_be32s(f, &s->latch);
2179 qemu_get_8s(f, &s->sr_index);
2180 qemu_get_buffer(f, s->sr, 8);
2181 qemu_get_8s(f, &s->gr_index);
2182 qemu_get_buffer(f, s->gr, 16);
2183 qemu_get_8s(f, &s->ar_index);
2184 qemu_get_buffer(f, s->ar, 21);
2185 s->ar_flip_flop=qemu_get_be32(f);
2186 qemu_get_8s(f, &s->cr_index);
2187 qemu_get_buffer(f, s->cr, 256);
2188 qemu_get_8s(f, &s->msr);
2189 qemu_get_8s(f, &s->fcr);
2190 qemu_get_8s(f, &s->st00);
2191 qemu_get_8s(f, &s->st01);
2193 qemu_get_8s(f, &s->dac_state);
2194 qemu_get_8s(f, &s->dac_sub_index);
2195 qemu_get_8s(f, &s->dac_read_index);
2196 qemu_get_8s(f, &s->dac_write_index);
2197 qemu_get_buffer(f, s->dac_cache, 3);
2198 qemu_get_buffer(f, s->palette, 768);
2200 s->bank_offset=qemu_get_be32(f);
2201 is_vbe = qemu_get_byte(f);
2202 #ifdef CONFIG_BOCHS_VBE
2205 qemu_get_be16s(f, &s->vbe_index);
2206 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2207 qemu_get_be16s(f, &s->vbe_regs[i]);
2208 qemu_get_be32s(f, &s->vbe_start_addr);
2209 qemu_get_be32s(f, &s->vbe_line_offset);
2210 qemu_get_be32s(f, &s->vbe_bank_mask);
2217 s->graphic_mode = -1;
2221 typedef struct PCIVGAState {
2226 void vga_dirty_log_start(VGAState *s)
2228 if (kvm_enabled() && s->map_addr)
2229 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2231 if (kvm_enabled() && s->lfb_vram_mapped) {
2232 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2233 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2237 void vga_dirty_log_stop(VGAState *s)
2239 if (kvm_enabled() && s->map_addr)
2240 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2242 if (kvm_enabled() && s->lfb_vram_mapped) {
2243 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2244 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2248 static void vga_map(PCIDevice *pci_dev, int region_num,
2249 uint32_t addr, uint32_t size, int type)
2251 PCIVGAState *d = (PCIVGAState *)pci_dev;
2252 VGAState *s = &d->vga_state;
2253 if (region_num == PCI_ROM_SLOT) {
2254 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2256 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2260 s->map_end = addr + VGA_RAM_SIZE;
2262 vga_dirty_log_start(s);
2265 void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
2266 ram_addr_t vga_ram_offset, int vga_ram_size)
2270 for(i = 0;i < 256; i++) {
2272 for(j = 0; j < 8; j++) {
2273 v |= ((i >> j) & 1) << (j * 4);
2278 for(j = 0; j < 4; j++) {
2279 v |= ((i >> (2 * j)) & 3) << (j * 4);
2283 for(i = 0; i < 16; i++) {
2285 for(j = 0; j < 4; j++) {
2288 v |= b << (2 * j + 1);
2293 s->vram_ptr = vga_ram_base;
2294 s->vram_offset = vga_ram_offset;
2295 s->vram_size = vga_ram_size;
2296 s->get_bpp = vga_get_bpp;
2297 s->get_offsets = vga_get_offsets;
2298 s->get_resolution = vga_get_resolution;
2299 s->update = vga_update_display;
2300 s->invalidate = vga_invalidate_display;
2301 s->screen_dump = vga_screen_dump;
2302 s->text_update = vga_update_text;
2303 switch (vga_retrace_method) {
2304 case VGA_RETRACE_DUMB:
2305 s->retrace = vga_dumb_retrace;
2306 s->update_retrace_info = vga_dumb_update_retrace_info;
2309 case VGA_RETRACE_PRECISE:
2310 s->retrace = vga_precise_retrace;
2311 s->update_retrace_info = vga_precise_update_retrace_info;
2317 /* used by both ISA and PCI */
2318 void vga_init(VGAState *s)
2322 qemu_register_reset(vga_reset, s);
2323 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2325 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2327 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2328 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2329 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2330 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2332 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2334 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2335 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2336 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2337 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2340 #ifdef CONFIG_BOCHS_VBE
2341 #if defined (TARGET_I386)
2342 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2343 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2345 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2346 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2348 /* old Bochs IO ports */
2349 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2350 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2352 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2353 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2355 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2356 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2358 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2359 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2361 #endif /* CONFIG_BOCHS_VBE */
2363 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2364 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2366 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2369 /* Memory mapped interface */
2370 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2372 VGAState *s = opaque;
2374 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2377 static void vga_mm_writeb (void *opaque,
2378 target_phys_addr_t addr, uint32_t value)
2380 VGAState *s = opaque;
2382 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2385 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2387 VGAState *s = opaque;
2389 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2392 static void vga_mm_writew (void *opaque,
2393 target_phys_addr_t addr, uint32_t value)
2395 VGAState *s = opaque;
2397 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2400 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2402 VGAState *s = opaque;
2404 return vga_ioport_read(s, addr >> s->it_shift);
2407 static void vga_mm_writel (void *opaque,
2408 target_phys_addr_t addr, uint32_t value)
2410 VGAState *s = opaque;
2412 vga_ioport_write(s, addr >> s->it_shift, value);
2415 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2421 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2427 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2428 target_phys_addr_t ctrl_base, int it_shift)
2430 int s_ioport_ctrl, vga_io_memory;
2432 s->it_shift = it_shift;
2433 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2434 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2436 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2438 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2440 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2441 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2444 int isa_vga_init(uint8_t *vga_ram_base,
2445 unsigned long vga_ram_offset, int vga_ram_size)
2449 s = qemu_mallocz(sizeof(VGAState));
2451 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2454 s->ds = graphic_console_init(s->update, s->invalidate,
2455 s->screen_dump, s->text_update, s);
2457 #ifdef CONFIG_BOCHS_VBE
2458 /* XXX: use optimized standard vga accesses */
2459 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2460 vga_ram_size, vga_ram_offset);
2465 int isa_vga_mm_init(uint8_t *vga_ram_base,
2466 unsigned long vga_ram_offset, int vga_ram_size,
2467 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2472 s = qemu_mallocz(sizeof(VGAState));
2474 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2475 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2477 s->ds = graphic_console_init(s->update, s->invalidate,
2478 s->screen_dump, s->text_update, s);
2480 #ifdef CONFIG_BOCHS_VBE
2481 /* XXX: use optimized standard vga accesses */
2482 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2483 vga_ram_size, vga_ram_offset);
2488 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
2489 unsigned long vga_ram_offset, int vga_ram_size,
2490 unsigned long vga_bios_offset, int vga_bios_size)
2496 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2497 sizeof(PCIVGAState),
2503 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2506 s->ds = graphic_console_init(s->update, s->invalidate,
2507 s->screen_dump, s->text_update, s);
2509 s->pci_dev = &d->dev;
2511 pci_conf = d->dev.config;
2512 // dummy VGA (same as Bochs ID)
2513 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2514 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2515 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2516 pci_conf[0x0e] = 0x00; // header_type
2518 /* XXX: vga_ram_size must be a power of two */
2519 pci_register_io_region(&d->dev, 0, vga_ram_size,
2520 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2521 if (vga_bios_size != 0) {
2522 unsigned int bios_total_size;
2523 s->bios_offset = vga_bios_offset;
2524 s->bios_size = vga_bios_size;
2525 /* must be a power of two */
2526 bios_total_size = 1;
2527 while (bios_total_size < vga_bios_size)
2528 bios_total_size <<= 1;
2529 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2530 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2535 /********************************************************/
2536 /* vga screen dump */
2538 static void vga_save_dpy_update(DisplayState *s,
2539 int x, int y, int w, int h)
2543 static void vga_save_dpy_resize(DisplayState *s)
2547 static void vga_save_dpy_refresh(DisplayState *s)
2551 int ppm_save(const char *filename, struct DisplaySurface *ds)
2559 f = fopen(filename, "wb");
2562 fprintf(f, "P6\n%d %d\n%d\n",
2563 ds->width, ds->height, 255);
2565 for(y = 0; y < ds->height; y++) {
2567 for(x = 0; x < ds->width; x++) {
2568 if (ds->pf.bits_per_pixel == 32)
2571 v = (uint32_t) (*(uint16_t *)d);
2572 r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2574 g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2576 b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2581 d += ds->pf.bytes_per_pixel;
2589 static void vga_screen_dump_blank(VGAState *s, const char *filename)
2592 unsigned int y, x, w, h;
2594 w = s->last_scr_width * sizeof(uint32_t);
2595 h = s->last_scr_height;
2597 f = fopen(filename, "wb");
2600 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
2601 for (y = 0; y < h; y++) {
2602 for (x = 0; x < w; x++) {
2609 static void vga_screen_dump_common(VGAState *s, const char *filename,
2612 DisplayState *saved_ds, ds1, *ds = &ds1;
2613 DisplayChangeListener dcl;
2615 /* XXX: this is a little hackish */
2616 vga_invalidate_display(s);
2619 memset(ds, 0, sizeof(DisplayState));
2620 memset(&dcl, 0, sizeof(DisplayChangeListener));
2621 dcl.dpy_update = vga_save_dpy_update;
2622 dcl.dpy_resize = vga_save_dpy_resize;
2623 dcl.dpy_refresh = vga_save_dpy_refresh;
2624 register_displaychangelistener(ds, &dcl);
2625 ds->surface = qemu_create_displaysurface(ds, w, h);
2628 s->graphic_mode = -1;
2629 vga_update_display(s);
2631 ppm_save(filename, ds->surface);
2633 qemu_free_displaysurface(ds);
2637 static void vga_screen_dump_graphic(VGAState *s, const char *filename)
2641 s->get_resolution(s, &w, &h);
2642 vga_screen_dump_common(s, filename, w, h);
2645 static void vga_screen_dump_text(VGAState *s, const char *filename)
2647 int w, h, cwidth, cheight;
2649 vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
2650 vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
2653 /* save the vga display in a PPM image even if no display is
2655 static void vga_screen_dump(void *opaque, const char *filename)
2657 VGAState *s = (VGAState *)opaque;
2659 if (!(s->ar_index & 0x20))
2660 vga_screen_dump_blank(s, filename);
2661 else if (s->gr[6] & 1)
2662 vga_screen_dump_graphic(s, filename);
2664 vga_screen_dump_text(s, filename);