2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 #define HW_MOUSE_ACCEL
39 struct vmsvga_state_s {
79 struct __attribute__((__packed__)) {
84 /* Add registers here when adding capabilities. */
89 #define REDRAW_FIFO_LEN 512
90 struct vmsvga_rect_s {
92 } redraw_fifo[REDRAW_FIFO_LEN];
93 int redraw_fifo_first, redraw_fifo_last;
96 struct pci_vmsvga_state_s {
98 struct vmsvga_state_s chip;
101 #define SVGA_MAGIC 0x900000UL
102 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
103 #define SVGA_ID_0 SVGA_MAKE_ID(0)
104 #define SVGA_ID_1 SVGA_MAKE_ID(1)
105 #define SVGA_ID_2 SVGA_MAKE_ID(2)
107 #define SVGA_LEGACY_BASE_PORT 0x4560
108 #define SVGA_INDEX_PORT 0x0
109 #define SVGA_VALUE_PORT 0x1
110 #define SVGA_BIOS_PORT 0x2
112 #define SVGA_VERSION_2
114 #ifdef SVGA_VERSION_2
115 # define SVGA_ID SVGA_ID_2
116 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
117 # define SVGA_IO_MUL 1
118 # define SVGA_FIFO_SIZE 0x10000
119 # define SVGA_MEM_BASE 0xe0000000
120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
122 # define SVGA_ID SVGA_ID_1
123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
124 # define SVGA_IO_MUL 4
125 # define SVGA_FIFO_SIZE 0x10000
126 # define SVGA_MEM_BASE 0xe0000000
127 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
131 /* ID 0, 1 and 2 registers */
136 SVGA_REG_MAX_WIDTH = 4,
137 SVGA_REG_MAX_HEIGHT = 5,
139 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
140 SVGA_REG_PSEUDOCOLOR = 8,
141 SVGA_REG_RED_MASK = 9,
142 SVGA_REG_GREEN_MASK = 10,
143 SVGA_REG_BLUE_MASK = 11,
144 SVGA_REG_BYTES_PER_LINE = 12,
145 SVGA_REG_FB_START = 13,
146 SVGA_REG_FB_OFFSET = 14,
147 SVGA_REG_VRAM_SIZE = 15,
148 SVGA_REG_FB_SIZE = 16,
150 /* ID 1 and 2 registers */
151 SVGA_REG_CAPABILITIES = 17,
152 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
153 SVGA_REG_MEM_SIZE = 19,
154 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
155 SVGA_REG_SYNC = 21, /* Write to force synchronization */
156 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
157 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
158 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
159 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
160 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
161 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
162 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
163 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
164 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
165 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
166 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
168 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
169 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
170 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
173 #define SVGA_CAP_NONE 0
174 #define SVGA_CAP_RECT_FILL (1 << 0)
175 #define SVGA_CAP_RECT_COPY (1 << 1)
176 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
177 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
178 #define SVGA_CAP_RASTER_OP (1 << 4)
179 #define SVGA_CAP_CURSOR (1 << 5)
180 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
181 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
182 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
183 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
184 #define SVGA_CAP_GLYPH (1 << 10)
185 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
186 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
187 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
188 #define SVGA_CAP_3D (1 << 14)
189 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
190 #define SVGA_CAP_MULTIMON (1 << 16)
191 #define SVGA_CAP_PITCHLOCK (1 << 17)
194 * FIFO offsets (seen as an array of 32-bit words)
198 * The original defined FIFO offsets
201 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
206 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
208 SVGA_FIFO_CAPABILITIES = 4,
211 SVGA_FIFO_3D_HWVERSION,
215 #define SVGA_FIFO_CAP_NONE 0
216 #define SVGA_FIFO_CAP_FENCE (1 << 0)
217 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
218 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
220 #define SVGA_FIFO_FLAG_NONE 0
221 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
223 /* These values can probably be changed arbitrarily. */
224 #define SVGA_SCRATCH_SIZE 0x8000
225 #define SVGA_MAX_WIDTH 2360
226 #define SVGA_MAX_HEIGHT 1770
229 # define GUEST_OS_BASE 0x5001
230 static const char *vmsvga_guest_id[] = {
231 [0x00 ... 0x15] = "an unknown OS",
233 [0x01] = "Windows 3.1",
234 [0x02] = "Windows 95",
235 [0x03] = "Windows 98",
236 [0x04] = "Windows ME",
237 [0x05] = "Windows NT",
238 [0x06] = "Windows 2000",
243 [0x15] = "Windows 2003",
248 SVGA_CMD_INVALID_CMD = 0,
250 SVGA_CMD_RECT_FILL = 2,
251 SVGA_CMD_RECT_COPY = 3,
252 SVGA_CMD_DEFINE_BITMAP = 4,
253 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
254 SVGA_CMD_DEFINE_PIXMAP = 6,
255 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
256 SVGA_CMD_RECT_BITMAP_FILL = 8,
257 SVGA_CMD_RECT_PIXMAP_FILL = 9,
258 SVGA_CMD_RECT_BITMAP_COPY = 10,
259 SVGA_CMD_RECT_PIXMAP_COPY = 11,
260 SVGA_CMD_FREE_OBJECT = 12,
261 SVGA_CMD_RECT_ROP_FILL = 13,
262 SVGA_CMD_RECT_ROP_COPY = 14,
263 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
264 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
265 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
266 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
267 SVGA_CMD_DEFINE_CURSOR = 19,
268 SVGA_CMD_DISPLAY_CURSOR = 20,
269 SVGA_CMD_MOVE_CURSOR = 21,
270 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
271 SVGA_CMD_DRAW_GLYPH = 23,
272 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
273 SVGA_CMD_UPDATE_VERBOSE = 25,
274 SVGA_CMD_SURFACE_FILL = 26,
275 SVGA_CMD_SURFACE_COPY = 27,
276 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
277 SVGA_CMD_FRONT_ROP_FILL = 29,
281 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
283 SVGA_CURSOR_ON_HIDE = 0,
284 SVGA_CURSOR_ON_SHOW = 1,
285 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
286 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
289 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
290 int x, int y, int w, int h)
294 int bypl = s->bypp * s->width;
295 int width = s->bypp * w;
296 int start = s->bypp * x + bypl * y;
297 uint8_t *src = s->vram + start;
298 uint8_t *dst = s->ds->data + start;
300 for (; line > 0; line --, src += bypl, dst += bypl)
301 memcpy(dst, src, width);
304 dpy_update(s->ds, x, y, w, h);
307 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
310 memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
313 dpy_update(s->ds, 0, 0, s->width, s->height);
317 # define vmsvga_update_rect_delayed vmsvga_update_rect
319 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
320 int x, int y, int w, int h)
322 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
323 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
331 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
333 struct vmsvga_rect_s *rect;
334 if (s->invalidated) {
335 s->redraw_fifo_first = s->redraw_fifo_last;
338 /* Overlapping region updates can be optimised out here - if someone
339 * knows a smart algorithm to do that, please share. */
340 while (s->redraw_fifo_first != s->redraw_fifo_last) {
341 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
342 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
343 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
348 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
349 int x0, int y0, int x1, int y1, int w, int h)
352 uint8_t *vram = s->ds->data;
354 uint8_t *vram = s->vram;
356 int bypl = s->bypp * s->width;
357 int width = s->bypp * w;
363 s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
368 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
369 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
370 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
371 memmove(ptr[1], ptr[0], width);
373 ptr[0] = vram + s->bypp * x0 + bypl * y0;
374 ptr[1] = vram + s->bypp * x1 + bypl * y1;
375 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
376 memmove(ptr[1], ptr[0], width);
380 vmsvga_update_rect_delayed(s, x1, y1, w, h);
385 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
386 uint32_t c, int x, int y, int w, int h)
389 uint8_t *vram = s->ds->data;
391 uint8_t *vram = s->vram;
394 int bypl = bypp * s->width;
395 int width = bypp * w;
398 uint8_t *fst = vram + bypp * x + bypl * y;
405 s->ds->dpy_fill(s->ds, x, y, w, h, c);
417 for (column = width; column > 0; column --) {
418 *(dst ++) = *(src ++);
419 if (src - col == bypp)
423 for (; line > 0; line --) {
425 memcpy(dst, fst, width);
430 vmsvga_update_rect_delayed(s, x, y, w, h);
434 struct vmsvga_cursor_definition_s {
442 uint32_t image[1024];
445 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
446 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
448 #ifdef HW_MOUSE_ACCEL
449 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
450 struct vmsvga_cursor_definition_s *c)
453 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
454 c->mask[i] = ~c->mask[i];
456 if (s->ds->cursor_define)
457 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
458 (uint8_t *) c->image, (uint8_t *) c->mask);
462 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
464 if (!s->config || !s->enable)
466 return (s->cmd->next_cmd == s->cmd->stop);
469 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
471 uint32_t cmd = s->fifo[s->cmd->stop >> 2];
473 if (s->cmd->stop >= s->cmd->max)
474 s->cmd->stop = s->cmd->min;
478 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
480 uint32_t cmd, colour;
482 int x, y, dx, dy, width, height;
483 struct vmsvga_cursor_definition_s cursor;
484 while (!vmsvga_fifo_empty(s))
485 switch (cmd = vmsvga_fifo_read(s)) {
486 case SVGA_CMD_UPDATE:
487 case SVGA_CMD_UPDATE_VERBOSE:
488 x = vmsvga_fifo_read(s);
489 y = vmsvga_fifo_read(s);
490 width = vmsvga_fifo_read(s);
491 height = vmsvga_fifo_read(s);
492 vmsvga_update_rect_delayed(s, x, y, width, height);
495 case SVGA_CMD_RECT_FILL:
496 colour = vmsvga_fifo_read(s);
497 x = vmsvga_fifo_read(s);
498 y = vmsvga_fifo_read(s);
499 width = vmsvga_fifo_read(s);
500 height = vmsvga_fifo_read(s);
502 vmsvga_fill_rect(s, colour, x, y, width, height);
508 case SVGA_CMD_RECT_COPY:
509 x = vmsvga_fifo_read(s);
510 y = vmsvga_fifo_read(s);
511 dx = vmsvga_fifo_read(s);
512 dy = vmsvga_fifo_read(s);
513 width = vmsvga_fifo_read(s);
514 height = vmsvga_fifo_read(s);
516 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
522 case SVGA_CMD_DEFINE_CURSOR:
523 cursor.id = vmsvga_fifo_read(s);
524 cursor.hot_x = vmsvga_fifo_read(s);
525 cursor.hot_y = vmsvga_fifo_read(s);
526 cursor.width = x = vmsvga_fifo_read(s);
527 cursor.height = y = vmsvga_fifo_read(s);
529 cursor.bpp = vmsvga_fifo_read(s);
530 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
531 cursor.mask[args] = vmsvga_fifo_read(s);
532 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
533 cursor.image[args] = vmsvga_fifo_read(s);
534 #ifdef HW_MOUSE_ACCEL
535 vmsvga_cursor_define(s, &cursor);
543 * Other commands that we at least know the number of arguments
544 * for so we can avoid FIFO desync if driver uses them illegally.
546 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
550 x = vmsvga_fifo_read(s);
551 y = vmsvga_fifo_read(s);
554 case SVGA_CMD_RECT_ROP_FILL:
557 case SVGA_CMD_RECT_ROP_COPY:
560 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
563 args = 7 + (vmsvga_fifo_read(s) >> 2);
565 case SVGA_CMD_SURFACE_ALPHA_BLEND:
570 * Other commands that are not listed as depending on any
571 * CAPABILITIES bits, but are not described in the README either.
573 case SVGA_CMD_SURFACE_FILL:
574 case SVGA_CMD_SURFACE_COPY:
575 case SVGA_CMD_FRONT_ROP_FILL:
577 case SVGA_CMD_INVALID_CMD:
584 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
592 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
594 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
598 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
600 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
604 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
607 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
612 case SVGA_REG_ENABLE:
618 case SVGA_REG_HEIGHT:
621 case SVGA_REG_MAX_WIDTH:
622 return SVGA_MAX_WIDTH;
624 case SVGA_REG_MAX_HEIGHT:
625 return SVGA_MAX_HEIGHT;
630 case SVGA_REG_BITS_PER_PIXEL:
631 return (s->depth + 7) & ~7;
633 case SVGA_REG_PSEUDOCOLOR:
636 case SVGA_REG_RED_MASK:
638 case SVGA_REG_GREEN_MASK:
640 case SVGA_REG_BLUE_MASK:
643 case SVGA_REG_BYTES_PER_LINE:
644 return ((s->depth + 7) >> 3) * s->new_width;
646 case SVGA_REG_FB_START:
647 return SVGA_MEM_BASE;
649 case SVGA_REG_FB_OFFSET:
652 case SVGA_REG_VRAM_SIZE:
653 return s->vram_size - SVGA_FIFO_SIZE;
655 case SVGA_REG_FB_SIZE:
658 case SVGA_REG_CAPABILITIES:
659 caps = SVGA_CAP_NONE;
661 caps |= SVGA_CAP_RECT_COPY;
664 caps |= SVGA_CAP_RECT_FILL;
666 #ifdef HW_MOUSE_ACCEL
667 if (s->ds->mouse_set)
668 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
669 SVGA_CAP_CURSOR_BYPASS;
673 case SVGA_REG_MEM_START:
674 return SVGA_MEM_BASE + s->vram_size - SVGA_FIFO_SIZE;
676 case SVGA_REG_MEM_SIZE:
677 return SVGA_FIFO_SIZE;
679 case SVGA_REG_CONFIG_DONE:
686 case SVGA_REG_GUEST_ID:
689 case SVGA_REG_CURSOR_ID:
692 case SVGA_REG_CURSOR_X:
695 case SVGA_REG_CURSOR_Y:
698 case SVGA_REG_CURSOR_ON:
701 case SVGA_REG_HOST_BITS_PER_PIXEL:
702 return (s->depth + 7) & ~7;
704 case SVGA_REG_SCRATCH_SIZE:
705 return s->scratch_size;
707 case SVGA_REG_MEM_REGS:
708 case SVGA_REG_NUM_DISPLAYS:
709 case SVGA_REG_PITCHLOCK:
710 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
714 if (s->index >= SVGA_SCRATCH_BASE &&
715 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
716 return s->scratch[s->index - SVGA_SCRATCH_BASE];
717 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
723 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
725 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
728 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
732 case SVGA_REG_ENABLE:
734 s->config &= !!value;
739 s->invalidate(opaque);
742 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
746 s->new_width = value;
750 case SVGA_REG_HEIGHT:
751 s->new_height = value;
756 case SVGA_REG_BITS_PER_PIXEL:
757 if (value != s->depth) {
758 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
763 case SVGA_REG_CONFIG_DONE:
765 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
766 /* Check range and alignment. */
767 if ((s->cmd->min | s->cmd->max |
768 s->cmd->next_cmd | s->cmd->stop) & 3)
770 if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
772 if (s->cmd->max > SVGA_FIFO_SIZE)
774 if (s->cmd->max < s->cmd->min + 10 * 1024)
782 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
785 case SVGA_REG_GUEST_ID:
788 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
789 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
790 printf("%s: guest runs %s.\n", __FUNCTION__,
791 vmsvga_guest_id[value - GUEST_OS_BASE]);
795 case SVGA_REG_CURSOR_ID:
796 s->cursor.id = value;
799 case SVGA_REG_CURSOR_X:
803 case SVGA_REG_CURSOR_Y:
807 case SVGA_REG_CURSOR_ON:
808 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
809 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
810 #ifdef HW_MOUSE_ACCEL
811 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
812 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
816 case SVGA_REG_MEM_REGS:
817 case SVGA_REG_NUM_DISPLAYS:
818 case SVGA_REG_PITCHLOCK:
819 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
823 if (s->index >= SVGA_SCRATCH_BASE &&
824 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
825 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
828 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
832 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
834 printf("%s: what are we supposed to return?\n", __FUNCTION__);
838 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
840 printf("%s: what are we supposed to do with (%08x)?\n",
844 static inline void vmsvga_size(struct vmsvga_state_s *s)
846 if (s->new_width != s->width || s->new_height != s->height) {
847 s->width = s->new_width;
848 s->height = s->new_height;
849 dpy_resize(s->ds, s->width, s->height);
854 static void vmsvga_update_display(void *opaque)
856 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
867 vmsvga_update_rect_flush(s);
870 * Is it more efficient to look at vram VGA-dirty bits or wait
871 * for the driver to issue SVGA_CMD_UPDATE?
873 if (s->invalidated) {
875 vmsvga_update_screen(s);
879 static void vmsvga_reset(struct vmsvga_state_s *s)
887 s->depth = s->ds->depth ? s->ds->depth : 24;
888 s->bypp = (s->depth + 7) >> 3;
890 s->redraw_fifo_first = 0;
891 s->redraw_fifo_last = 0;
894 s->wred = 0x00000007;
895 s->wgreen = 0x00000038;
896 s->wblue = 0x000000c0;
899 s->wred = 0x0000001f;
900 s->wgreen = 0x000003e0;
901 s->wblue = 0x00007c00;
904 s->wred = 0x0000001f;
905 s->wgreen = 0x000007e0;
906 s->wblue = 0x0000f800;
909 s->wred = 0x00ff0000;
910 s->wgreen = 0x0000ff00;
911 s->wblue = 0x000000ff;
914 s->wred = 0x00ff0000;
915 s->wgreen = 0x0000ff00;
916 s->wblue = 0x000000ff;
922 static void vmsvga_invalidate_display(void *opaque)
924 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
927 s->invalidate(opaque);
935 /* save the vga display in a PPM image even if no display is
937 static void vmsvga_screen_dump(void *opaque, const char *filename)
939 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
942 s->screen_dump(opaque, filename);
947 if (s->depth == 32) {
948 ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
953 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
955 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
956 addr -= SVGA_MEM_BASE;
957 if (addr < s->fb_size)
958 return *(uint8_t *) (s->ds->data + addr);
960 return *(uint8_t *) (s->vram + addr);
963 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
965 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
966 addr -= SVGA_MEM_BASE;
967 if (addr < s->fb_size)
968 return *(uint16_t *) (s->ds->data + addr);
970 return *(uint16_t *) (s->vram + addr);
973 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
975 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
976 addr -= SVGA_MEM_BASE;
977 if (addr < s->fb_size)
978 return *(uint32_t *) (s->ds->data + addr);
980 return *(uint32_t *) (s->vram + addr);
983 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
986 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
987 addr -= SVGA_MEM_BASE;
988 if (addr < s->fb_size)
989 *(uint8_t *) (s->ds->data + addr) = value;
991 *(uint8_t *) (s->vram + addr) = value;
994 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
997 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
998 addr -= SVGA_MEM_BASE;
999 if (addr < s->fb_size)
1000 *(uint16_t *) (s->ds->data + addr) = value;
1002 *(uint16_t *) (s->vram + addr) = value;
1005 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1008 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1009 addr -= SVGA_MEM_BASE;
1010 if (addr < s->fb_size)
1011 *(uint32_t *) (s->ds->data + addr) = value;
1013 *(uint32_t *) (s->vram + addr) = value;
1016 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1022 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1029 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1031 qemu_put_be32(f, s->depth);
1032 qemu_put_be32(f, s->enable);
1033 qemu_put_be32(f, s->config);
1034 qemu_put_be32(f, s->cursor.id);
1035 qemu_put_be32(f, s->cursor.x);
1036 qemu_put_be32(f, s->cursor.y);
1037 qemu_put_be32(f, s->cursor.on);
1038 qemu_put_be32(f, s->index);
1039 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1040 qemu_put_be32(f, s->new_width);
1041 qemu_put_be32(f, s->new_height);
1042 qemu_put_be32s(f, &s->guest);
1043 qemu_put_be32s(f, &s->svgaid);
1044 qemu_put_be32(f, s->syncing);
1045 qemu_put_be32(f, s->fb_size);
1048 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1051 depth=qemu_get_be32(f);
1052 s->enable=qemu_get_be32(f);
1053 s->config=qemu_get_be32(f);
1054 s->cursor.id=qemu_get_be32(f);
1055 s->cursor.x=qemu_get_be32(f);
1056 s->cursor.y=qemu_get_be32(f);
1057 s->cursor.on=qemu_get_be32(f);
1058 s->index=qemu_get_be32(f);
1059 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1060 s->new_width=qemu_get_be32(f);
1061 s->new_height=qemu_get_be32(f);
1062 qemu_get_be32s(f, &s->guest);
1063 qemu_get_be32s(f, &s->svgaid);
1064 s->syncing=qemu_get_be32(f);
1065 s->fb_size=qemu_get_be32(f);
1067 if (s->enable && depth != s->depth) {
1068 printf("%s: need colour depth of %i bits to resume operation.\n",
1069 __FUNCTION__, depth);
1075 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1080 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1081 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1086 s->vram = vga_ram_base;
1087 s->vram_size = vga_ram_size;
1089 s->scratch_size = SVGA_SCRATCH_SIZE;
1090 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1095 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1096 vmsvga_vram_write, s);
1098 iomemtype = vga_ram_offset | IO_MEM_RAM;
1100 cpu_register_physical_memory(SVGA_MEM_BASE, vga_ram_size,
1103 graphic_console_init(ds, vmsvga_update_display,
1104 vmsvga_invalidate_display, vmsvga_screen_dump, s);
1107 vga_common_init((VGAState *) s, ds,
1108 vga_ram_base, vga_ram_offset, vga_ram_size);
1109 vga_init((VGAState *) s);
1113 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1115 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1116 pci_device_save(&s->card, f);
1117 vmsvga_save(&s->chip, f);
1120 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1122 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1125 ret = pci_device_load(&s->card, f);
1129 ret = vmsvga_load(&s->chip, f);
1136 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1137 uint32_t addr, uint32_t size, int type)
1139 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1140 struct vmsvga_state_s *s = &d->chip;
1142 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1143 1, 4, vmsvga_index_read, s);
1144 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1145 1, 4, vmsvga_index_write, s);
1146 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1147 1, 4, vmsvga_value_read, s);
1148 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1149 1, 4, vmsvga_value_write, s);
1150 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1151 1, 4, vmsvga_bios_read, s);
1152 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1153 1, 4, vmsvga_bios_write, s);
1156 #define PCI_VENDOR_ID_VMWARE 0x15ad
1157 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1158 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1159 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
1160 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1161 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1162 #define PCI_CLASS_BASE_DISPLAY 0x03
1163 #define PCI_CLASS_SUB_VGA 0x00
1164 #define PCI_CLASS_HEADERTYPE_00h 0x00
1166 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1167 unsigned long vga_ram_offset, int vga_ram_size)
1169 struct pci_vmsvga_state_s *s;
1171 /* Setup PCI configuration */
1172 s = (struct pci_vmsvga_state_s *)
1173 pci_register_device(bus, "QEMUware SVGA",
1174 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1175 s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1176 s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1177 s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1178 s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1179 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1180 s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1181 s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
1182 s->card.config[0x0c] = 0x08; /* Cache line size */
1183 s->card.config[0x0d] = 0x40; /* Latency timer */
1184 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
1185 s->card.config[0x10] = ((SVGA_IO_BASE >> 0) & 0xff) | 1;
1186 s->card.config[0x11] = (SVGA_IO_BASE >> 8) & 0xff;
1187 s->card.config[0x12] = (SVGA_IO_BASE >> 16) & 0xff;
1188 s->card.config[0x13] = (SVGA_IO_BASE >> 24) & 0xff;
1189 s->card.config[0x18] = (SVGA_MEM_BASE >> 0) & 0xff;
1190 s->card.config[0x19] = (SVGA_MEM_BASE >> 8) & 0xff;
1191 s->card.config[0x1a] = (SVGA_MEM_BASE >> 16) & 0xff;
1192 s->card.config[0x1b] = (SVGA_MEM_BASE >> 24) & 0xff;
1193 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1194 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1195 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1196 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1197 s->card.config[0x3c] = 0xff; /* End */
1199 pci_register_io_region(&s->card, 0, 0x10,
1200 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1202 vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1204 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);