1 --- kernel-maemo-2.6.28.orig/arch/arm/boot/compressed/head.S
2 +++ kernel-maemo-2.6.28/arch/arm/boot/compressed/head.S
5 mcr p14, 0, \ch, c0, c5, 0
7 +elif defined(CONFIG_CPU_V7)
10 + .macro writeb, ch, rb
11 +wait: mrc p14, 0, pc, c0, c1, 0
13 + mcr p14, 0, \ch, c0, c5, 0
18 --- kernel-maemo-2.6.28.orig/arch/arm/boot/compressed/misc.c
19 +++ kernel-maemo-2.6.28/arch/arm/boot/compressed/misc.c
21 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
24 +#elif defined(CONFIG_CPU_V7)
26 +static void icedcc_putc(int ch)
29 + "wait: mrc p14, 0, pc, c0, c1, 0 \n\
31 + mcr p14, 0, %0, c0, c5, 0 "
37 static void icedcc_putc(int ch)
38 --- kernel-maemo-2.6.28.orig/arch/arm/include/asm/cacheflush.h
39 +++ kernel-maemo-2.6.28/arch/arm/include/asm/cacheflush.h
41 * Please note that the implementation of these, and the required
42 * effects are cache-type (VIVT/VIPT/PIPT) specific.
44 - * flush_cache_kern_all()
47 * Unconditionally clean and invalidate the entire cache.
49 - * flush_cache_user_mm(mm)
52 * Clean and invalidate all user space cache entries
53 * before a change of page tables.
55 - * flush_cache_user_range(start, end, flags)
56 + * flush_user_range(start, end, flags)
58 * Clean and invalidate a range of cache entries in the
59 * specified address space before a change of page tables.
61 * - start - virtual start address
62 * - end - virtual end address
64 + * coherent_user_range(start, end)
66 + * Ensure coherency between the Icache and the Dcache in the
67 + * region described by start, end. If you have non-snooping
68 + * Harvard caches, you need to implement this function.
69 + * - start - virtual start address
70 + * - end - virtual end address
72 + * flush_kern_dcache_area(kaddr, size)
74 + * Ensure that the data held in page is written back.
75 + * - kaddr - page address
76 + * - size - region size
81 --- kernel-maemo-2.6.28.orig/arch/arm/kernel/debug.S
82 +++ kernel-maemo-2.6.28/arch/arm/kernel/debug.S
87 +#elif defined(CONFIG_CPU_V7)
92 + .macro senduart, rd, rx
93 + mcr p14, 0, \rd, c0, c5, 0
96 + .macro busyuart, rd, rx
97 +busy: mrc p14, 0, pc, c0, c1, 0
101 + .macro waituart, rd, rx
102 +wait: mrc p14, 0, pc, c0, c1, 0
110 --- kernel-maemo-2.6.28.orig/arch/arm/mm/mmu.c
111 +++ kernel-maemo-2.6.28/arch/arm/mm/mmu.c
113 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
114 flush_pmd_entry(pmd);
117 + local_flush_tlb_all();
119 --- kernel-maemo-2.6.28.orig/arch/arm/mm/proc-v6.S
120 +++ kernel-maemo-2.6.28/arch/arm/mm/proc-v6.S
122 * to what would be the reset vector.
124 * - loc - location to jump to for soft reset
126 - * It is assumed that:
130 --- kernel-maemo-2.6.28.orig/arch/arm/mm/proc-v7.S
131 +++ kernel-maemo-2.6.28/arch/arm/mm/proc-v7.S
133 ENDPROC(cpu_v7_proc_init)
135 ENTRY(cpu_v7_proc_fin)
138 + cpsid if @ disable interrupts
139 + bl v7_flush_kern_cache_all
140 + mrc p15, 0, r0, c1, c0, 0 @ ctrl register
141 + bic r0, r0, #0x1000 @ ...i............
142 + bic r0, r0, #0x0006 @ .............ca.
143 + mcr p15, 0, r0, c1, c0, 0 @ disable caches
145 ENDPROC(cpu_v7_proc_fin)
149 * to what would be the reset vector.
151 * - loc - location to jump to for soft reset
153 - * It is assumed that: