git.maemo.org Git - drnoksnes/blob - os9x_65c816.s

   1         .DATA
   2 /****************************************************************
   3 ****************************************************************/
   4         .align 4
   5
   6     @ notaz
   7         .equiv ASM_SPC700,              1               ;@ 1 = use notaz's ASM_SPC700 core
   8
   9 /****************************************************************
  10         DEFINES
  11 ****************************************************************/
  12
  13 .equ MAP_LAST,  12
  14
  15 rstatus         .req R4  @ format : 0xff800000
  16 reg_d_bank      .req R4  @ format : 0x000000ll
  17 reg_a           .req R5  @ format : 0xhhll0000 or 0xll000000
  18 reg_d           .req R6  @ format : 0xhhll0000
  19 reg_p_bank      .req R6  @ format : 0x000000ll
  20 reg_x           .req R7  @ format : 0xhhll0000 or 0xll000000
  21 reg_s           .req R8  @ format : 0x0000hhll
  22 reg_y           .req R9  @ format : 0xhhll0000 or 0xll000000
  23
  24 rpc             .req R10 @ 32bits address
  25 reg_cycles      .req R11 @ 32bits counter
  26 regpcbase       .req R12 @ 32bits address
  27
  28 rscratch        .req R0  @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
  29 regopcode       .req R0  @ format : 0x000000ll
  30 rscratch2       .req R1  @ format : 0xhhll for calculation and value
  31 rscratch3       .req R2  @
  32 rscratch4       .req R3  @ ??????
  33
  34 @ used for SBC opcode
  35 rscratch9       .req R10 @ ??????
  36
  37 reg_cpu_var .req R14
  38
  39
  40
  41 @ not used
  42 @ R13   @ Pointer 32 bit on a struct.
  43
  44 @ R15 = pc (sic!)
  45
  46
  47 /*
  48 .equ Carry       1
  49 .equ Zero        2
  50 .equ IRQ         4
  51 .equ Decimal     8
  52 .equ IndexFlag  16
  53 .equ MemoryFlag 32
  54 .equ Overflow   64
  55 .equ Negative  128
  56 .equ Emulation 256*/
  57
  58 .equ STATUS_SHIFTER,            24
  59 .equ MASK_EMUL,         (1<<(STATUS_SHIFTER-1))
  60 .equ MASK_SHIFTER_CARRY,        (STATUS_SHIFTER+1)
  61 .equ    MASK_CARRY,             (1<<(STATUS_SHIFTER))  @ 0
  62 .equ    MASK_ZERO,              (2<<(STATUS_SHIFTER))  @ 1
  63 .equ MASK_IRQ,          (4<<(STATUS_SHIFTER))  @ 2
  64 .equ MASK_DECIMAL,              (8<<(STATUS_SHIFTER))  @ 3
  65 .equ    MASK_INDEX,             (16<<(STATUS_SHIFTER)) @ 4  @ 1
  66 .equ    MASK_MEM,               (32<<(STATUS_SHIFTER)) @ 5  @ 2
  67 .equ    MASK_OVERFLOW,          (64<<(STATUS_SHIFTER)) @ 6  @ 4
  68 .equ    MASK_NEG,               (128<<(STATUS_SHIFTER))@ 7  @ 8
  69
  70 .equ ONE_CYCLE, 6
  71 .equ SLOW_ONE_CYCLE, 8
  72
  73 .equ    NMI_FLAG,           (1 << 7)
  74 .equ IRQ_PENDING_FLAG,    (1 << 11)
  75 .equ SCAN_KEYS_FLAG,        (1 << 4)
  76
  77
  78 .equ MEMMAP_BLOCK_SIZE, (0x1000)
  79 .equ MEMMAP_SHIFT, 12
  80 .equ MEMMAP_MASK, (0xFFF)
  81
  82 /****************************************************************
  83         MACROS
  84 ****************************************************************/
  85
  86 @ #include "os9x_65c816_mac_gen.h"
  87 /*****************************************************************/
  88 /*     Offset in SCPUState structure                             */
  89 /*****************************************************************/
  90 .equ Flags_ofs,             0
  91 .equ BranchSkip_ofs,    4
  92 .equ NMIActive_ofs,             5
  93 .equ IRQActive_ofs,             6
  94 .equ WaitingForInterrupt_ofs,   7
  95
  96 .equ    RPB_ofs,                8
  97 .equ    RDB_ofs,                9
  98 .equ    RP_ofs,             10
  99 .equ    RA_ofs,             12
 100 .equ    RAH_ofs,            13
 101 .equ    RD_ofs,             14
 102 .equ    RX_ofs,             16
 103 .equ    RS_ofs,             18
 104 .equ    RY_ofs,             20
 105 @.equ   RPC_ofs,                22
 106
 107 .equ PC_ofs,                    24
 108 .equ Cycles_ofs,                28
 109 .equ PCBase_ofs,                32
 110
 111 .equ PCAtOpcodeStart_ofs,       36
 112 .equ WaitAddress_ofs,           40
 113 .equ WaitCounter_ofs,           44
 114 .equ NextEvent_ofs,                 48
 115 .equ V_Counter_ofs,                 52
 116 .equ MemSpeed_ofs,                  56
 117 .equ MemSpeedx2_ofs,            60
 118 .equ FastROMSpeed_ofs,      64
 119 .equ AutoSaveTimer_ofs,     68
 120 .equ NMITriggerPoint_ofs,       72
 121 .equ NMICycleCount_ofs,     76
 122 .equ IRQCycleCount_ofs,     80
 123
 124 .equ InDMA_ofs,                 84
 125 .equ WhichEvent,                    85
 126 .equ SRAMModified_ofs,      86
 127 .equ BRKTriggered_ofs,      87
 128 .equ    asm_OPTABLE_ofs,                88
 129 .equ TriedInterleavedMode2_ofs, 92
 130
 131 .equ Map_ofs,               96
 132 .equ WriteMap_ofs,      100
 133 .equ MemorySpeed_ofs,   104
 134 .equ BlockIsRAM_ofs,    108
 135 .equ SRAM,                      112
 136 .equ BWRAM,             116
 137 .equ SRAMMask,          120
 138
 139 .equ    APUExecuting_ofs,   122
 140
 141 .equ    PALMOS_R9_ofs,      124
 142 .equ    PALMOS_R10_ofs,         128
 143
 144 @ notaz
 145 .equ    APU_Cycles,         132
 146
 147 /*****************************************************************/
 148
 149 /* prepare */
 150 .macro          PREPARE_C_CALL
 151         STMFD   R13!,{R12,R14}
 152 .endm
 153 .macro          PREPARE_C_CALL_R0
 154         STMFD   R13!,{R0,R12,R14}
 155 .endm
 156 .macro          PREPARE_C_CALL_R0R1
 157         STMFD   R13!,{R0,R1,R12,R14}
 158 .endm
 159 .macro          PREPARE_C_CALL_LIGHT
 160         STMFD   R13!,{R14}
 161 .endm
 162 .macro          PREPARE_C_CALL_LIGHTR12
 163         STMFD   R13!,{R12,R14}
 164 .endm
 165 /* restore */
 166 .macro          RESTORE_C_CALL
 167         LDMFD   R13!,{R12,R14}
 168 .endm
 169 .macro          RESTORE_C_CALL_R0
 170         LDMFD   R13!,{R0,R12,R14}
 171 .endm
 172 .macro          RESTORE_C_CALL_R1
 173         LDMFD   R13!,{R1,R12,R14}
 174 .endm
 175 .macro          RESTORE_C_CALL_LIGHT
 176         LDMFD   R13!,{R14}
 177 .endm
 178 .macro          RESTORE_C_CALL_LIGHTR12
 179         LDMFD   R13!,{R12,R14}
 180 .endm
 181
 182
 183 @ --------------
 184 .macro          LOAD_REGS
 185     @ notaz
 186     add     r0,reg_cpu_var,#8
 187     ldmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 188     @ rstatus (P) & reg_d_bank
 189     mov     reg_d_bank,r1,lsl #16
 190     mov     reg_d_bank,reg_d_bank,lsr #24
 191     mov     r0,r1,lsr #16
 192         orrs    rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
 193         @ if Carry set, then EMULATION bit was set
 194         orrcs   rstatus,rstatus,#MASK_EMUL
 195     @ reg_d & reg_p_bank
 196     mov     reg_d,reg_a,lsr #16
 197     mov     reg_d,reg_d,lsl #8
 198     orr     reg_d,reg_d,r1,lsl #24
 199     mov     reg_d,reg_d,ror #24    @ 0xdddd00pb
 200     @ reg_x, reg_s
 201     mov     reg_s,reg_x,lsr #16
 202         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 203         tst             rstatus,#MASK_INDEX
 204         movne   reg_x,reg_x,lsl #24
 205         movne   reg_y,reg_y,lsl #24
 206         moveq   reg_x,reg_x,lsl #16
 207         moveq   reg_y,reg_y,lsl #16
 208         tst             rstatus,#MASK_MEM
 209         movne   reg_a,reg_a,lsl #24
 210         moveq   reg_a,reg_a,lsl #16
 211
 212 /*
 213     @ reg_d & reg_p_bank share the same register
 214         LDRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 215         LDRH            rscratch,[reg_cpu_var,#RD_ofs]
 216         ORR             reg_d,reg_d,rscratch, LSL #16
 217         @ rstatus & reg_d_bank share the same register
 218         LDRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 219         LDRH            rscratch,[reg_cpu_var,#RP_ofs]
 220         ORRS            rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
 221         @ if Carry set, then EMULATION bit was set
 222         ORRCS           rstatus,rstatus,#MASK_EMUL
 223         @
 224         LDRH            reg_a,[reg_cpu_var,#RA_ofs]
 225         LDRH            reg_x,[reg_cpu_var,#RX_ofs]
 226         LDRH            reg_y,[reg_cpu_var,#RY_ofs]
 227         LDRH            reg_s,[reg_cpu_var,#RS_ofs]
 228         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 229         TST             rstatus,#MASK_INDEX
 230         MOVNE           reg_x,reg_x,LSL #24
 231         MOVNE           reg_y,reg_y,LSL #24
 232         MOVEQ           reg_x,reg_x,LSL #16
 233         MOVEQ           reg_y,reg_y,LSL #16
 234         TST             rstatus,#MASK_MEM
 235         MOVNE           reg_a,reg_a,LSL #24
 236         MOVEQ           reg_a,reg_a,LSL #16
 237
 238         LDR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 239         LDR             rpc,[reg_cpu_var,#PC_ofs]
 240         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 241 */
 242 .endm
 243
 244
 245 .macro          SAVE_REGS
 246     @ notaz
 247     @ reg_p_bank, reg_d_bank and rstatus
 248     mov         r1, rstatus, lsr #16
 249     orr     r1, r1, reg_p_bank, lsl #24
 250         movs    r1, r1, lsr #8
 251         orrcs   r1, r1, #0x100 @ EMULATION bit
 252     orr     r1, r1, reg_d_bank, lsl #24
 253     mov     r1, r1, ror #16
 254     @ reg_a, reg_d
 255         tst             rstatus,#MASK_MEM
 256         ldrneh  r0, [reg_cpu_var,#RA_ofs]
 257         bicne   r0, r0,#0xFF
 258         orrne   reg_a, r0, reg_a,lsr #24
 259         moveq   reg_a, reg_a, lsr #16
 260     mov     reg_d, reg_d, lsr #16
 261         orr     reg_a, reg_a, reg_d, lsl #16
 262         @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
 263         tst             rstatus,#MASK_INDEX
 264         movne   reg_x,reg_x,LSR #24
 265         movne   reg_y,reg_y,LSR #24
 266         moveq   reg_x,reg_x,LSR #16
 267         moveq   reg_y,reg_y,LSR #16
 268     @ reg_x, reg_s
 269         orr     reg_x, reg_x, reg_s, lsl #16
 270     @ store
 271     add     r0,reg_cpu_var,#8
 272     stmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 273
 274 /*
 275     @ reg_d & reg_p_bank is same register
 276         STRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 277         MOV             rscratch,reg_d, LSR #16
 278         STRH            rscratch,[reg_cpu_var,#RD_ofs]
 279         @ rstatus & reg_d_bank is same register
 280         STRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 281         MOVS            rscratch, rstatus, LSR #STATUS_SHIFTER
 282         ORRCS           rscratch,rscratch,#0x100 @ EMULATION bit
 283         STRH            rscratch,[reg_cpu_var,#RP_ofs]
 284         @
 285         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 286         TST             rstatus,#MASK_INDEX
 287         MOVNE           rscratch,reg_x,LSR #24
 288         MOVNE           rscratch2,reg_y,LSR #24
 289         MOVEQ           rscratch,reg_x,LSR #16
 290         MOVEQ           rscratch2,reg_y,LSR #16
 291         STRH            rscratch,[reg_cpu_var,#RX_ofs]
 292         STRH            rscratch2,[reg_cpu_var,#RY_ofs]
 293         TST             rstatus,#MASK_MEM
 294         LDRNEH          rscratch,[reg_cpu_var,#RA_ofs]
 295         BICNE           rscratch,rscratch,#0xFF
 296         ORRNE           rscratch,rscratch,reg_a,LSR #24
 297         MOVEQ           rscratch,reg_a,LSR #16
 298         STRH            rscratch,[reg_cpu_var,#RA_ofs]
 299
 300         STRH            reg_s,[reg_cpu_var,#RS_ofs]
 301         STR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 302         STR             rpc,[reg_cpu_var,#PC_ofs]
 303
 304         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 305 */
 306 .endm
 307
 308 /*****************************************************************/
 309 .macro          ADD1CYCLE
 310                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 311 .endm
 312 .macro          ADD1CYCLENE
 313                 addne   reg_cycles,reg_cycles, #ONE_CYCLE
 314 .endm
 315 .macro          ADD1CYCLEEQ
 316                 addeq   reg_cycles,reg_cycles, #ONE_CYCLE
 317 .endm
 318
 319 .macro          ADD2CYCLE
 320                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 321 .endm
 322 .macro          ADD2CYCLENE
 323                 addne   reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 324 .endm
 325 .macro          ADD2CYCLE2MEM
 326                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 327                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 328                 add     reg_cycles, reg_cycles, rscratch, LSL #1
 329 .endm
 330 .macro          ADD2CYCLE1MEM
 331                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 332                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 333                 add     reg_cycles, reg_cycles, rscratch
 334 .endm
 335
 336 .macro          ADD3CYCLE
 337                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*3)
 338 .endm
 339
 340 .macro          ADD1CYCLE1MEM
 341                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 342                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 343                 add     reg_cycles, reg_cycles, rscratch
 344 .endm
 345
 346 .macro          ADD1CYCLE2MEM
 347                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 348                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 349                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 350 .endm
 351
 352 .macro          ADD1MEM
 353                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 354                 add     reg_cycles, reg_cycles, rscratch
 355 .endm
 356
 357 .macro          ADD2MEM
 358                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 359                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 360 .endm
 361
 362 .macro          ADD3MEM
 363                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 364                 add     reg_cycles, rscratch, reg_cycles
 365                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 366 .endm
 367
 368 /**************/
 369 .macro          ClearDecimal
 370                 BIC     rstatus,rstatus,#MASK_DECIMAL
 371 .endm
 372 .macro          SetDecimal
 373                 ORR     rstatus,rstatus,#MASK_DECIMAL
 374 .endm
 375 .macro          SetIRQ
 376                 ORR     rstatus,rstatus,#MASK_IRQ
 377 .endm
 378 .macro          ClearIRQ
 379                 BIC     rstatus,rstatus,#MASK_IRQ
 380 .endm
 381
 382 .macro          CPUShutdown
 383 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
 384                 LDR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 385                 CMP             rpc,rscratch
 386                 BNE             5431f
 387 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
 388                 LDR             rscratch,[reg_cpu_var,#Flags_ofs]
 389                 LDR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 390                 TST             rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
 391                 BNE             5432f
 392                 MOVS            rscratch2,rscratch2
 393                 BNE             5432f
 394 @ CPU.WaitAddress = NULL;
 395                 MOV             rscratch,#0
 396                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 397 @ if (Settings.SA1)
 398 @               S9xSA1ExecuteDuringSleep ();            : TODO
 399
 400 @           CPU.Cycles = CPU.NextEvent;
 401                 LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
 402                 LDRB            r0,[reg_cpu_var,#APUExecuting_ofs]
 403                 MOVS            r0,r0
 404                 BEQ             5431f
 405 @           if (IAPU.APUExecuting)
 406 /*          {
 407                 ICPU.CPUExecuting = FALSE;
 408                 do
 409                 {
 410                     APU_EXECUTE1();
 411                 } while (APU.Cycles < CPU.NextEvent);
 412                 ICPU.CPUExecuting = TRUE;
 413             }
 414         */
 415                 asmAPU_EXECUTE2
 416                 B               5431f
 417 @.pool
 418 5432:
 419 /*      else
 420         if (CPU.WaitCounter >= 2)
 421             CPU.WaitCounter = 1;
 422         else
 423             CPU.WaitCounter--;
 424 */
 425                 CMP             rscratch2,#1
 426                 MOVHI           rscratch2,#1
 427                 @ SUBLS         rscratch2,rscratch2,#1
 428                 MOVLS           rscratch2,#0
 429                 STR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 430 5431:
 431
 432 .endm
 433 .macro          BranchCheck0
 434                 /*in rsctach : OpAddress
 435                 /*destroy rscratch2*/
 436                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 437                 MOVS    rscratch2,rscratch2
 438                 BEQ     1110f
 439                 MOV     rscratch2,#0
 440                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 441                 SUB     rscratch2,rpc,regpcbase
 442                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 443                 CMP     rscratch2,rscratch
 444                 BHI     1111f
 445 1110:
 446 .endm
 447 .macro          BranchCheck1
 448                 /*in rsctach : OpAddress
 449                 /*destroy rscratch2*/
 450                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 451                 MOVS    rscratch2,rscratch2
 452                 BEQ     1110f
 453                 MOV     rscratch2,#0
 454                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 455                 SUB     rscratch2,rpc,regpcbase
 456                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 457                 CMP     rscratch2,rscratch
 458                 BHI     1111f
 459 1110:
 460 .endm
 461 .macro          BranchCheck2
 462                 /*in rsctach : OpAddress
 463                 /*destroy rscratch2*/
 464                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 465                 MOVS    rscratch2,rscratch2
 466                 BEQ     1110f
 467                 MOV     rscratch2,#0
 468                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 469                 SUB     rscratch2,rpc,regpcbase
 470                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 471                 CMP     rscratch2,rscratch
 472                 BHI     1111f
 473 1110:
 474 .endm
 475
 476 .macro          S9xSetPCBase
 477                 @  in  : rscratch (0x00hhmmll)
 478                 PREPARE_C_CALL
 479                 BL      asm_S9xSetPCBase
 480                 RESTORE_C_CALL
 481                 LDR     rpc,[reg_cpu_var,#PC_ofs]
 482                 LDR     regpcbase,[reg_cpu_var,#PCBase_ofs]
 483 .endm
 484
 485 .macro          S9xFixCycles
 486                 TST             rstatus,#MASK_EMUL
 487                 LDRNE           rscratch, = jumptable1     @ Mode 0 : M=1,X=1
 488                 BNE             991111f
 489                 @ EMULATION=0
 490                 TST             rstatus,#MASK_MEM
 491                 BEQ             991112f
 492                 @ MEMORY=1
 493                 TST             rstatus,#MASK_INDEX
 494                 @ INDEX=1  @ Mode 0 : M=1,X=1
 495                 LDRNE           rscratch, = jumptable1
 496                 @ INDEX=0  @ Mode 1 : M=1,X=0
 497                 LDREQ           rscratch, = jumptable2
 498                 B               991111f
 499 991112:         @ MEMORY=0
 500                 TST             rstatus,#MASK_INDEX
 501                 @ INDEX=1   @ Mode 3 : M=0,X=1
 502                 LDRNE           rscratch, = jumptable4
 503                 @ INDEX=0   @ Mode 2 : M=0,X=0
 504                 LDREQ           rscratch, = jumptable3
 505 991111:
 506                 STR             rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
 507 .endm
 508 /*
 509 .macro          S9xOpcode_NMI
 510                 SAVE_REGS
 511                 PREPARE_C_CALL_LIGHT
 512                 BL      asm_S9xOpcode_NMI
 513                 RESTORE_C_CALL_LIGHT
 514                 LOAD_REGS
 515 .endm
 516 .macro          S9xOpcode_IRQ
 517                 SAVE_REGS
 518                 PREPARE_C_CALL_LIGHT
 519                 BL      asm_S9xOpcode_IRQ
 520                 RESTORE_C_CALL_LIGHT
 521                 LOAD_REGS
 522 .endm
 523 */
 524 .macro          S9xDoHBlankProcessing
 525                 SAVE_REGS
 526                 PREPARE_C_CALL_LIGHT
 527 @               BL      asm_S9xDoHBlankProcessing
 528                 BL      S9xDoHBlankProcessing @ let's go straight to number one
 529                 RESTORE_C_CALL_LIGHT
 530                 LOAD_REGS
 531 .endm
 532
 533 /********************************/
 534 .macro          EXEC_OP
 535                 LDR             R1,[reg_cpu_var,#asm_OPTABLE_ofs]
 536                 STR             rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
 537                 ADD1MEM
 538                 LDRB            R0, [rpc], #1
 539
 540                 LDR             PC, [R1,R0, LSL #2]
 541 .endm
 542 .macro          NEXTOPCODE
 543                 LDR                     rscratch,[reg_cpu_var,#NextEvent_ofs]
 544                 CMP                     reg_cycles,rscratch
 545                 BLT                     mainLoop
 546                 S9xDoHBlankProcessing
 547                 B                       mainLoop
 548 .endm
 549
 550 .macro          asmAPU_EXECUTE
 551                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 552                 CMP             R0,#1   @ spc700 enabled, hack mode off
 553                 BNE                 43210f
 554                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 555         SUBS        R0,reg_cycles,R0
 556         BMI         43210f
 557 .if ASM_SPC700
 558                 PREPARE_C_CALL_LIGHTR12
 559                 BL              spc700_execute
 560                 RESTORE_C_CALL_LIGHTR12
 561         SUB     R0,reg_cycles,R0 @ sub cycles left
 562                 STR             R0,[reg_cpu_var,#APU_Cycles]
 563 .else
 564         @ SAVE_REGS
 565                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 566                 PREPARE_C_CALL_LIGHTR12
 567                 BL              asm_APU_EXECUTE
 568                 RESTORE_C_CALL_LIGHTR12
 569                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 570 .endif
 571         @ LOAD_REGS
 572                 @ S9xFixCycles
 573 43210:
 574 .endm
 575
 576 .macro          asmAPU_EXECUTE2
 577 .if ASM_SPC700
 578                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 579                 CMP             R0,#1   @ spc700 enabled, hack mode off
 580                 BNE                 43211f
 581                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 582         SUBS        R0,reg_cycles,R0 @ reg_cycles == NextEvent
 583         BLE         43211f
 584                 PREPARE_C_CALL_LIGHTR12
 585                 BL              spc700_execute
 586                 RESTORE_C_CALL_LIGHTR12
 587         SUB     R0,reg_cycles,R0 @ sub cycles left
 588                 STR             R0,[reg_cpu_var,#APU_Cycles]
 589 43211:
 590 .else
 591                 @ SAVE_REGS
 592                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 593                 PREPARE_C_CALL_LIGHTR12
 594                 BL              asm_APU_EXECUTE2
 595                 RESTORE_C_CALL_LIGHTR12
 596                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 597                 @ LOAD_REGS
 598 .endif
 599 .endm
 600
 601 @ #include "os9x_65c816_mac_mem.h"
 602 .macro          S9xGetWord
 603                 @  in  : rscratch (0x00hhmmll)
 604                 @  out : rscratch (0xhhll0000)
 605                 STMFD   R13!,{PC} @ Push return address
 606                 B       asmS9xGetWord
 607                 MOV     R0,R0
 608                 MOV     R0, R0, LSL #16
 609 .endm
 610 .macro          S9xGetWordLow
 611                 @  in  : rscratch (0x00hhmmll)
 612                 @  out : rscratch (0x0000hhll)
 613                 STMFD   R13!,{PC} @ Push return address
 614                 B       asmS9xGetWord
 615                 MOV     R0,R0
 616 .endm
 617 .macro          S9xGetWordRegStatus     reg
 618                 @  in  : rscratch (0x00hhmmll)
 619                 @  out : reg      (0xhhll0000)
 620                 @  flags have to be updated with read value
 621                 STMFD   R13!,{PC} @ Push return address
 622                 B       asmS9xGetWord
 623                 MOV     R0,R0
 624                 MOVS    \reg, R0, LSL #16
 625 .endm
 626 .macro          S9xGetWordRegNS reg
 627                 @  in  : rscratch (0x00hhmmll)
 628                 @  out : reg (0xhhll0000)
 629                 @  DOES NOT DESTROY rscratch (R0)
 630                 STMFD   R13!,{R0}
 631                 STMFD   R13!,{PC} @ Push return address
 632                 B       asmS9xGetWord
 633                 MOV     R0,R0
 634                 MOV     \reg, R0, LSL #16
 635                 LDMFD   R13!,{R0}
 636 .endm
 637 .macro          S9xGetWordLowRegNS      reg
 638                 @  in  : rscratch (0x00hhmmll)
 639                 @  out : reg (0xhhll0000)
 640                 @  DOES NOT DESTROY rscratch (R0)
 641                 STMFD   R13!,{R0}
 642                 STMFD   R13!,{PC} @ Push return address
 643                 B       asmS9xGetWord
 644                 MOV     R0,R0
 645                 MOV     \reg, R0
 646                 LDMFD   R13!,{R0}
 647 .endm
 648
 649 .macro          S9xGetByte
 650                 @  in  : rscratch (0x00hhmmll)
 651                 @  out : rscratch (0xll000000)
 652                 STMFD   R13!,{PC} @ Push return address
 653                 B       asmS9xGetByte
 654                 MOV     R0,R0
 655                 MOV     R0, R0, LSL #24
 656 .endm
 657 .macro          S9xGetByteLow
 658                 @  in  : rscratch (0x00hhmmll)
 659                 @  out : rscratch (0x000000ll)
 660                 STMFD   R13!,{PC}
 661                 B       asmS9xGetByte
 662                 MOV     R0,R0
 663 .endm
 664 .macro          S9xGetByteRegStatus     reg
 665                 @  in  : rscratch (0x00hhmmll)
 666                 @  out : reg      (0xll000000)
 667                 @  flags have to be updated with read value
 668                 STMFD   R13!,{PC} @ Push return address
 669                 B       asmS9xGetByte
 670                 MOV     R0,R0
 671                 MOVS    \reg, R0, LSL #24
 672 .endm
 673 .macro          S9xGetByteRegNS reg
 674                 @  in  : rscratch (0x00hhmmll)
 675                 @  out : reg      (0xll000000)
 676                 @  DOES NOT DESTROY rscratch (R0)
 677                 STMFD   R13!,{R0}
 678                 STMFD   R13!,{PC} @ Push return address
 679                 B       asmS9xGetByte
 680                 MOV     R0,R0
 681                 MOVS    \reg, R0, LSL #24
 682                 LDMFD   R13!,{R0}
 683 .endm
 684 .macro          S9xGetByteLowRegNS      reg
 685                 @  in  : rscratch (0x00hhmmll)
 686                 @  out : reg      (0x000000ll)
 687                 @  DOES NOT DESTROY rscratch (R0)
 688                 STMFD   R13!,{R0}
 689                 STMFD   R13!,{PC} @ Push return address
 690                 B       asmS9xGetByte
 691                 MOV     R0,R0
 692                 MOVS    \reg, R0
 693                 LDMFD   R13!,{R0}
 694 .endm
 695
 696 .macro          S9xSetWord      regValue
 697                 @  in  : regValue  (0xhhll0000)
 698                 @  in  : rscratch=address   (0x00hhmmll)
 699                 STMFD   R13!,{PC} @ Push return address
 700                 MOV     R1,\regValue, LSR #16
 701                 B       asmS9xSetWord
 702                 MOV     R0,R0
 703 .endm
 704 .macro          S9xSetWordZero
 705                 @  in  : rscratch=address   (0x00hhmmll)
 706                 STMFD   R13!,{PC} @ Push return address
 707                 MOV     R1,#0
 708                 B       asmS9xSetWord
 709                 MOV     R0,R0
 710 .endm
 711 .macro          S9xSetWordLow   regValue
 712                 @  in  : regValue  (0x0000hhll)
 713                 @  in  : rscratch=address   (0x00hhmmll)
 714                 STMFD   R13!,{PC} @ Push return address
 715                 MOV     R1,\regValue
 716                 B       asmS9xSetWord
 717                 MOV     R0,R0
 718 .endm
 719 .macro          S9xSetByte      regValue
 720                 @  in  : regValue  (0xll000000)
 721                 @  in  : rscratch=address   (0x00hhmmll)
 722                 STMFD   R13!,{PC} @ Push return address
 723                 MOV     R1,\regValue, LSR #24
 724                 B       asmS9xSetByte
 725                 MOV     R0,R0
 726 .endm
 727 .macro          S9xSetByteZero
 728                 @  in  : rscratch=address   (0x00hhmmll)
 729                 STMFD   R13!,{PC} @ Push return address
 730                 MOV     R1,#0
 731                 B       asmS9xSetByte
 732                 MOV     R0,R0
 733 .endm
 734 .macro          S9xSetByteLow   regValue
 735                 @  in  : regValue  (0x000000ll)
 736                 @  in  : rscratch=address   (0x00hhmmll)
 737                 STMFD   R13!,{PC} @ Push return address
 738                 MOV     R1,\regValue
 739                 B       asmS9xSetByte
 740                 MOV     R0,R0
 741 .endm
 742
 743
 744 @  ===========================================
 745 @  ===========================================
 746 @  Adressing mode
 747 @  ===========================================
 748 @  ===========================================
 749
 750
 751 .macro          Absolute
 752                 ADD2MEM
 753                 LDRB    rscratch2    , [rpc, #1]
 754                 LDRB    rscratch   , [rpc],#2
 755                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 756                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 757 .endm
 758 .macro          AbsoluteIndexedIndirectX0
 759                 ADD2MEM
 760                 LDRB    rscratch2    , [rpc, #1]
 761                 LDRB    rscratch   , [rpc], #2
 762                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 763                 ADD     rscratch    , reg_x, rscratch, LSL #16
 764                 MOV     rscratch , rscratch, LSR #16
 765                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 766                 S9xGetWordLow
 767
 768 .endm
 769 .macro          AbsoluteIndexedIndirectX1
 770                 ADD2MEM
 771                 LDRB    rscratch2    , [rpc, #1]
 772                 LDRB    rscratch   , [rpc], #2
 773                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 774                 ADD     rscratch    , rscratch, reg_x, LSR #24
 775                 BIC     rscratch , rscratch, #0x00FF0000
 776                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 777                 S9xGetWordLow
 778
 779 .endm
 780 .macro          AbsoluteIndirectLong
 781                 ADD2MEM
 782                 LDRB                    rscratch2    , [rpc, #1]
 783                 LDRB                    rscratch   , [rpc], #2
 784                 ORR                     rscratch    , rscratch, rscratch2, LSL #8
 785                 S9xGetWordLowRegNS      rscratch2
 786                 ADD                     rscratch   , rscratch,  #2
 787                 STMFD                   r13!,{rscratch2}
 788                 S9xGetByteLow
 789                 LDMFD                   r13!,{rscratch2}
 790                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 791 .endm
 792 .macro          AbsoluteIndirect
 793                 ADD2MEM
 794                 LDRB    rscratch2    , [rpc,#1]
 795                 LDRB    rscratch   , [rpc], #2
 796                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 797                 S9xGetWordLow
 798                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 799 .endm
 800 .macro          AbsoluteIndexedX0
 801                 ADD2MEM
 802                 LDRB    rscratch2    , [rpc, #1]
 803                 LDRB    rscratch   , [rpc], #2
 804                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 805                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 806                 ADD     rscratch    , rscratch, reg_x, LSR #16
 807 .endm
 808 .macro          AbsoluteIndexedX1
 809                 ADD2MEM
 810                 LDRB    rscratch2    , [rpc, #1]
 811                 LDRB    rscratch   , [rpc], #2
 812                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 813                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 814                 ADD     rscratch    , rscratch, reg_x, LSR #24
 815 .endm
 816
 817
 818 .macro          AbsoluteIndexedY0
 819                 ADD2MEM
 820                 LDRB    rscratch2    , [rpc, #1]
 821                 LDRB    rscratch   , [rpc], #2
 822                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 823                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 824                 ADD     rscratch    , rscratch, reg_y, LSR #16
 825 .endm
 826 .macro          AbsoluteIndexedY1
 827                 ADD2MEM
 828                 LDRB    rscratch2    , [rpc, #1]
 829                 LDRB    rscratch   , [rpc], #2
 830                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 831                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 832                 ADD     rscratch    , rscratch, reg_y, LSR #24
 833 .endm
 834 .macro          AbsoluteLong
 835                 ADD3MEM
 836                 LDRB    rscratch2    , [rpc, #1]
 837                 LDRB    rscratch   , [rpc], #2
 838                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 839                 LDRB    rscratch2   , [rpc], #1
 840                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 841 .endm
 842
 843
 844 .macro          AbsoluteLongIndexedX0
 845                 ADD3MEM
 846                 LDRB    rscratch2    , [rpc, #1]
 847                 LDRB    rscratch   , [rpc], #2
 848                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 849                 LDRB    rscratch2   , [rpc], #1
 850                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 851                 ADD     rscratch    , rscratch, reg_x, LSR #16
 852                 BIC     rscratch, rscratch, #0xFF000000
 853 .endm
 854 .macro          AbsoluteLongIndexedX1
 855                 ADD3MEM
 856                 LDRB    rscratch2    , [rpc, #1]
 857                 LDRB    rscratch   , [rpc], #2
 858                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 859                 LDRB    rscratch2   , [rpc], #1
 860                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 861                 ADD     rscratch    , rscratch, reg_x, LSR #24
 862                 BIC     rscratch, rscratch, #0xFF000000
 863 .endm
 864 .macro          Direct
 865                 ADD1MEM
 866                 LDRB    rscratch    , [rpc], #1
 867                 ADD     rscratch    , reg_d, rscratch, LSL #16
 868                 MOV     rscratch, rscratch, LSR #16
 869 .endm
 870 .macro          DirectIndirect
 871                 ADD1MEM
 872                 LDRB    rscratch    , [rpc], #1
 873                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 874                 MOV     rscratch, rscratch, LSR #16
 875                 S9xGetWordLow
 876                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 877 .endm
 878 .macro          DirectIndirectLong
 879                 ADD1MEM
 880                 LDRB                    rscratch    , [rpc], #1
 881                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 882                 MOV                     rscratch, rscratch, LSR #16
 883                 S9xGetWordLowRegNS      rscratch2
 884                 ADD                     rscratch    , rscratch,#2
 885                 STMFD                   r13!,{rscratch2}
 886                 S9xGetByteLow
 887                 LDMFD                   r13!,{rscratch2}
 888                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 889 .endm
 890 .macro          DirectIndirectIndexed0
 891                 ADD1MEM
 892                 LDRB    rscratch    , [rpc], #1
 893                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 894                 MOV     rscratch, rscratch, LSR #16
 895                 S9xGetWordLow
 896                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 897                 ADD     rscratch, rscratch,reg_y, LSR #16
 898 .endm
 899 .macro          DirectIndirectIndexed1
 900                 ADD1MEM
 901                 LDRB    rscratch    , [rpc], #1
 902                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 903                 MOV     rscratch, rscratch, LSR #16
 904                 S9xGetWordLow
 905                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 906                 ADD     rscratch, rscratch,reg_y, LSR #24
 907 .endm
 908 .macro          DirectIndirectIndexedLong0
 909                 ADD1MEM
 910                 LDRB                    rscratch    , [rpc], #1
 911                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 912                 MOV                     rscratch, rscratch, LSR #16
 913                 S9xGetWordLowRegNS      rscratch2
 914                 ADD                     rscratch    , rscratch,#2
 915                 STMFD                   r13!,{rscratch2}
 916                 S9xGetByteLow
 917                 LDMFD                   r13!,{rscratch2}
 918                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 919                 ADD                     rscratch, rscratch,reg_y, LSR #16
 920 .endm
 921 .macro          DirectIndirectIndexedLong1
 922                 ADD1MEM
 923                 LDRB                    rscratch    , [rpc], #1
 924                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 925                 MOV                     rscratch, rscratch, LSR #16
 926                 S9xGetWordLowRegNS      rscratch2
 927                 ADD                     rscratch    , rscratch,#2
 928                 STMFD                   r13!,{rscratch2}
 929                 S9xGetByteLow
 930                 LDMFD                   r13!,{rscratch2}
 931                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 932                 ADD                     rscratch, rscratch,reg_y, LSR #24
 933 .endm
 934 .macro          DirectIndexedIndirect0
 935                 ADD1CYCLE1MEM
 936                 LDRB    rscratch    , [rpc], #1
 937                 ADD     rscratch2   , reg_d , reg_x
 938                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 939                 MOV     rscratch, rscratch, LSR #16
 940                 S9xGetWordLow
 941                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 942 .endm
 943 .macro          DirectIndexedIndirect1
 944                 ADD1CYCLE1MEM
 945                 LDRB    rscratch    , [rpc], #1
 946                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 947                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 948                 MOV     rscratch, rscratch, LSR #16
 949                 S9xGetWordLow
 950                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 951 .endm
 952 .macro          DirectIndexedX0
 953                 ADD1CYCLE1MEM
 954                 LDRB    rscratch    , [rpc], #1
 955                 ADD     rscratch2   , reg_d , reg_x
 956                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 957                 MOV     rscratch, rscratch, LSR #16
 958 .endm
 959 .macro          DirectIndexedX1
 960                 ADD1CYCLE1MEM
 961                 LDRB    rscratch    , [rpc], #1
 962                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 963                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 964                 MOV     rscratch, rscratch, LSR #16
 965 .endm
 966 .macro          DirectIndexedY0
 967                 ADD1CYCLE1MEM
 968                 LDRB    rscratch    , [rpc], #1
 969                 ADD     rscratch2   , reg_d , reg_y
 970                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 971                 MOV     rscratch, rscratch, LSR #16
 972 .endm
 973 .macro          DirectIndexedY1
 974                 ADD1CYCLE1MEM
 975                 LDRB    rscratch    , [rpc], #1
 976                 ADD     rscratch2   , reg_d , reg_y, LSR #8
 977                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 978                 MOV     rscratch, rscratch, LSR #16
 979 .endm
 980 .macro          Immediate8
 981                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 982                 SUB     rscratch, rscratch, regpcbase
 983                 ADD     rpc, rpc, #1
 984 .endm
 985 .macro          Immediate16
 986                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 987                 SUB     rscratch, rscratch, regpcbase
 988                 ADD     rpc, rpc, #2
 989 .endm
 990 .macro          asmRelative
 991                 ADD1MEM
 992                 LDRSB   rscratch    , [rpc],#1
 993                 ADD     rscratch , rscratch , rpc
 994                 SUB     rscratch , rscratch, regpcbase
 995                 BIC     rscratch,rscratch,#0x00FF0000
 996                 BIC     rscratch,rscratch,#0xFF000000
 997 .endm
 998 .macro          asmRelativeLong
 999                 ADD1CYCLE2MEM
1000                 LDRB    rscratch2    , [rpc, #1]
1001                 LDRB    rscratch   , [rpc], #2
1002                 ORR     rscratch    , rscratch, rscratch2, LSL #8
1003                 SUB     rscratch2    , rpc, regpcbase
1004                 ADD     rscratch    , rscratch2, rscratch
1005                 BIC     rscratch,rscratch,#0x00FF0000
1006 .endm
1007
1008
1009 .macro          StackasmRelative
1010                 ADD1CYCLE1MEM
1011                 LDRB    rscratch    , [rpc], #1
1012                 ADD     rscratch    , rscratch, reg_s
1013                 BIC     rscratch,rscratch,#0x00FF0000
1014 .endm
1015 .macro          StackasmRelativeIndirectIndexed0
1016                 ADD2CYCLE1MEM
1017                 LDRB    rscratch    , [rpc], #1
1018                 ADD     rscratch    , rscratch, reg_s
1019                 BIC     rscratch,rscratch,#0x00FF0000
1020                 S9xGetWordLow
1021                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1022                 ADD     rscratch    , rscratch, reg_y, LSR #16
1023                 BIC     rscratch, rscratch, #0xFF000000
1024 .endm
1025 .macro          StackasmRelativeIndirectIndexed1
1026                 ADD2CYCLE1MEM
1027                 LDRB    rscratch    , [rpc], #1
1028                 ADD     rscratch    , rscratch, reg_s
1029                 BIC     rscratch,rscratch,#0x00FF0000
1030                 S9xGetWordLow
1031                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1032                 ADD     rscratch    , rscratch, reg_y, LSR #24
1033                 BIC     rscratch, rscratch, #0xFF000000
1034 .endm
1035
1036
1037 /****************************************/
1038 .macro          PushB           reg
1039                 MOV             rscratch,reg_s
1040                 S9xSetByte      \reg
1041                 SUB             reg_s,reg_s,#1
1042 .endm
1043 .macro          PushBLow        reg
1044                 MOV             rscratch,reg_s
1045                 S9xSetByteLow   \reg
1046                 SUB             reg_s,reg_s,#1
1047 .endm
1048 .macro          PushWLow        reg
1049                 SUB             rscratch,reg_s,#1
1050                 S9xSetWordLow   \reg
1051                 SUB             reg_s,reg_s,#2
1052 .endm
1053 .macro          PushWrLow
1054                 MOV             rscratch2,rscratch
1055                 SUB             rscratch,reg_s,#1
1056                 S9xSetWordLow   rscratch2
1057                 SUB             reg_s,reg_s,#2
1058 .endm
1059 .macro          PushW           reg
1060                 SUB             rscratch,reg_s,#1
1061                 S9xSetWord      \reg
1062                 SUB             reg_s,reg_s,#2
1063 .endm
1064
1065 /********/
1066
1067 .macro          PullB           reg
1068                 ADD             rscratch,reg_s,#1
1069                 S9xGetByteLow
1070                 ADD             reg_s,reg_s,#1
1071                 MOV             \reg,rscratch,LSL #24
1072 .endm
1073 .macro          PullBr
1074                 ADD             rscratch,reg_s,#1
1075                 S9xGetByte
1076                 ADD             reg_s,reg_s,#1
1077 .endm
1078 .macro          PullBLow        reg
1079                 ADD             rscratch,reg_s,#1
1080                 S9xGetByteLow
1081                 ADD             reg_s,reg_s,#1
1082                 MOV             \reg,rscratch
1083 .endm
1084 .macro          PullBrLow
1085                 ADD             rscratch,reg_s,#1
1086                 S9xGetByteLow
1087                 ADD             reg_s,reg_s,#1
1088 .endm
1089 .macro          PullW           reg
1090                 ADD             rscratch,reg_s,#1
1091                 S9xGetWordLow
1092                 ADD             reg_s,reg_s,#2
1093                 MOV             \reg,rscratch,LSL #16
1094 .endm
1095
1096 .macro          PullWLow        reg
1097                 ADD             rscratch,reg_s,#1
1098                 S9xGetWordLow
1099                 ADD             reg_s,reg_s,#2
1100                 MOV             \reg,rscratch
1101 .endm
1102
1103
1104 /*****************/
1105 .macro          PullBS          reg
1106                 ADD             rscratch,reg_s,#1
1107                 S9xGetByteLow
1108                 ADD             reg_s,reg_s,#1
1109                 MOVS            \reg,rscratch,LSL #24
1110 .endm
1111 .macro          PullBrS
1112                 ADD             rscratch,reg_s,#1
1113                 S9xGetByteLow
1114                 ADD             reg_s,reg_s,#1
1115                 MOVS            rscratch,rscratch,LSL #24
1116 .endm
1117 .macro          PullBLowS       reg
1118                 ADD             rscratch,reg_s,#1
1119                 S9xGetByteLow
1120                 ADD             reg_s,reg_s,#1
1121                 MOVS            \reg,rscratch
1122 .endm
1123 .macro          PullBrLowS
1124                 ADD             rscratch,reg_s,#1
1125                 S9xGetByteLow
1126                 ADD             reg_s,reg_s,#1
1127                 MOVS            rscratch,rscratch
1128 .endm
1129 .macro          PullWS          reg
1130                 ADD             rscratch,reg_s,#1
1131                 S9xGetWordLow
1132                 ADD             reg_s,reg_s,#2
1133                 MOVS            \reg,rscratch, LSL #16
1134 .endm
1135 .macro          PullWrS
1136                 ADD             rscratch,reg_s,#1
1137                 S9xGetWordLow
1138                 ADD             reg_s,reg_s,#2
1139                 MOVS            rscratch,rscratch, LSL #16
1140 .endm
1141 .macro          PullWLowS       reg
1142                 ADD             rscratch,reg_s,#1
1143                 S9xGetWordLow
1144                 ADD             reg_s,reg_s,#2
1145                 MOVS            \reg,rscratch
1146 .endm
1147 .macro          PullWrLowS
1148                 ADD             rscratch,reg_s,#1
1149                 S9xGetWordLow
1150                 ADD             reg_s,reg_s,#2
1151                 MOVS            rscratch,rscratch
1152 .endm
1153
1154
1155 .globl asmS9xGetByte
1156 .globl asmS9xGetWord
1157 .globl asmS9xSetByte
1158 .globl asmS9xSetWord
1159
1160 @ uint8 aaS9xGetByte(uint32 address);
1161 asmS9xGetByte:
1162         @  in : R0  = 0x00hhmmll
1163         @  out : R0 = 0x000000ll
1164         @  DESTROYED : R1,R2,R3
1165         @  UPDATE : reg_cycles
1166         @ R1 <= block
1167         MOV             R1,R0,LSR #MEMMAP_SHIFT
1168         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1169         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1170         @ so AND MEMMAP_MASK is BIC 0xFF000
1171         BIC             R1,R1,#0xFF000
1172         @ R2 <= Map[block] (GetAddress)
1173         LDR             R2,[reg_cpu_var,#Map_ofs]
1174         LDR             R2,[R2,R1,LSL #2]
1175         CMP             R2,#MAP_LAST
1176         BLO             GBSpecial  @ special
1177         @  Direct ROM/RAM acess
1178         @ R2 <= GetAddress + Address & 0xFFFF
1179         @ R3 <= MemorySpeed[block]
1180         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1181         MOV             R0,R0,LSL #16
1182         LDRB            R3,[R3,R1]
1183         ADD             R2,R2,R0,LSR #16
1184         @ Update CPU.Cycles
1185         ADD             reg_cycles,reg_cycles,R3
1186         @ R3 = BlockIsRAM[block]
1187         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1188         @ Get value to return
1189         LDRB            R0,[R2]
1190         LDRB            R3,[R3,R1]
1191         MOVS            R3,R3
1192         @  if BlockIsRAM => update for CPUShutdown
1193         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1194         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1195
1196         LDMFD           R13!,{PC} @ Return
1197 GBSpecial:
1198
1199         LDR             PC,[PC,R2,LSL #2]
1200         MOV             R0,R0           @ nop, for align
1201         .long GBPPU
1202         .long GBCPU
1203         .long GBDSP
1204         .long GBLSRAM
1205         .long GBHSRAM
1206         .long GBNONE
1207         .long GBDEBUG
1208         .long GBC4
1209         .long GBBWRAM
1210         .long GBNONE
1211         .long GBNONE
1212         .long GBNONE
1213         /*.long GB7ROM
1214         .long GB7RAM
1215         .long GB7SRM*/
1216 GBPPU:
1217         @ InDMA ?
1218         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1219         MOVS            R1,R1
1220         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1221         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1222         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1223         MOV             R0,R0,LSR #16
1224                 PREPARE_C_CALL
1225         BL              S9xGetPPU
1226                 RESTORE_C_CALL
1227         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1228         LDMFD           R13!,{PC} @ Return
1229 GBCPU:
1230         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1231         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1232         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1233         MOV             R0,R0,LSR #16
1234                 PREPARE_C_CALL
1235         BL              S9xGetCPU
1236                 RESTORE_C_CALL
1237         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1238         LDMFD           R13!,{PC} @ Return
1239 GBDSP:
1240         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1241         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1242         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1243         MOV             R0,R0,LSR #16
1244                 PREPARE_C_CALL
1245         BL              S9xGetDSP
1246                 RESTORE_C_CALL
1247         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1248         LDMFD           R13!,{PC} @ Return
1249 GBLSRAM:
1250         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1251         LDRH            R2,[reg_cpu_var,#SRAMMask]
1252         LDR             R1,[reg_cpu_var,#SRAM]
1253         AND             R0,R2,R0                @ Address&SRAMMask
1254         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1255         LDMFD           R13!,{PC}
1256 GB7SRM:
1257 GBHSRAM:
1258         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1259
1260         MOV             R1,R0,LSL #17
1261         AND             R2,R0,#0xF0000
1262         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1263         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1264         ADD             R0,R2,R1
1265         LDRH            R2,[reg_cpu_var,#SRAMMask]
1266         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1267         LDR             R1,[reg_cpu_var,#SRAM]
1268         AND             R0,R2,R0                @ Address&SRAMMask
1269         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1270         LDMFD           R13!,{PC}               @ return
1271 GB7ROM:
1272 GB7RAM:
1273 GBNONE:
1274         MOV             R0,R0,LSR #8
1275         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1276         AND             R0,R0,#0xFF
1277         LDMFD           R13!,{PC}
1278 @ GBDEBUG:
1279         /*ADD           reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1280         MOV             R0,#0
1281         LDMFD           R13!,{PC}*/
1282 GBC4:
1283         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1284         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1285         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1286         MOV             R0,R0,LSR #16
1287                 PREPARE_C_CALL
1288         BL              S9xGetC4
1289                 RESTORE_C_CALL
1290         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1291         LDMFD           R13!,{PC} @ Return
1292 GBDEBUG:
1293 GBBWRAM:
1294         MOV             R0,R0,LSL #17
1295         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1296         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1297         LDR             R1,[reg_cpu_var,#BWRAM]
1298         SUB             R0,R0,#0x6000   @ ((Address & 0x7fff) - 0x6000)
1299         LDRB            R0,[R0,R1]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1300         LDMFD           R13!,{PC}
1301
1302
1303 @ uint16 aaS9xGetWord(uint32 address);
1304 asmS9xGetWord:
1305         @  in : R0  = 0x00hhmmll
1306         @  out : R0 = 0x000000ll
1307         @  DESTROYED : R1,R2,R3
1308         @  UPDATE : reg_cycles
1309
1310
1311         MOV             R1,R0,LSL #19
1312         ADDS            R1,R1,#0x80000
1313         @ if = 0x1FFF => 0
1314         BNE             GW_NotBoundary
1315
1316         STMFD           R13!,{R0}
1317                 STMFD           R13!,{PC}
1318         B               asmS9xGetByte
1319                 MOV             R0,R0
1320         LDMFD           R13!,{R1}
1321         STMFD           R13!,{R0}
1322         ADD             R0,R1,#1
1323                 STMFD           R13!,{PC}
1324         B               asmS9xGetByte
1325                 MOV             R0,R0
1326         LDMFD           R13!,{R1}
1327         ORR             R0,R1,R0,LSL #8
1328         LDMFD           R13!,{PC}
1329
1330 GW_NotBoundary:
1331
1332         @ R1 <= block
1333         MOV             R1,R0,LSR #MEMMAP_SHIFT
1334         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1335         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1336         @ so AND MEMMAP_MASK is BIC 0xFF000
1337         BIC             R1,R1,#0xFF000
1338         @ R2 <= Map[block] (GetAddress)
1339         LDR             R2,[reg_cpu_var,#Map_ofs]
1340         LDR             R2,[R2,R1,LSL #2]
1341         CMP             R2,#MAP_LAST
1342         BLO             GWSpecial  @ special
1343         @  Direct ROM/RAM acess
1344
1345         TST             R0,#1
1346         BNE             GW_Not_Aligned1
1347         @ R2 <= GetAddress + Address & 0xFFFF
1348         @ R3 <= MemorySpeed[block]
1349         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1350         MOV             R0,R0,LSL #16
1351         LDRB            R3,[R3,R1]
1352         MOV             R0,R0,LSR #16
1353         @ Update CPU.Cycles
1354         ADD             reg_cycles,reg_cycles,R3, LSL #1
1355         @ R3 = BlockIsRAM[block]
1356         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1357         @ Get value to return
1358         LDRH            R0,[R2,R0]
1359         LDRB            R3,[R3,R1]
1360         MOVS            R3,R3
1361         @  if BlockIsRAM => update for CPUShutdown
1362         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1363         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1364
1365         LDMFD           R13!,{PC} @ Return
1366 GW_Not_Aligned1:
1367
1368         MOV             R0,R0,LSL #16
1369         ADD             R3,R0,#0x10000
1370         LDRB            R3,[R2,R3,LSR #16]      @ GetAddress+ (Address+1)&0xFFFF
1371         LDRB            R0,[R2,R0,LSR #16]      @ GetAddress+ Address&0xFFFF
1372         ORR             R0,R0,R3,LSL #8
1373
1374         @  if BlockIsRAM => update for CPUShutdown
1375         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1376         LDR             R2,[reg_cpu_var,#MemorySpeed_ofs]
1377         LDRB            R3,[R3,R1]   @ R3 = BlockIsRAM[block]
1378         LDRB            R2,[R2,R1]   @ R2 <= MemorySpeed[block]
1379         MOVS            R3,R3       @ IsRAM ? CPUShutdown stuff
1380         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1381         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1382         ADD             reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1383         LDMFD           R13!,{PC}  @ Return
1384 GWSpecial:
1385         LDR             PC,[PC,R2,LSL #2]
1386         MOV             R0,R0           @ nop, for align
1387         .long GWPPU
1388         .long GWCPU
1389         .long GWDSP
1390         .long GWLSRAM
1391         .long GWHSRAM
1392         .long GWNONE
1393         .long GWDEBUG
1394         .long GWC4
1395         .long GWBWRAM
1396         .long GWNONE
1397         .long GWNONE
1398         .long GWNONE
1399         /*.long GW7ROM
1400         .long GW7RAM
1401         .long GW7SRM*/
1402 /*      MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1403         MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1404         MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1405
1406 GWPPU:
1407         @ InDMA ?
1408         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1409         MOVS            R1,R1
1410         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1411         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1412         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1413         MOV             R0,R0,LSR #16
1414                 PREPARE_C_CALL_R0
1415         BL              S9xGetPPU
1416         LDMFD           R13!,{R1}
1417         STMFD           R13!,{R0}
1418         ADD             R0,R1,#1
1419         @ BIC           R0,R0,#0x10000
1420         BL              S9xGetPPU
1421                 RESTORE_C_CALL_R1
1422         ORR             R0,R1,R0,LSL #8
1423         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1424         LDMFD           R13!,{PC} @ Return
1425 GWCPU:
1426         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1427         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1428         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1429         MOV             R0,R0,LSR #16
1430                 PREPARE_C_CALL_R0
1431         BL              S9xGetCPU
1432         LDMFD           R13!,{R1}
1433         STMFD           R13!,{R0}
1434         ADD             R0,R1,#1
1435         @ BIC           R0,R0,#0x10000
1436         BL              S9xGetCPU
1437                 RESTORE_C_CALL_R1
1438         ORR             R0,R1,R0,LSL #8
1439         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1440         LDMFD           R13!,{PC} @ Return
1441 GWDSP:
1442         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1443         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1444         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1445         MOV             R0,R0,LSR #16
1446                 PREPARE_C_CALL_R0
1447         BL              S9xGetDSP
1448         LDMFD           R13!,{R1}
1449         STMFD           R13!,{R0}
1450         ADD             R0,R1,#1
1451         @ BIC           R0,R0,#0x10000
1452         BL              S9xGetDSP
1453                 RESTORE_C_CALL_R1
1454         ORR             R0,R1,R0,LSL #8
1455         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1456         LDMFD           R13!,{PC} @ Return
1457 GWLSRAM:
1458         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1459
1460         TST             R0,#1
1461         BNE             GW_Not_Aligned2
1462         LDRH            R2,[reg_cpu_var,#SRAMMask]
1463         LDR             R1,[reg_cpu_var,#SRAM]
1464         AND             R3,R2,R0                @ Address&SRAMMask
1465         LDRH            R0,[R3,R1]              @ *Memory.SRAM + Address&SRAMMask
1466         LDMFD           R13!,{PC}       @ return
1467 GW_Not_Aligned2:
1468         LDRH            R2,[reg_cpu_var,#SRAMMask]
1469         LDR             R1,[reg_cpu_var,#SRAM]
1470         AND             R3,R2,R0                @ Address&SRAMMask
1471         ADD             R0,R0,#1
1472         AND             R2,R0,R2                @ Address&SRAMMask
1473         LDRB            R3,[R1,R3]              @ *Memory.SRAM + Address&SRAMMask
1474         LDRB            R2,[R1,R2]              @ *Memory.SRAM + Address&SRAMMask
1475         ORR             R0,R3,R2,LSL #8
1476         LDMFD           R13!,{PC}       @ return
1477 GW7SRM:
1478 GWHSRAM:
1479         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1480
1481         TST             R0,#1
1482         BNE             GW_Not_Aligned3
1483
1484         MOV             R1,R0,LSL #17
1485         AND             R2,R0,#0xF0000
1486         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1487         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1488         ADD             R0,R2,R1
1489         LDRH            R2,[reg_cpu_var,#SRAMMask]
1490         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1491         LDR             R1,[reg_cpu_var,#SRAM]
1492         AND             R0,R2,R0                @ Address&SRAMMask
1493         LDRH            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1494         LDMFD           R13!,{PC}               @ return
1495
1496 GW_Not_Aligned3:
1497         MOV             R3,R0,LSL #17
1498         AND             R2,R0,#0xF0000
1499         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1500         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1501         ADD             R2,R2,R3
1502         ADD             R0,R0,#1
1503         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1504         MOV             R3,R0,LSL #17
1505         AND             R0,R0,#0xF0000
1506         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1507         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1508         ADD             R0,R0,R3
1509         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1510         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1511         AND             R2,R3,R2                @ Address...&SRAMMask
1512         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1513
1514         LDR             R3,[reg_cpu_var,#SRAM]
1515         LDRB            R0,[R0,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1516         LDRB            R2,[R2,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1517         ORR             R0,R2,R0,LSL #8
1518
1519         LDMFD           R13!,{PC}               @ return
1520 GW7ROM:
1521 GW7RAM:
1522 GWNONE:
1523         MOV             R0,R0,LSL #16
1524         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1525         MOV             R0,R0,LSR #24
1526         ORR             R0,R0,R0,LSL #8
1527         LDMFD           R13!,{PC}
1528 GWDEBUG:
1529         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1530         MOV             R0,#0
1531         LDMFD           R13!,{PC}
1532 GWC4:
1533         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1534         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1535         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1536         MOV             R0,R0,LSR #16
1537                 PREPARE_C_CALL_R0
1538         BL              S9xGetC4
1539         LDMFD           R13!,{R1}
1540         STMFD           R13!,{R0}
1541         ADD             R0,R1,#1
1542         @ BIC           R0,R0,#0x10000
1543         BL              S9xGetC4
1544                 RESTORE_C_CALL_R1
1545         ORR             R0,R1,R0,LSL #8
1546         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1547         LDMFD           R13!,{PC} @ Return
1548 GWBWRAM:
1549         TST             R0,#1
1550         BNE             GW_Not_Aligned4
1551         MOV             R0,R0,LSL #17
1552         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1553         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1554         LDR             R1,[reg_cpu_var,#BWRAM]
1555         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1556         LDRH            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1557         LDMFD           R13!,{PC}               @ return
1558 GW_Not_Aligned4:
1559         MOV             R0,R0,LSL #17
1560         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1561         ADD             R3,R0,#0x20000
1562         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1563         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1564         LDR             R1,[reg_cpu_var,#BWRAM]
1565         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1566         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1567         LDRB            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1568         LDRB            R3,[R1,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1569         ORR             R0,R0,R3,LSL #8
1570         LDMFD           R13!,{PC}               @ return
1571
1572
1573
1574
1575 @ void aaS9xSetByte(uint32 address,uint8 val);
1576 asmS9xSetByte:
1577         @  in : R0=0x00hhmmll  R1=0x000000ll
1578         @  DESTROYED : R0,R1,R2,R3
1579         @  UPDATE : reg_cycles
1580         @ cpu shutdown
1581         MOV             R2,#0
1582         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1583         @
1584
1585         @ R3 <= block
1586         MOV             R3,R0,LSR #MEMMAP_SHIFT
1587         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1588         @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1589         @ so AND MEMMAP_MASK is BIC 0xFF000
1590         BIC             R3,R3,#0xFF000
1591         @ R2 <= Map[block] (SetAddress)
1592         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1593         LDR             R2,[R2,R3,LSL #2]
1594         CMP             R2,#MAP_LAST
1595         BLO             SBSpecial  @ special
1596         @  Direct ROM/RAM acess
1597
1598         @ R2 <= SetAddress + Address & 0xFFFF
1599         MOV             R0,R0,LSL #16
1600         ADD             R2,R2,R0,LSR #16
1601         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1602         @ Set byte
1603         STRB            R1,[R2]
1604         @ R0 <= MemorySpeed[block]
1605         LDRB            R0,[R0,R3]
1606         @ Update CPU.Cycles
1607         ADD             reg_cycles,reg_cycles,R0
1608         @ CPUShutdown
1609         @ only SA1 here : TODO
1610         @ Return
1611         LDMFD           R13!,{PC}
1612 SBSpecial:
1613         LDR             PC,[PC,R2,LSL #2]
1614         MOV             R0,R0           @ nop, for align
1615         .long SBPPU
1616         .long SBCPU
1617         .long SBDSP
1618         .long SBLSRAM
1619         .long SBHSRAM
1620         .long SBNONE
1621         .long SBDEBUG
1622         .long SBC4
1623         .long SBBWRAM
1624         .long SBNONE
1625         .long SBNONE
1626         .long SBNONE
1627         /*.long SB7ROM
1628         .long SB7RAM
1629         .long SB7SRM*/
1630 SBPPU:
1631         @ InDMA ?
1632         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1633         MOVS            R2,R2
1634         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1635         MOV             R0,R0,LSL #16
1636         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1637         MOV             R0,R0,LSR #16
1638                 PREPARE_C_CALL
1639         MOV             R12,R0
1640         MOV             R0,R1
1641         MOV             R1,R12
1642         BL              S9xSetPPU
1643                 RESTORE_C_CALL
1644         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1645         LDMFD           R13!,{PC} @ Return
1646 SBCPU:
1647         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1648         MOV             R0,R0,LSL #16
1649         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1650         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1651                 PREPARE_C_CALL
1652         MOV             R12,R0
1653         MOV             R0,R1
1654         MOV             R1,R12
1655         BL              S9xSetCPU
1656                 RESTORE_C_CALL
1657         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1658         LDMFD           R13!,{PC} @ Return
1659 SBDSP:
1660         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1661         MOV             R0,R0,LSL #16
1662         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1663         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1664                 PREPARE_C_CALL
1665         MOV             R12,R0
1666         MOV             R0,R1
1667         MOV             R1,R12
1668         BL              S9xSetDSP
1669                 RESTORE_C_CALL
1670         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1671         LDMFD           R13!,{PC} @ Return
1672 SBLSRAM:
1673         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1674         LDRH            R2,[reg_cpu_var,#SRAMMask]
1675         MOVS            R2,R2
1676         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1677         LDR             R3,[reg_cpu_var,#SRAM]
1678         AND             R0,R2,R0                @ Address&SRAMMask
1679         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1680
1681         MOV             R0,#1
1682         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1683         LDMFD           R13!,{PC}  @ return
1684 SB7SRM:
1685 SBHSRAM:
1686         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1687
1688         MOV             R3,R0,LSL #17
1689         AND             R2,R0,#0xF0000
1690         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1691         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1692         ADD             R0,R2,R3
1693
1694         LDRH            R2,[reg_cpu_var,#SRAMMask]
1695         MOVS            R2,R2
1696         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1697
1698         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1699         LDR             R3,[reg_cpu_var,#SRAM]
1700         AND             R0,R2,R0                @ Address&SRAMMask
1701         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1702
1703         MOV             R0,#1
1704         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1705         LDMFD           R13!,{PC}       @ return
1706 SB7ROM:
1707 SB7RAM:
1708 SBNONE:
1709 SBDEBUG:
1710         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1711         LDMFD           R13!,{PC}
1712 SBC4:
1713         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1714         MOV             R0,R0,LSL #16
1715         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1716         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1717                 PREPARE_C_CALL
1718         MOV             R12,R0
1719         MOV             R0,R1
1720         MOV             R1,R12
1721         BL              S9xSetC4
1722                 RESTORE_C_CALL
1723         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1724         LDMFD           R13!,{PC} @ Return
1725 SBBWRAM:
1726         MOV             R0,R0,LSL #17
1727         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1728         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1729         LDR             R2,[reg_cpu_var,#BWRAM]
1730         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1731         STRB            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1732
1733         MOV             R0,#1
1734         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1735
1736         LDMFD           R13!,{PC}
1737
1738
1739
1740 @ void aaS9xSetWord(uint32 address,uint16 val);
1741 asmS9xSetWord:
1742         @  in : R0  = 0x00hhmmll R1=0x0000hhll
1743         @  DESTROYED : R0,R1,R2,R3
1744         @  UPDATE : reg_cycles
1745         @ R1 <= block
1746
1747         MOV             R2,R0,LSL #19
1748         ADDS            R2,R2,#0x80000
1749         @ if = 0x1FFF => 0
1750         BNE             SW_NotBoundary
1751
1752         STMFD           R13!,{R0,R1}
1753                 STMFD           R13!,{PC}
1754         B               asmS9xSetByte
1755                 MOV             R0,R0
1756         LDMFD           R13!,{R0,R1}
1757         ADD             R0,R0,#1
1758         MOV             R1,R1,LSR #8
1759                 STMFD           R13!,{PC}
1760         B               asmS9xSetByte
1761                 MOV             R0,R0
1762
1763         LDMFD           R13!,{PC}
1764
1765 SW_NotBoundary:
1766
1767         MOV             R2,#0
1768         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1769         @
1770         @ R3 <= block
1771         MOV             R3,R0,LSR #MEMMAP_SHIFT
1772         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1773         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1774         @ so AND MEMMAP_MASK is BIC 0xFF000
1775         BIC             R3,R3,#0xFF000
1776         @ R2 <= Map[block] (SetAddress)
1777         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1778         LDR             R2,[R2,R3,LSL #2]
1779         CMP             R2,#MAP_LAST
1780         BLO             SWSpecial  @ special
1781         @  Direct ROM/RAM acess
1782
1783
1784         @ check if address is 16bits aligned or not
1785         TST             R0,#1
1786         BNE             SW_not_aligned1
1787         @ aligned
1788         MOV             R0,R0,LSL #16
1789         ADD             R2,R2,R0,LSR #16        @ address & 0xFFFF + SetAddress
1790         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1791         @ Set word
1792         STRH            R1,[R2]
1793         @ R1 <= MemorySpeed[block]
1794         LDRB            R0,[R0,R3]
1795         @ Update CPU.Cycles
1796         ADD             reg_cycles,reg_cycles,R0, LSL #1
1797         @ CPUShutdown
1798         @ only SA1 here : TODO
1799         @ Return
1800         LDMFD           R13!,{PC}
1801
1802 SW_not_aligned1:
1803         @ R1 = (Address&0xFFFF)<<16
1804         MOV             R0,R0,LSL #16
1805         @ First write @address
1806         STRB            R1,[R2,R0,LSR #16]
1807         ADD             R0,R0,#0x10000
1808         MOV             R1,R1,LSR #8
1809         @ Second write @address+1
1810         STRB            R1,[R2,R0,LSR #16]
1811         @ R1 <= MemorySpeed[block]
1812         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1813         LDRB            R0,[R0,R3]
1814         @ Update CPU.Cycles
1815         ADD             reg_cycles,reg_cycles,R0,LSL #1
1816         @ CPUShutdown
1817         @ only SA1 here : TODO
1818         @ Return
1819         LDMFD           R13!,{PC}
1820 SWSpecial:
1821         LDR             PC,[PC,R2,LSL #2]
1822         MOV             R0,R0           @ nop, for align
1823         .long SWPPU
1824         .long SWCPU
1825         .long SWDSP
1826         .long SWLSRAM
1827         .long SWHSRAM
1828         .long SWNONE
1829         .long SWDEBUG
1830         .long SWC4
1831         .long SWBWRAM
1832         .long SWNONE
1833         .long SWNONE
1834         .long SWNONE
1835         /*.long SW7ROM
1836         .long SW7RAM
1837         .long SW7SRM*/
1838 SWPPU:
1839         @ InDMA ?
1840         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1841         MOVS            R2,R2
1842         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1843         MOV             R0,R0,LSL #16
1844         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1845         MOV             R0,R0,LSR #16
1846         MOV             R2,R1
1847         MOV             R1,R0
1848         MOV             R0,R2
1849                 PREPARE_C_CALL_R0R1
1850         BL              S9xSetPPU
1851         LDMFD           R13!,{R0,R1}
1852         ADD             R1,R1,#1
1853         MOV             R0,R0,LSR #8
1854         BIC             R1,R1,#0x10000
1855         BL              S9xSetPPU
1856                 RESTORE_C_CALL
1857         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1858         LDMFD           R13!,{PC} @ Return
1859 SWCPU:
1860         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1861         MOV             R0,R0,LSL #16
1862         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1863         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1864         MOV             R2,R1
1865         MOV             R1,R0
1866         MOV             R0,R2
1867                 PREPARE_C_CALL_R0R1
1868         BL              S9xSetCPU
1869         LDMFD           R13!,{R0,R1}
1870         ADD             R1,R1,#1
1871         MOV             R0,R0,LSR #8
1872         BIC             R1,R1,#0x10000
1873         BL              S9xSetCPU
1874                 RESTORE_C_CALL
1875         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1876         LDMFD           R13!,{PC} @ Return
1877 SWDSP:
1878         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1879         MOV             R0,R0,LSL #16
1880         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1881         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1882         MOV             R2,R1
1883         MOV             R1,R0
1884         MOV             R0,R2
1885                 PREPARE_C_CALL_R0R1
1886         BL              S9xSetDSP
1887         LDMFD           R13!,{R0,R1}
1888         ADD             R1,R1,#1
1889         MOV             R0,R0,LSR #8
1890         BIC             R1,R1,#0x10000
1891         BL              S9xSetDSP
1892                 RESTORE_C_CALL
1893         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1894         LDMFD           R13!,{PC} @ Return
1895 SWLSRAM:
1896         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1897         LDRH            R2,[reg_cpu_var,#SRAMMask]
1898         MOVS            R2,R2
1899         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1900
1901         AND             R3,R2,R0                @ Address&SRAMMask
1902         TST             R0,#1
1903         BNE             SW_not_aligned2
1904         @ aligned
1905         LDR             R0,[reg_cpu_var,#SRAM]
1906         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1907         MOV             R0,#1
1908         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1909         LDMFD           R13!,{PC}  @ return
1910 SW_not_aligned2:
1911
1912         ADD             R0,R0,#1
1913         AND             R2,R2,R0                @ (Address+1)&SRAMMask
1914         LDR             R0,[reg_cpu_var,#SRAM]
1915         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1916         MOV             R1,R1,LSR #8
1917         STRB            R1,[R0,R2]              @ *Memory.SRAM + (Address+1)&SRAMMask
1918         MOV             R0,#1
1919         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1920         LDMFD           R13!,{PC}  @ return
1921 SW7SRM:
1922 SWHSRAM:
1923         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1924
1925         LDRH            R2,[reg_cpu_var,#SRAMMask]
1926         MOVS            R2,R2
1927         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1928
1929         TST             R0,#1
1930         BNE             SW_not_aligned3
1931         @ aligned
1932         MOV             R3,R0,LSL #17
1933         AND             R2,R0,#0xF0000
1934         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1935         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1936         ADD             R0,R2,R3
1937         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1938         LDRH            R2,[reg_cpu_var,#SRAMMask]
1939         LDR             R3,[reg_cpu_var,#SRAM]
1940         AND             R0,R2,R0                @ Address&SRAMMask
1941         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1942         MOV             R0,#1
1943         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1944         LDMFD           R13!,{PC}       @ return
1945 SW_not_aligned3:
1946         MOV             R3,R0,LSL #17
1947         AND             R2,R0,#0xF0000
1948         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1949         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1950         ADD             R2,R2,R3
1951         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1952
1953         ADD             R0,R0,#1
1954         MOV             R3,R0,LSL #17
1955         AND             R0,R0,#0xF0000
1956         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1957         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1958         ADD             R0,R0,R3
1959         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1960         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1961         AND             R2,R3,R2                @ Address...&SRAMMask
1962         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1963
1964         LDR             R3,[reg_cpu_var,#SRAM]
1965         STRB            R1,[R2,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1966         MOV             R1,R1,LSR #8
1967         STRB            R1,[R0,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1968
1969         MOV             R0,#1
1970         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1971         LDMFD           R13!,{PC}       @ return
1972 SW7ROM:
1973 SW7RAM:
1974 SWNONE:
1975 SWDEBUG:
1976         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1977         LDMFD           R13!,{PC}       @ return
1978 SWC4:
1979         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1980         MOV             R0,R0,LSL #16
1981         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1982         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1983         MOV             R2,R1
1984         MOV             R1,R0
1985         MOV             R0,R2
1986                 PREPARE_C_CALL_R0R1
1987         BL              S9xSetC4
1988         LDMFD           R13!,{R0,R1}
1989         ADD             R1,R1,#1
1990         MOV             R0,R0,LSR #8
1991         BIC             R1,R1,#0x10000
1992         BL              S9xSetC4
1993                 RESTORE_C_CALL
1994         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1995         LDMFD           R13!,{PC} @ Return
1996 SWBWRAM:
1997         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1998         TST             R0,#1
1999         BNE             SW_not_aligned4
2000         @ aligned
2001         MOV             R0,R0,LSL #17
2002         LDR             R2,[reg_cpu_var,#BWRAM]
2003         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2004         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2005         MOV             R3,#1
2006         STRH            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2007         STRB            R3,[reg_cpu_var,#SRAMModified_ofs]
2008         LDMFD           R13!,{PC}       @ return
2009 SW_not_aligned4:
2010         MOV             R0,R0,LSL #17
2011         ADD             R3,R0,#0x20000
2012         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2013         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
2014         LDR             R2,[reg_cpu_var,#BWRAM]
2015         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2016         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2017         STRB            R1,[R2,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2018         MOV             R1,R1,LSR #8
2019         STRB            R1,[R2,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2020         MOV             R0,#1
2021         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
2022         LDMFD           R13!,{PC}               @ return
2023
2024
2025
2026
2027
2028 /*****************************************************************
2029         FLAGS
2030 *****************************************************************/
2031
2032 .macro          UPDATE_C
2033                 @  CC : ARM Carry Clear
2034                 BICCC   rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2035                 @  CS : ARM Carry Set
2036                 ORRCS   rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2037 .endm
2038 .macro          UPDATE_Z
2039                 @  NE : ARM Zero Clear
2040                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2041                 @  EQ : ARM Zero Set
2042                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2043 .endm
2044 .macro          UPDATE_ZN
2045                 @  NE : ARM Zero Clear
2046                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2047                 @  EQ : ARM Zero Set
2048                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2049                 @  PL : ARM Neg Clear
2050                 BICPL   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2051                 @  MI : ARM Neg Set
2052                 ORRMI   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2053 .endm
2054
2055 /*****************************************************************
2056         OPCODES_MAC
2057 *****************************************************************/
2058
2059
2060
2061
2062 .macro ADC8
2063                 TST rstatus, #MASK_DECIMAL
2064                 BEQ 1111f
2065                 S9xGetByte
2066
2067
2068                 STMFD   R13!,{rscratch}
2069                 MOV     rscratch4,#0x0F000000
2070                 @ rscratch2=xxW1xxxxxxxxxxxx
2071                 AND     rscratch2, rscratch, rscratch4
2072                 @ rscratch=xxW2xxxxxxxxxxxx
2073                 AND     rscratch, rscratch4, rscratch, LSR #4
2074                 @ rscratch3=xxA2xxxxxxxxxxxx
2075                 AND     rscratch3, rscratch4, reg_a, LSR #4
2076                 @ rscratch4=xxA1xxxxxxxxxxxx
2077                 AND     rscratch4,reg_a,rscratch4
2078                 @ R1=A1+W1+CARRY
2079                 TST     rstatus, #MASK_CARRY
2080                 ADDNE   rscratch2, rscratch2, #0x01000000
2081                 ADD     rscratch2,rscratch2,rscratch4
2082                 @  if R1 > 9
2083                 CMP     rscratch2, #0x09000000
2084                 @  then R1 -= 10
2085                 SUBGT   rscratch2, rscratch2, #0x0A000000
2086                 @  then A2++
2087                 ADDGT   rscratch3, rscratch3, #0x01000000
2088                 @  R2 = A2+W2
2089                 ADD     rscratch3, rscratch3, rscratch
2090                 @  if R2 > 9
2091                 CMP     rscratch3, #0x09000000
2092                 @  then R2 -= 10@
2093                 SUBGT   rscratch3, rscratch3, #0x0A000000
2094                 @  then SetCarry()
2095                 ORRGT   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2096                 @  else ClearCarry()
2097                 BICLE   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2098                 @  gather rscratch3 and rscratch2 into ans8
2099                 @  rscratch3 : 0R2000000
2100                 @  rscratch2 : 0R1000000
2101                 @  -> 0xR2R1000000
2102                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2103                 LDMFD   R13!,{rscratch}
2104                 @ only last bit
2105                 AND     rscratch,rscratch,#0x80000000
2106                 @  (register.AL ^ Work8)
2107                 EORS    rscratch3, reg_a, rscratch
2108                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2109                 BNE     1112f
2110                 @  (Work8 ^ Ans8)
2111                 EORS    rscratch3, rscratch2, rscratch
2112                 @  & 0x80
2113                 TSTNE   rscratch3,#0x80000000
2114                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2115                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2116 1112:
2117                 MOVS reg_a, rscratch2
2118                 UPDATE_ZN
2119                 B 1113f
2120 1111:
2121                 S9xGetByteLow
2122                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2123                 SUBCS rscratch, rscratch, #0x100
2124                 ADCS reg_a, reg_a, rscratch, ROR #8
2125                 @ OverFlow
2126                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2127                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2128                 @ Carry
2129                 UPDATE_C
2130                 @ clear lower part
2131                 ANDS reg_a, reg_a, #0xFF000000
2132                 @ Update flag
2133                 UPDATE_ZN
2134 1113:
2135 .endm
2136 /* TO TEST */
2137 .macro ADC16
2138                 TST rstatus, #MASK_DECIMAL
2139                 BEQ 1111f
2140                 S9xGetWord
2141
2142                 @ rscratch = W3W2W1W0........
2143                 LDR     rscratch4, = 0x0F0F0000
2144                 @  rscratch2 = xxW2xxW0xxxxxx
2145                 @  rscratch3 = xxW3xxW1xxxxxx
2146                 AND     rscratch2, rscratch4, rscratch
2147                 AND     rscratch3, rscratch4, rscratch, LSR #4
2148                 @  rscratch2 = xxW3xxW1xxW2xxW0
2149                 ORR     rscratch2, rscratch3, rscratch2, LSR #16
2150                 @  rscratch3 = xxA2xxA0xxxxxx
2151                 @  rscratch4 = xxA3xxA1xxxxxx
2152                 @  rscratch2 = xxA3xxA1xxA2xxA0
2153                 AND     rscratch3, rscratch4, reg_a
2154                 AND     rscratch4, rscratch4, reg_a, LSR #4
2155                 ORR     rscratch3, rscratch4, rscratch3, LSR #16
2156                 ADD     rscratch2, rscratch3, rscratch2
2157                 LDR     rscratch4, = 0x0F0F0000
2158                 @  rscratch2 = A + W
2159                 TST     rstatus, #MASK_CARRY
2160                 ADDNE   rscratch2, rscratch2, #0x1
2161                 @  rscratch2 = A + W + C
2162                 @ A0
2163                 AND     rscratch3, rscratch2, #0x0000001F
2164                 CMP     rscratch3, #0x00000009
2165                 ADDHI   rscratch2, rscratch2, #0x00010000
2166                 SUBHI   rscratch2, rscratch2, #0x0000000A
2167                 @ A1
2168                 AND     rscratch3, rscratch2, #0x001F0000
2169                 CMP     rscratch3, #0x00090000
2170                 ADDHI   rscratch2, rscratch2, #0x00000100
2171                 SUBHI   rscratch2, rscratch2, #0x000A0000
2172                 @ A2
2173                 AND     rscratch3, rscratch2, #0x00001F00
2174                 CMP     rscratch3, #0x00000900
2175                 SUBHI   rscratch2, rscratch2, #0x00000A00
2176                 ADDHI   rscratch2, rscratch2, #0x01000000
2177                 @ A3
2178                 AND     rscratch3, rscratch2, #0x1F000000
2179                 CMP     rscratch3, #0x09000000
2180                 SUBHI   rscratch2, rscratch2, #0x0A000000
2181                 @ SetCarry
2182                 ORRHI   rstatus, rstatus, #MASK_CARRY
2183                 @ ClearCarry
2184                 BICLS   rstatus, rstatus, #MASK_CARRY
2185                 @ rscratch2 = xxR3xxR1xxR2xxR0
2186                 @ Pack result
2187                 @ rscratch3 = xxR3xxR1xxxxxxxx
2188                 AND     rscratch3, rscratch4, rscratch2
2189                 @ rscratch2 = xxR2xxR0xxxxxxxx
2190                 AND     rscratch2, rscratch4, rscratch2,LSL #16
2191                 @ rscratch2 = R3R2R1R0xxxxxxxx
2192                 ORR     rscratch2, rscratch2,rscratch3,LSL #4
2193 @ only last bit
2194                 AND     rscratch,rscratch,#0x80000000
2195                 @  (register.AL ^ Work8)
2196                 EORS    rscratch3, reg_a, rscratch
2197                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2198                 BNE     1112f
2199                 @  (Work8 ^ Ans8)
2200                 EORS    rscratch3, rscratch2, rscratch
2201                 TSTNE   rscratch3,#0x80000000
2202                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2203                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2204 1112:
2205                 MOVS    reg_a, rscratch2
2206                 UPDATE_ZN
2207                 B       1113f
2208 1111:
2209                 S9xGetWordLow
2210                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2211                 SUBCS rscratch, rscratch, #0x10000
2212                 ADCS reg_a, reg_a,rscratch, ROR #16
2213                 @ OverFlow
2214                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2215                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2216                 MOV reg_a, reg_a, LSR #16
2217                 @ Carry
2218                 UPDATE_C
2219                 @ clear lower parts
2220                 MOVS reg_a, reg_a, LSL #16
2221                 @ Update flag
2222                 UPDATE_ZN
2223 1113:
2224 .endm
2225
2226
2227 .macro          AND16
2228                 S9xGetWord
2229                 ANDS            reg_a, reg_a, rscratch
2230                 UPDATE_ZN
2231 .endm
2232 .macro          AND8
2233                 S9xGetByte
2234                 ANDS            reg_a, reg_a, rscratch
2235                 UPDATE_ZN
2236 .endm
2237 .macro          A_ASL8
2238                 @  7    instr
2239                 MOVS    reg_a, reg_a, LSL #1
2240                 UPDATE_C
2241                 UPDATE_ZN
2242                 ADD1CYCLE
2243 .endm
2244 .macro          A_ASL16
2245                 @  7    instr
2246                 MOVS    reg_a, reg_a, LSL #1
2247                 UPDATE_C
2248                 UPDATE_ZN
2249                 ADD1CYCLE
2250 .endm
2251 .macro          ASL16
2252                 S9xGetWordRegNS rscratch2             @         do not destroy Opadress in rscratch
2253                 MOVS            rscratch2, rscratch2, LSL #1
2254                 UPDATE_C
2255                 UPDATE_ZN
2256                 S9xSetWord      rscratch2
2257                 ADD1CYCLE
2258 .endm
2259 .macro          ASL8
2260                 S9xGetByteRegNS rscratch2             @         do not destroy Opadress in rscratch
2261                 MOVS            rscratch2, rscratch2, LSL #1
2262                 UPDATE_C
2263                 UPDATE_ZN
2264                 S9xSetByte      rscratch2
2265                 ADD1CYCLE
2266 .endm
2267 .macro          BIT8
2268                 S9xGetByte
2269                 MOVS    rscratch2, rscratch, LSL #1
2270                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2271                 @                                         ARM N = Snes V
2272                 @  If Carry Set, then Set Neg in SNES
2273                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set C to zero
2274                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set C to one
2275                 @  If Neg Set, then Set Overflow in SNES
2276                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set N to zero
2277                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set N to one
2278
2279                 @  Now do a real AND    with A register
2280                 @  Set Zero Flag, bit test
2281                 ANDS    rscratch2, reg_a, rscratch
2282                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2283                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2284 .endm
2285
2286 .macro          BIT16
2287                 S9xGetWord
2288                 MOVS    rscratch2, rscratch, LSL #1
2289                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2290                 @                                         ARM N = Snes V
2291                 @  If Carry Set, then Set Neg in SNES
2292                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2293                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2294                 @  If Neg Set, then Set Overflow in SNES
2295                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set V to zero
2296                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set V to one
2297                 @  Now do a real AND    with A register
2298                 @  Set Zero Flag, bit test
2299                 ANDS    rscratch2, reg_a, rscratch
2300                 @  Bit set  ->Z=0->xxxNE Clear flag
2301                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2302                 @  Bit clear->Z=1->xxxEQ Set flag
2303                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2304 .endm
2305 .macro          CMP8
2306                 S9xGetByte
2307                 SUBS    rscratch2,reg_a,rscratch
2308                 BICCC   rstatus, rstatus, #MASK_CARRY
2309                 ORRCS   rstatus, rstatus, #MASK_CARRY
2310                 UPDATE_ZN
2311
2312 .endm
2313 .macro          CMP16
2314                 S9xGetWord
2315                 SUBS    rscratch2,reg_a,rscratch
2316                 BICCC   rstatus, rstatus, #MASK_CARRY
2317                 ORRCS   rstatus, rstatus, #MASK_CARRY
2318                 UPDATE_ZN
2319
2320 .endm
2321 .macro          CMX16
2322                 S9xGetWord
2323                 SUBS    rscratch2,reg_x,rscratch
2324                 BICCC   rstatus, rstatus, #MASK_CARRY
2325                 ORRCS   rstatus, rstatus, #MASK_CARRY
2326                 UPDATE_ZN
2327 .endm
2328 .macro          CMX8
2329                 S9xGetByte
2330                 SUBS    rscratch2,reg_x,rscratch
2331                 BICCC   rstatus, rstatus, #MASK_CARRY
2332                 ORRCS   rstatus, rstatus, #MASK_CARRY
2333                 UPDATE_ZN
2334 .endm
2335 .macro          CMY16
2336                 S9xGetWord
2337                 SUBS    rscratch2,reg_y,rscratch
2338                 BICCC   rstatus, rstatus, #MASK_CARRY
2339                 ORRCS   rstatus, rstatus, #MASK_CARRY
2340                 UPDATE_ZN
2341 .endm
2342 .macro          CMY8
2343                 S9xGetByte
2344                 SUBS    rscratch2,reg_y,rscratch
2345                 BICCC   rstatus, rstatus, #MASK_CARRY
2346                 ORRCS   rstatus, rstatus, #MASK_CARRY
2347                 UPDATE_ZN
2348 .endm
2349 .macro          A_DEC8
2350                 MOV             rscratch,#0
2351                 SUBS            reg_a, reg_a, #0x01000000
2352                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2353                 UPDATE_ZN
2354                 ADD1CYCLE
2355 .endm
2356 .macro          A_DEC16
2357                 MOV             rscratch,#0
2358                 SUBS            reg_a, reg_a, #0x00010000
2359                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2360                 UPDATE_ZN
2361                 ADD1CYCLE
2362 .endm
2363 .macro          DEC16
2364                 S9xGetWordRegNS rscratch2              @  do not        destroy Opadress in rscratch
2365                 MOV             rscratch3,#0
2366                 SUBS            rscratch2, rscratch2, #0x00010000
2367                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2368                 UPDATE_ZN
2369                 S9xSetWord      rscratch2
2370                 ADD1CYCLE
2371 .endm
2372 .macro          DEC8
2373                 S9xGetByteRegNS rscratch2              @  do not        destroy Opadress in rscratch
2374                 MOV             rscratch3,#0
2375                 SUBS            rscratch2, rscratch2, #0x01000000
2376                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2377                 UPDATE_ZN
2378                 S9xSetByte      rscratch2
2379                 ADD1CYCLE
2380 .endm
2381 .macro          EOR16
2382                 S9xGetWord
2383                 EORS            reg_a, reg_a, rscratch
2384                 UPDATE_ZN
2385 .endm
2386 .macro          EOR8
2387                 S9xGetByte
2388                 EORS            reg_a, reg_a, rscratch
2389                 UPDATE_ZN
2390 .endm
2391 .macro          A_INC8
2392                 MOV             rscratch3,#0
2393                 ADDS            reg_a, reg_a, #0x01000000
2394                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2395                 UPDATE_ZN
2396                 ADD1CYCLE
2397 .endm
2398 .macro          A_INC16
2399                 MOV             rscratch3,#0
2400                 ADDS            reg_a, reg_a, #0x00010000
2401                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2402                 UPDATE_ZN
2403                 ADD1CYCLE
2404 .endm
2405 .macro          INC16
2406                 S9xGetWordRegNS rscratch2
2407                 MOV             rscratch3,#0
2408                 ADDS            rscratch2, rscratch2, #0x00010000
2409                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2410                 UPDATE_ZN
2411                 S9xSetWord      rscratch2
2412                 ADD1CYCLE
2413 .endm
2414 .macro          INC8
2415                 S9xGetByteRegNS rscratch2
2416                 MOV             rscratch3,#0
2417                 ADDS            rscratch2, rscratch2, #0x01000000
2418                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2419                 UPDATE_ZN
2420                 S9xSetByte      rscratch2
2421                 ADD1CYCLE
2422 .endm
2423 .macro          LDA16
2424                 S9xGetWordRegStatus reg_a
2425                 UPDATE_ZN
2426 .endm
2427 .macro          LDA8
2428                 S9xGetByteRegStatus reg_a
2429                 UPDATE_ZN
2430 .endm
2431 .macro          LDX16
2432                 S9xGetWordRegStatus reg_x
2433                 UPDATE_ZN
2434 .endm
2435 .macro          LDX8
2436                 S9xGetByteRegStatus reg_x
2437                 UPDATE_ZN
2438 .endm
2439 .macro          LDY16
2440                 S9xGetWordRegStatus reg_y
2441                 UPDATE_ZN
2442 .endm
2443 .macro          LDY8
2444                 S9xGetByteRegStatus reg_y
2445                 UPDATE_ZN
2446 .endm
2447 .macro          A_LSR16
2448                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2449                 MOVS    reg_a, reg_a, LSR #17            @  hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2450                 @  Update Zero
2451                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2452                 MOV     reg_a, reg_a, LSL #16                   @  -> 0lllllll 00000000 00000000        00000000
2453                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2454                 @  Note : the two MOV are included between instruction, to optimize
2455                 @  the pipeline.
2456                 UPDATE_C
2457                 ADD1CYCLE
2458 .endm
2459 .macro          A_LSR8
2460                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2461                 MOVS    reg_a, reg_a, LSR #25            @  llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2462                 @  Update Zero
2463                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2464                 MOV     reg_a, reg_a, LSL #24                   @  -> 00000000 00000000 00000000        0lllllll
2465                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2466                 @  Note : the two MOV are included between instruction, to optimize
2467                 @  the pipeline.
2468                 UPDATE_C
2469                 ADD1CYCLE
2470 .endm
2471 .macro          LSR16
2472                 S9xGetWordRegNS rscratch2
2473                 @  N set to zero by >> 1 LSR
2474                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2475                 MOVS            rscratch2, rscratch2, LSR #17              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2476                 @  Update Carry
2477                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2478                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2479                 @  Update Zero
2480                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2481                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2482                 S9xSetWordLow   rscratch2
2483                 ADD1CYCLE
2484 .endm
2485 .macro          LSR8
2486                 S9xGetByteRegNS rscratch2
2487                 @  N set to zero by >> 1 LSR
2488                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2489                 MOVS            rscratch2, rscratch2, LSR #25              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2490                 @  Update Carry
2491                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2492                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2493                 @  Update Zero
2494                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2495                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2496                 S9xSetByteLow   rscratch2
2497                 ADD1CYCLE
2498 .endm
2499 .macro          ORA8
2500                 S9xGetByte
2501                 ORRS            reg_a, reg_a, rscratch
2502                 UPDATE_ZN
2503 .endm
2504 .macro          ORA16
2505                 S9xGetWord
2506                 ORRS            reg_a, reg_a, rscratch
2507                 UPDATE_ZN
2508 .endm
2509 .macro          A_ROL16
2510                 TST             rstatus, #MASK_CARRY
2511                 ORRNE           reg_a, reg_a, #0x00008000
2512                 MOVS            reg_a, reg_a, LSL #1
2513                 UPDATE_ZN
2514                 UPDATE_C
2515                 ADD1CYCLE
2516 .endm
2517 .macro          A_ROL8
2518                 TST             rstatus, #MASK_CARRY
2519                 ORRNE           reg_a, reg_a, #0x00800000
2520                 MOVS            reg_a, reg_a, LSL #1
2521                 UPDATE_ZN
2522                 UPDATE_C
2523                 ADD1CYCLE
2524 .endm
2525 .macro          ROL16
2526                 S9xGetWordRegNS rscratch2
2527                 TST             rstatus, #MASK_CARRY
2528                 ORRNE           rscratch2, rscratch2, #0x00008000
2529                 MOVS            rscratch2, rscratch2, LSL #1
2530                 UPDATE_ZN
2531                 UPDATE_C
2532                 S9xSetWord      rscratch2
2533                 ADD1CYCLE
2534 .endm
2535 .macro          ROL8
2536                 S9xGetByteRegNS rscratch2
2537                 TST             rstatus, #MASK_CARRY
2538                 ORRNE           rscratch2, rscratch2, #0x00800000
2539                 MOVS            rscratch2, rscratch2, LSL #1
2540                 UPDATE_ZN
2541                 UPDATE_C
2542                 S9xSetByte      rscratch2
2543                 ADD1CYCLE
2544 .endm
2545 .macro          A_ROR16
2546                 MOV                     reg_a,reg_a, LSR #16
2547                 TST                     rstatus, #MASK_CARRY
2548                 ORRNE                   reg_a, reg_a, #0x00010000
2549                 ORRNE                   rstatus,rstatus,#MASK_NEG
2550                 BICEQ                   rstatus,rstatus,#MASK_NEG
2551                 MOVS                    reg_a,reg_a,LSR #1
2552                 UPDATE_C
2553                 UPDATE_Z
2554                 MOV                     reg_a,reg_a, LSL #16
2555                 ADD1CYCLE
2556 .endm
2557 .macro          A_ROR8
2558                 MOV                     reg_a,reg_a, LSR #24
2559                 TST                     rstatus, #MASK_CARRY
2560                 ORRNE                   reg_a, reg_a, #0x00000100
2561                 ORRNE                   rstatus,rstatus,#MASK_NEG
2562                 BICEQ                   rstatus,rstatus,#MASK_NEG
2563                 MOVS                    reg_a,reg_a,LSR #1
2564                 UPDATE_C
2565                 UPDATE_Z
2566                 MOV                     reg_a,reg_a, LSL #24
2567                 ADD1CYCLE
2568 .endm
2569 .macro          ROR16
2570                 S9xGetWordLowRegNS      rscratch2
2571                 TST                     rstatus, #MASK_CARRY
2572                 ORRNE                   rscratch2, rscratch2, #0x00010000
2573                 ORRNE                   rstatus,rstatus,#MASK_NEG
2574                 BICEQ                   rstatus,rstatus,#MASK_NEG
2575                 MOVS                    rscratch2,rscratch2,LSR #1
2576                 UPDATE_C
2577                 UPDATE_Z
2578                 S9xSetWordLow   rscratch2
2579                 ADD1CYCLE
2580
2581 .endm
2582 .macro          ROR8
2583                 S9xGetByteLowRegNS      rscratch2
2584                 TST                     rstatus, #MASK_CARRY
2585                 ORRNE                   rscratch2, rscratch2, #0x00000100
2586                 ORRNE                   rstatus,rstatus,#MASK_NEG
2587                 BICEQ                   rstatus,rstatus,#MASK_NEG
2588                 MOVS                    rscratch2,rscratch2,LSR #1
2589                 UPDATE_C
2590                 UPDATE_Z
2591                 S9xSetByteLow   rscratch2
2592                 ADD1CYCLE
2593 .endm
2594
2595 .macro SBC16
2596         TST rstatus, #MASK_DECIMAL
2597                 BEQ 1111f
2598                 @ TODO
2599                 S9xGetWord
2600
2601                 STMFD   R13!,{rscratch9}
2602                 MOV     rscratch9,#0x000F0000
2603         @ rscratch2 - result
2604         @ rscratch3 - scratch
2605         @ rscratch4 - scratch
2606         @ rscratch9 - pattern
2607
2608                 AND     rscratch2, rscratch, #0x000F0000
2609                 TST     rstatus, #MASK_CARRY
2610                 ADDEQ   rscratch2, rscratch2, #0x00010000  @ W1=W1+!Carry
2611                 AND     rscratch4, reg_a, #0x000F0000
2612         SUB     rscratch2, rscratch4,rscratch2          @ R1=A1-W1-!Carry
2613                 CMP     rscratch2, #0x00090000  @  if R1 > 9
2614                 ADDHI   rscratch2, rscratch2, #0x000A0000 @  then R1 += 10
2615                 AND         rscratch2, rscratch2, #0x000F0000
2616
2617                 AND     rscratch3, rscratch9, rscratch, LSR #4
2618         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W2++)
2619
2620                 AND     rscratch4, rscratch9, reg_a, LSR #4
2621         SUB     rscratch3, rscratch4, rscratch3         @ R2=A2-W2
2622                 CMP     rscratch3, #0x00090000  @  if R2 > 9
2623                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R2 += 10
2624                 AND         rscratch3, rscratch3, #0x000F0000
2625                 ORR         rscratch2, rscratch2, rscratch3,LSL #4
2626
2627                 AND     rscratch3, rscratch9, rscratch, LSR #8
2628         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2629
2630                 AND     rscratch4, rscratch9, reg_a, LSR #8
2631         SUB     rscratch3, rscratch4, rscratch3         @ R3=A3-W3
2632                 CMP     rscratch3, #0x00090000  @  if R3 > 9
2633                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R3 += 10
2634                 AND         rscratch3, rscratch3, #0x000F0000
2635                 ORR         rscratch2, rscratch2, rscratch3,LSL #8
2636
2637                 AND     rscratch3, rscratch9, rscratch, LSR #12
2638         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2639
2640                 AND     rscratch4, rscratch9, reg_a, LSR #12
2641         SUB     rscratch3, rscratch4, rscratch3         @ R4=A4-W4
2642                 CMP     rscratch3, #0x00090000  @  if R4 > 9
2643                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R4 += 10
2644                 BICHI   rstatus, rstatus, #MASK_CARRY   @  then ClearCarry
2645                 ORRLS   rstatus, rstatus, #MASK_CARRY   @  else SetCarry
2646
2647                 AND         rscratch3,rscratch3,#0x000F0000
2648                 ORR         rscratch2,rscratch2,rscratch3,LSL #12
2649
2650                 LDMFD   R13!,{rscratch9}
2651                 @ only last bit
2652                 AND     reg_a,reg_a,#0x80000000
2653                 @  (register.A.W ^ Work8)
2654                 EORS    rscratch3, reg_a, rscratch
2655                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2656                 BEQ     1112f
2657                 @  (register.A.W ^ Ans8)
2658                 EORS    rscratch3, reg_a, rscratch2
2659                 @  & 0x80
2660                 TSTNE   rscratch3,#0x80000000
2661                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2662                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2663 1112:
2664                 MOVS    reg_a, rscratch2
2665                 UPDATE_ZN
2666                 B 1113f
2667 1111:
2668                 S9xGetWordLow
2669                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2670                 SBCS reg_a, reg_a, rscratch, LSL #16
2671                 @ OverFlow
2672                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2673                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2674                 MOV reg_a, reg_a, LSR #16
2675                 @ Carry
2676                 UPDATE_C
2677                 MOVS reg_a, reg_a, LSL #16
2678                 @ Update flag
2679                 UPDATE_ZN
2680 1113:
2681 .endm
2682
2683 .macro SBC8
2684                 TST rstatus, #MASK_DECIMAL
2685                 BEQ 1111f
2686                 S9xGetByte
2687                 STMFD   R13!,{rscratch}
2688                 MOV     rscratch4,#0x0F000000
2689                 @ rscratch2=xxW1xxxxxxxxxxxx
2690                 AND     rscratch2, rscratch, rscratch4
2691                 @ rscratch=xxW2xxxxxxxxxxxx
2692                 AND     rscratch, rscratch4, rscratch, LSR #4
2693                 @ rscratch3=xxA2xxxxxxxxxxxx
2694                 AND     rscratch3, rscratch4, reg_a, LSR #4
2695                 @ rscratch4=xxA1xxxxxxxxxxxx
2696                 AND     rscratch4,reg_a,rscratch4
2697                 @ R1=A1-W1-!CARRY
2698                 TST     rstatus, #MASK_CARRY
2699                 ADDEQ   rscratch2, rscratch2, #0x01000000
2700                 SUB     rscratch2,rscratch4,rscratch2
2701                 @  if R1 > 9
2702                 CMP     rscratch2, #0x09000000
2703                 @  then R1 += 10
2704                 ADDHI   rscratch2, rscratch2, #0x0A000000
2705                 @  then A2-- (W2++)
2706                 ADDHI   rscratch, rscratch, #0x01000000
2707                 @  R2=A2-W2
2708                 SUB     rscratch3, rscratch3, rscratch
2709                 @  if R2 > 9
2710                 CMP     rscratch3, #0x09000000
2711                 @  then R2 -= 10@
2712                 ADDHI   rscratch3, rscratch3, #0x0A000000
2713                 @  then SetCarry()
2714                 BICHI   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2715                 @  else ClearCarry()
2716                 ORRLS   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2717                 @  gather rscratch3 and rscratch2 into ans8
2718                 AND     rscratch3,rscratch3,#0x0F000000
2719                 AND     rscratch2,rscratch2,#0x0F000000
2720                 @  rscratch3 : 0R2000000
2721                 @  rscratch2 : 0R1000000
2722                 @  -> 0xR2R1000000
2723                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2724                 LDMFD   R13!,{rscratch}
2725                 @ only last bit
2726                 AND     reg_a,reg_a,#0x80000000
2727                 @  (register.AL ^ Work8)
2728                 EORS    rscratch3, reg_a, rscratch
2729                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2730                 BEQ     1112f
2731                 @  (register.AL ^ Ans8)
2732                 EORS    rscratch3, reg_a, rscratch2
2733                 @  & 0x80
2734                 TSTNE   rscratch3,#0x80000000
2735                 BICEQ rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2736                 ORRNE rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2737 1112:
2738                 MOVS reg_a, rscratch2
2739                 UPDATE_ZN
2740                 B 1113f
2741 1111:
2742                 S9xGetByteLow
2743                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2744                 SBCS reg_a, reg_a, rscratch, LSL #24
2745                 @ OverFlow
2746                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2747                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2748                 @ Carry
2749                 UPDATE_C
2750                 @ Update flag
2751                 ANDS reg_a, reg_a, #0xFF000000
2752                 UPDATE_ZN
2753 1113:
2754 .endm
2755
2756 .macro          STA16
2757                 S9xSetWord      reg_a
2758 .endm
2759 .macro          STA8
2760                 S9xSetByte      reg_a
2761 .endm
2762 .macro          STX16
2763                 S9xSetWord      reg_x
2764 .endm
2765 .macro          STX8
2766                 S9xSetByte      reg_x
2767 .endm
2768 .macro          STY16
2769                 S9xSetWord      reg_y
2770 .endm
2771 .macro          STY8
2772                 S9xSetByte      reg_y
2773 .endm
2774 .macro          STZ16
2775                 S9xSetWordZero
2776 .endm
2777 .macro          STZ8
2778                 S9xSetByteZero
2779 .endm
2780 .macro          TSB16
2781                 S9xGetWordRegNS rscratch2
2782                 TST             reg_a, rscratch2
2783                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2784                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2785                 ORR             rscratch2, reg_a, rscratch2
2786                 S9xSetWord      rscratch2
2787                 ADD1CYCLE
2788 .endm
2789 .macro          TSB8
2790                 S9xGetByteRegNS rscratch2
2791                 TST             reg_a, rscratch2
2792                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2793                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2794                 ORR             rscratch2, reg_a, rscratch2
2795                 S9xSetByte      rscratch2
2796                 ADD1CYCLE
2797 .endm
2798 .macro          TRB16
2799                 S9xGetWordRegNS rscratch2
2800                 TST             reg_a, rscratch2
2801                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2802                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2803                 MVN             rscratch3, reg_a
2804                 AND             rscratch2, rscratch3, rscratch2
2805                 S9xSetWord      rscratch2
2806                 ADD1CYCLE
2807 .endm
2808 .macro          TRB8
2809                 S9xGetByteRegNS rscratch2
2810                 TST             reg_a, rscratch2
2811                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2812                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2813                 MVN             rscratch3, reg_a
2814                 AND             rscratch2, rscratch3, rscratch2
2815                 S9xSetByte      rscratch2
2816                 ADD1CYCLE
2817 .endm
2818 /**************************************************************************/
2819
2820
2821 /**************************************************************************/
2822
2823 .macro          Op09M0          /*ORA*/
2824                 LDRB            rscratch2, [rpc,#1]
2825                 LDRB            rscratch, [rpc], #2
2826                 ORR             rscratch2,rscratch,rscratch2,LSL #8
2827                 ORRS            reg_a,reg_a,rscratch2,LSL #16
2828                 UPDATE_ZN
2829                 ADD2MEM
2830 .endm
2831 .macro          Op09M1          /*ORA*/
2832                 LDRB            rscratch, [rpc], #1
2833                 ORRS            reg_a,reg_a,rscratch,LSL #24
2834                 UPDATE_ZN
2835                 ADD1MEM
2836 .endm
2837 /***********************************************************************/
2838 .macro          Op90    /*BCC*/
2839                 asmRelative
2840                 BranchCheck0
2841                 TST             rstatus, #MASK_CARRY
2842                 BNE             1111f
2843                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2844                 ADD1CYCLE
2845                 CPUShutdown
2846 1111:
2847 .endm
2848 .macro          OpB0    /*BCS*/
2849                 asmRelative
2850                 BranchCheck0
2851                 TST             rstatus, #MASK_CARRY
2852                 BEQ             1111f
2853                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2854                 ADD1CYCLE
2855                 CPUShutdown
2856 1111:
2857 .endm
2858 .macro          OpF0    /*BEQ*/
2859                 asmRelative
2860                 BranchCheck2
2861                 TST             rstatus, #MASK_ZERO
2862                 BEQ             1111f
2863                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2864                 ADD1CYCLE
2865                 CPUShutdown
2866 1111:
2867 .endm
2868 .macro          OpD0    /*BNE*/
2869                 asmRelative
2870                 BranchCheck1
2871                 TST             rstatus, #MASK_ZERO
2872                 BNE             1111f
2873                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2874                 ADD1CYCLE
2875                 CPUShutdown
2876 1111:
2877 .endm
2878 .macro          Op30    /*BMI*/
2879                 asmRelative
2880                 BranchCheck0
2881                 TST             rstatus, #MASK_NEG
2882                 BEQ             1111f
2883                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2884                 ADD1CYCLE
2885                 CPUShutdown
2886 1111:
2887 .endm
2888 .macro          Op10   /*BPL*/
2889                 asmRelative
2890                 BranchCheck1
2891                 TST             rstatus, #MASK_NEG @  neg, z!=0, NE
2892                 BNE             1111f
2893                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2894                 ADD1CYCLE
2895                 CPUShutdown
2896 1111:
2897 .endm
2898 .macro          Op50   /*BVC*/
2899                 asmRelative
2900                 BranchCheck0
2901                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2902                 BNE             1111f
2903                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2904                 ADD1CYCLE
2905                 CPUShutdown
2906 1111:
2907 .endm
2908 .macro          Op70   /*BVS*/
2909                 asmRelative
2910                 BranchCheck0
2911                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2912                 BEQ             1111f
2913                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2914                 ADD1CYCLE
2915                 CPUShutdown
2916 1111:
2917 .endm
2918 .macro          Op80   /*BRA*/
2919                 asmRelative
2920                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2921                 ADD1CYCLE
2922                 CPUShutdown
2923 1111:
2924 .endm
2925 /*******************************************************************************************/
2926 /************************************************************/
2927 /* SetFlag Instructions ********************************************************************** */
2928 .macro          Op38 /*SEC*/
2929                 ORR             rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2930                 ADD1CYCLE
2931 .endm
2932 .macro          OpF8 /*SED*/
2933                 SetDecimal
2934                 ADD1CYCLE
2935 .endm
2936 .macro          Op78 /*SEI*/
2937                 SetIRQ
2938                 ADD1CYCLE
2939 .endm
2940
2941
2942 /****************************************************************************************/
2943 /* ClearFlag Instructions ******************************************************************** */
2944 .macro          Op18  /*CLC*/
2945                 BIC             rstatus, rstatus, #MASK_CARRY
2946                 ADD1CYCLE
2947 .endm
2948 .macro          OpD8 /*CLD*/
2949                 ClearDecimal
2950                 ADD1CYCLE
2951 .endm
2952 .macro          Op58  /*CLI*/
2953                 ClearIRQ
2954                 ADD1CYCLE
2955                 @ CHECK_FOR_IRQ
2956 .endm
2957 .macro          OpB8 /*CLV*/
2958                 BIC             rstatus, rstatus, #MASK_OVERFLOW
2959                 ADD1CYCLE
2960 .endm
2961
2962 /******************************************************************************************/
2963 /* DEX/DEY *********************************************************************************** */
2964
2965 .macro          OpCAX1  /*DEX*/
2966                 MOV             rscratch3,#0
2967                 SUBS            reg_x, reg_x, #0x01000000
2968                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2969                 UPDATE_ZN
2970                 ADD1CYCLE
2971 .endm
2972 .macro          OpCAX0  /*DEX*/
2973                 MOV             rscratch3,#0
2974                 SUBS            reg_x, reg_x, #0x00010000
2975                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2976                 UPDATE_ZN
2977                 ADD1CYCLE
2978 .endm
2979 .macro          Op88X1 /*DEY*/
2980                 MOV             rscratch3,#0
2981                 SUBS            reg_y, reg_y, #0x01000000
2982                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2983                 UPDATE_ZN
2984                 ADD1CYCLE
2985 .endm
2986 .macro          Op88X0 /*DEY*/
2987                 MOV             rscratch3,#0
2988                 SUBS            reg_y, reg_y, #0x00010000
2989                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2990                 UPDATE_ZN
2991                 ADD1CYCLE
2992 .endm
2993
2994 /******************************************************************************************/
2995 /* INX/INY *********************************************************************************** */
2996 .macro          OpE8X1
2997                 MOV             rscratch3,#0
2998                 ADDS            reg_x, reg_x, #0x01000000
2999                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3000                 UPDATE_ZN
3001                 ADD1CYCLE
3002 .endm
3003 .macro          OpE8X0
3004                 MOV             rscratch3,#0
3005                 ADDS            reg_x, reg_x, #0x00010000
3006                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3007                 UPDATE_ZN
3008                 ADD1CYCLE
3009 .endm
3010 .macro          OpC8X1
3011                 MOV             rscratch3,#0
3012                 ADDS            reg_y, reg_y, #0x01000000
3013                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3014                 UPDATE_ZN
3015                 ADD1CYCLE
3016 .endm
3017 .macro          OpC8X0
3018                 MOV             rscratch3,#0
3019                 ADDS            reg_y, reg_y, #0x00010000
3020                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3021                 UPDATE_ZN
3022                 ADD1CYCLE
3023 .endm
3024
3025 /**********************************************************************************************/
3026
3027 /* NOP *************************************************************************************** */
3028 .macro          OpEA
3029                 ADD1CYCLE
3030 .endm
3031
3032 /**************************************************************************/
3033 /* PUSH Instructions **************************************************** */
3034 .macro          OpF4
3035                 Absolute
3036                 PushWrLow
3037 .endm
3038 .macro          OpD4
3039                 DirectIndirect
3040                 PushWrLow
3041 .endm
3042 .macro          Op62
3043                 asmRelativeLong
3044                 PushWrLow
3045 .endm
3046 .macro          Op48M0
3047                 PushW           reg_a
3048                 ADD1CYCLE
3049 .endm
3050 .macro          Op48M1
3051                 PushB           reg_a
3052                 ADD1CYCLE
3053 .endm
3054 .macro          Op8B
3055                 AND             rscratch2, reg_d_bank, #0xFF
3056                 PushBLow        rscratch2
3057                 ADD1CYCLE
3058 .endm
3059 .macro          Op0B
3060                 PushW           reg_d
3061                 ADD1CYCLE
3062 .endm
3063 .macro          Op4B
3064                 PushBlow        reg_p_bank
3065                 ADD1CYCLE
3066 .endm
3067 .macro          Op08
3068                 PushB           rstatus
3069                 ADD1CYCLE
3070 .endm
3071 .macro          OpDAX1
3072                 PushB           reg_x
3073                 ADD1CYCLE
3074 .endm
3075 .macro          OpDAX0
3076                 PushW           reg_x
3077                 ADD1CYCLE
3078 .endm
3079 .macro          Op5AX1
3080                 PushB           reg_y
3081                 ADD1CYCLE
3082 .endm
3083 .macro          Op5AX0
3084                 PushW           reg_y
3085                 ADD1CYCLE
3086 .endm
3087 /**************************************************************************/
3088 /* PULL Instructions **************************************************** */
3089 .macro          Op68M1
3090                 PullBS          reg_a
3091                 UPDATE_ZN
3092                 ADD2CYCLE
3093 .endm
3094 .macro          Op68M0
3095                 PullWS          reg_a
3096                 UPDATE_ZN
3097                 ADD2CYCLE
3098 .endm
3099 .macro          OpAB
3100                 BIC             reg_d_bank,reg_d_bank, #0xFF
3101                 PullBrS
3102                 ORR             reg_d_bank,reg_d_bank,rscratch, LSR #24
3103                 UPDATE_ZN
3104                 ADD2CYCLE
3105 .endm
3106 .macro          Op2B
3107                 BIC             reg_d,reg_d, #0xFF000000
3108                 BIC             reg_d,reg_d, #0x00FF0000
3109                 PullWrS
3110                 ORR             reg_d,rscratch,reg_d
3111                 UPDATE_ZN
3112                 ADD2CYCLE
3113 .endm
3114 .macro          Op28X1M1        /*PLP*/
3115                 @ INDEX set, MEMORY set
3116                 BIC             rstatus,rstatus,#0xFF000000
3117                 PullBr
3118                 ORR             rstatus,rscratch,rstatus
3119                 TST             rstatus, #MASK_INDEX
3120                 @ INDEX clear & was set : 8->16
3121                 MOVEQ           reg_x,reg_x,LSR #8
3122                 MOVEQ           reg_y,reg_y,LSR #8
3123                 TST             rstatus, #MASK_MEM
3124                 @ MEMORY cleared & was set : 8->16
3125                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3126                 MOVEQ           reg_a,reg_a,LSR #8
3127                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3128                 S9xFixCycles
3129                 ADD2CYCLE
3130 .endm
3131 .macro          Op28X0M1        /*PLP*/
3132                 @ INDEX cleared, MEMORY set
3133                 BIC             rstatus,rstatus,#0xFF000000
3134                 PullBr
3135                 ORR             rstatus,rscratch,rstatus
3136                 TST             rstatus, #MASK_INDEX
3137                 @ INDEX set & was cleared : 16->8
3138                 MOVNE           reg_x,reg_x,LSL #8
3139                 MOVNE           reg_y,reg_y,LSL #8
3140                 TST             rstatus, #MASK_MEM
3141                 @ MEMORY cleared & was set : 8->16
3142                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3143                 MOVEQ           reg_a,reg_a,LSR #8
3144                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3145                 S9xFixCycles
3146                 ADD2CYCLE
3147 .endm
3148 .macro          Op28X1M0        /*PLP*/
3149                 @ INDEX set, MEMORY set
3150                 BIC             rstatus,rstatus,#0xFF000000
3151                 PullBr
3152                 ORR             rstatus,rscratch,rstatus
3153                 TST             rstatus, #MASK_INDEX
3154                 @ INDEX clear & was set : 8->16
3155                 MOVEQ           reg_x,reg_x,LSR #8
3156                 MOVEQ           reg_y,reg_y,LSR #8
3157                 TST             rstatus, #MASK_MEM
3158                 @ MEMORY set & was cleared : 16->8
3159                 MOVNE           rscratch,reg_a,LSR #24
3160                 MOVNE           reg_a,reg_a,LSL #8
3161                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3162                 S9xFixCycles
3163                 ADD2CYCLE
3164 .endm
3165 .macro          Op28X0M0        /*PLP*/
3166                 @ INDEX set, MEMORY set
3167                 BIC             rstatus,rstatus,#0xFF000000
3168                 PullBr
3169                 ORR             rstatus,rscratch,rstatus
3170                 TST             rstatus, #MASK_INDEX
3171                 @ INDEX set & was cleared : 16->8
3172                 MOVNE           reg_x,reg_x,LSL #8
3173                 MOVNE           reg_y,reg_y,LSL #8
3174                 TST             rstatus, #MASK_MEM
3175                 @ MEMORY set & was cleared : 16->8
3176                 MOVNE           rscratch,reg_a,LSR #24
3177                 MOVNE           reg_a,reg_a,LSL #8
3178                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3179                 S9xFixCycles
3180                 ADD2CYCLE
3181 .endm
3182 .macro          OpFAX1
3183                 PullBS          reg_x
3184                 UPDATE_ZN
3185                 ADD2CYCLE
3186 .endm
3187 .macro          OpFAX0
3188                 PullWS          reg_x
3189                 UPDATE_ZN
3190                 ADD2CYCLE
3191 .endm
3192 .macro          Op7AX1
3193                 PullBS          reg_y
3194                 UPDATE_ZN
3195                 ADD2CYCLE
3196 .endm
3197 .macro          Op7AX0
3198                 PullWS          reg_y
3199                 UPDATE_ZN
3200                 ADD2CYCLE
3201 .endm
3202
3203 /**********************************************************************************************/
3204 /* Transfer Instructions ********************************************************************* */
3205 .macro          OpAAX1M1 /*TAX8*/
3206                 MOVS            reg_x, reg_a
3207                 UPDATE_ZN
3208                 ADD1CYCLE
3209 .endm
3210 .macro          OpAAX0M1 /*TAX16*/
3211                 LDRB            reg_x, [reg_cpu_var,#RAH_ofs]
3212                 MOV             reg_x, reg_x,LSL #24
3213                 ORRS            reg_x, reg_x,reg_a, LSR #8
3214                 UPDATE_ZN
3215                 ADD1CYCLE
3216 .endm
3217 .macro          OpAAX1M0 /*TAX8*/
3218                 MOVS            reg_x, reg_a, LSL #8
3219                 UPDATE_ZN
3220                 ADD1CYCLE
3221 .endm
3222 .macro          OpAAX0M0 /*TAX16*/
3223                 MOVS            reg_x, reg_a
3224                 UPDATE_ZN
3225                 ADD1CYCLE
3226 .endm
3227 .macro          OpA8X1M1 /*TAY8*/
3228                 MOVS            reg_y, reg_a
3229                 UPDATE_ZN
3230                 ADD1CYCLE
3231 .endm
3232 .macro          OpA8X0M1 /*TAY16*/
3233                 LDRB            reg_y, [reg_cpu_var,#RAH_ofs]
3234                 MOV             reg_y, reg_y,LSL #24
3235                 ORRS            reg_y, reg_y,reg_a, LSR #8
3236                 UPDATE_ZN
3237                 ADD1CYCLE
3238 .endm
3239 .macro          OpA8X1M0 /*TAY8*/
3240                 MOVS            reg_y, reg_a, LSL #8
3241                 UPDATE_ZN
3242                 ADD1CYCLE
3243 .endm
3244 .macro          OpA8X0M0 /*TAY16*/
3245                 MOVS            reg_y, reg_a
3246                 UPDATE_ZN
3247                 ADD1CYCLE
3248 .endm
3249 .macro          Op5BM1
3250                 LDRB            rscratch, [reg_cpu_var,#RAH_ofs]
3251                 MOV             reg_d,reg_d,LSL #16
3252                 MOV             rscratch,rscratch,LSL #24
3253                 ORRS            rscratch,rscratch,reg_a, LSR #8
3254                 UPDATE_ZN
3255                 ORR             reg_d,rscratch,reg_d,LSR #16
3256                 ADD1CYCLE
3257 .endm
3258 .macro          Op5BM0
3259                 MOV             reg_d,reg_d,LSL #16
3260                 MOVS            reg_a,reg_a
3261                 UPDATE_ZN
3262                 ORR             reg_d,reg_a,reg_d,LSR #16
3263                 ADD1CYCLE
3264 .endm
3265 .macro          Op1BM1
3266                 TST             rstatus, #MASK_EMUL
3267                 MOVNE           reg_s, reg_a, LSR #24
3268                 ORRNE           reg_s, reg_s, #0x100
3269                 LDREQB          reg_s, [reg_cpu_var,#RAH_ofs]
3270                 ORREQ           reg_s, reg_s, reg_a
3271                 MOVEQ           reg_s, reg_s, ROR #24
3272                 ADD1CYCLE
3273 .endm
3274 .macro          Op1BM0
3275                 MOV             reg_s, reg_a, LSR #16
3276                 ADD1CYCLE
3277 .endm
3278 .macro          Op7BM1
3279                 MOVS            reg_a, reg_d, ASR #16
3280                 UPDATE_ZN
3281                 MOV             rscratch,reg_a,LSR #8
3282                 MOV             reg_a,reg_a, LSL #24
3283                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3284                 ADD1CYCLE
3285 .endm
3286 .macro          Op7BM0
3287                 MOVS            reg_a, reg_d, ASR #16
3288                 UPDATE_ZN
3289                 MOV             reg_a,reg_a, LSL #16
3290                 ADD1CYCLE
3291 .endm
3292 .macro          Op3BM1
3293                 MOV             rscratch,reg_s, LSR #8
3294                 MOVS            reg_a, reg_s, LSL #16
3295                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3296                 UPDATE_ZN
3297                 MOV             reg_a,reg_a, LSL #8
3298                 ADD1CYCLE
3299 .endm
3300 .macro          Op3BM0
3301                 MOVS            reg_a, reg_s, LSL #16
3302                 UPDATE_ZN
3303                 ADD1CYCLE
3304 .endm
3305 .macro          OpBAX1
3306                 MOVS            reg_x, reg_s, LSL #24
3307                 UPDATE_ZN
3308                 ADD1CYCLE
3309 .endm
3310 .macro          OpBAX0
3311                 MOVS            reg_x, reg_s, LSL #16
3312                 UPDATE_ZN
3313                 ADD1CYCLE
3314 .endm
3315 .macro          Op8AM1X1
3316                 MOVS            reg_a, reg_x
3317                 UPDATE_ZN
3318                 ADD1CYCLE
3319 .endm
3320 .macro          Op8AM1X0
3321                 MOVS            reg_a, reg_x, LSL #8
3322                 UPDATE_ZN
3323                 ADD1CYCLE
3324 .endm
3325 .macro          Op8AM0X1
3326                 MOVS            reg_a, reg_x, LSR #8
3327                 UPDATE_ZN
3328                 ADD1CYCLE
3329 .endm
3330 .macro          Op8AM0X0
3331                 MOVS            reg_a, reg_x
3332                 UPDATE_ZN
3333                 ADD1CYCLE
3334 .endm
3335 .macro          Op9AX1
3336                 MOV             reg_s, reg_x, LSR #24
3337                 TST             rstatus, #MASK_EMUL
3338                 ORRNE           reg_s, reg_s, #0x100
3339                 ADD1CYCLE
3340 .endm
3341 .macro          Op9AX0
3342                 MOV             reg_s, reg_x, LSR #16
3343                 ADD1CYCLE
3344 .endm
3345 .macro          Op9BX1
3346                 MOVS            reg_y, reg_x
3347                 UPDATE_ZN
3348                 ADD1CYCLE
3349 .endm
3350 .macro          Op9BX0
3351                 MOVS            reg_y, reg_x
3352                 UPDATE_ZN
3353                 ADD1CYCLE
3354 .endm
3355 .macro          Op98M1X1
3356                 MOVS            reg_a, reg_y
3357                 UPDATE_ZN
3358                 ADD1CYCLE
3359 .endm
3360 .macro          Op98M1X0
3361                 MOVS            reg_a, reg_y, LSL #8
3362                 UPDATE_ZN
3363                 ADD1CYCLE
3364 .endm
3365 .macro          Op98M0X1
3366                 MOVS            reg_a, reg_y, LSR #8
3367                 UPDATE_ZN
3368                 ADD1CYCLE
3369 .endm
3370 .macro          Op98M0X0
3371                 MOVS            reg_a, reg_y
3372                 UPDATE_ZN
3373                 ADD1CYCLE
3374 .endm
3375 .macro          OpBBX1
3376                 MOVS            reg_x, reg_y
3377                 UPDATE_ZN
3378                 ADD1CYCLE
3379 .endm
3380 .macro          OpBBX0
3381                 MOVS            reg_x, reg_y
3382                 UPDATE_ZN
3383                 ADD1CYCLE
3384 .endm
3385
3386 /**********************************************************************************************/
3387 /* XCE *************************************************************************************** */
3388
3389 .macro          OpFB
3390     TST         rstatus,#MASK_CARRY
3391     BEQ         1111f
3392     @ CARRY is set
3393     TST         rstatus,#MASK_EMUL
3394     BNE         1112f
3395     @ EMUL is cleared
3396     BIC         rstatus,rstatus,#(MASK_CARRY)
3397     TST         rstatus,#MASK_INDEX
3398     @ X & Y were 16bits before
3399     MOVEQ       reg_x,reg_x,LSL #8
3400     MOVEQ       reg_y,reg_y,LSL #8
3401     TST         rstatus,#MASK_MEM
3402     @ A was 16bits before
3403     @ save AH
3404     MOVEQ       rscratch,reg_a,LSR #24
3405     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3406     MOVEQ       reg_a,reg_a,LSL #8
3407     ORR         rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3408     AND         reg_s,reg_s,#0xFF
3409     ORR         reg_s,reg_s,#0x100
3410     B           1113f
3411 1112:
3412     @ EMUL is set
3413     TST         rstatus,#MASK_INDEX
3414     @ X & Y were 16bits before
3415     MOVEQ       reg_x,reg_x,LSL #8
3416     MOVEQ       reg_y,reg_y,LSL #8
3417     TST         rstatus,#MASK_MEM
3418     @ A was 16bits before
3419     @ save AH
3420     MOVEQ       rscratch,reg_a,LSR #24
3421     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3422     MOVEQ       reg_a,reg_a,LSL #8
3423     ORR         rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3424     AND         reg_s,reg_s,#0xFF
3425     ORR         reg_s,reg_s,#0x100
3426     B           1113f
3427 1111:
3428     @ CARRY is cleared
3429     TST         rstatus,#MASK_EMUL
3430     BEQ         1115f
3431     @ EMUL was set : X,Y & A were 8bits
3432     @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3433     TST         rstatus,#MASK_INDEX
3434     @  X & Y are now 16bits
3435     MOVEQ       reg_x,reg_x,LSR #8
3436     MOVEQ       reg_y,reg_y,LSR #8
3437     TST         rstatus,#MASK_MEM
3438     @  A is now 16bits
3439     MOVEQ       reg_a,reg_a,LSR #8
3440     @ restore AH
3441     LDREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3442     ORREQ       reg_a,reg_a,rscratch,LSL #24
3443 1115:
3444     BIC         rstatus,rstatus,#(MASK_EMUL)
3445     ORR         rstatus,rstatus,#(MASK_CARRY)
3446 1113:
3447     ADD1CYCLE
3448     S9xFixCycles
3449 .endm
3450
3451 /*******************************************************************************/
3452 /* BRK *************************************************************************/
3453 .macro          Op00            /*BRK*/
3454                 MOV             rscratch,#1
3455                 STRB            rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3456
3457                 TST             rstatus, #MASK_EMUL
3458                 @  EQ is flag to zero (!CheckEmu)
3459                 BNE             2001f@ elseOp00
3460                 PushBLow        reg_p_bank
3461                 SUB             rscratch, rpc, regpcbase
3462                 ADD             rscratch2, rscratch, #1
3463                 PushWLow        rscratch2
3464                 @  PackStatus
3465                 PushB           rstatus
3466                 ClearDecimal
3467                 SetIRQ
3468                 BIC             reg_p_bank, reg_p_bank, #0xFF
3469                 MOV             rscratch, #0xE6
3470                 ORR             rscratch, rscratch, #0xFF00
3471                 S9xGetWordLow
3472                 S9xSetPCBase
3473                 ADD2CYCLE
3474                 B               2002f@ endOp00
3475 2001:@ elseOp00
3476                 SUB             rscratch2, rpc, regpcbase
3477                 PushWLow        rscratch2
3478                 @  PackStatus
3479                 PushB           rstatus
3480                 ClearDecimal
3481                 SetIRQ
3482                 BIC             reg_p_bank,reg_p_bank, #0xFF
3483                 MOV             rscratch, #0xFE
3484                 ORR             rscratch, rscratch, #0xFF00
3485                 S9xGetWordLow
3486                 S9xSetPCBase
3487                 ADD1CYCLE
3488 2002:@ endOp00
3489 .endm
3490
3491
3492 /**********************************************************************************************/
3493 /* BRL ************************************************************************************** */
3494 .macro          Op82    /*BRL*/
3495                 asmRelativeLong
3496                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3497                 S9xSetPCBase
3498 .endm
3499 /**********************************************************************************************/
3500 /* IRQ *************************************************************************************** */
3501 @ void S9xOpcode_IRQ (void)
3502 .macro          S9xOpcode_IRQ   @ IRQ
3503                 TST             rstatus, #MASK_EMUL
3504                 @  EQ is flag to zero (!CheckEmu)
3505                 BNE             2121f@ elseOp02
3506                 PushBLow        reg_p_bank
3507                 SUB             rscratch2, rpc, regpcbase
3508                 PushWLow        rscratch2
3509                 @  PackStatus
3510                 PushB           rstatus
3511                 ClearDecimal
3512                 SetIRQ
3513                 BIC             reg_p_bank, reg_p_bank,#0xFF
3514                 MOV             rscratch, #0xEE
3515                 ORR             rscratch, rscratch, #0xFF00
3516                 S9xGetWordLow
3517                 S9xSetPCBase
3518                 ADD2CYCLE
3519                 B 2122f
3520 2121:@ else
3521                 SUB             rscratch2, rpc, regpcbase
3522                 PushWLow        rscratch2
3523                 @  PackStatus
3524                 PushB           rstatus
3525                 ClearDecimal
3526                 SetIRQ
3527                 BIC             reg_p_bank,reg_p_bank, #0xFF
3528                 MOV             rscratch, #0xFE
3529                 ORR             rscratch, rscratch, #0xFF00
3530                 S9xGetWordLow
3531                 S9xSetPCBase
3532                 ADD1CYCLE
3533 2122:
3534 .endm
3535
3536 /*
3537 void asm_S9xOpcode_IRQ(void)
3538 {
3539     if (!CheckEmulation())
3540     {
3541         PushB (Registers.PB);
3542         PushW (CPU.PC - CPU.PCBase);
3543         PushB (Registers.PL);
3544         ClearDecimal ();
3545         SetIRQ ();
3546
3547         Registers.PB = 0;
3548                 S9xSetPCBase (S9xGetWord (0xFFEE));
3549         CPU.Cycles += TWO_CYCLES;
3550     }
3551     else
3552     {
3553         PushW (CPU.PC - CPU.PCBase);
3554         PushB (Registers.PL);
3555         ClearDecimal ();
3556         SetIRQ ();
3557
3558         Registers.PB = 0;
3559         S9xSetPCBase (S9xGetWord (0xFFFE));
3560         CPU.Cycles += ONE_CYCLE;
3561     }
3562 }
3563 */
3564
3565 /**********************************************************************************************/
3566 /* NMI *************************************************************************************** */
3567 @ void S9xOpcode_NMI (void)
3568 .macro          S9xOpcode_NMI   @ NMI
3569                 TST             rstatus, #MASK_EMUL
3570                 @  EQ is flag to zero (!CheckEmu)
3571                 BNE             2123f@ elseOp02
3572                 PushBLow        reg_p_bank
3573                 SUB             rscratch2, rpc, regpcbase
3574                 PushWLow        rscratch2
3575                 @  PackStatus
3576                 PushB           rstatus
3577                 ClearDecimal
3578                 SetIRQ
3579                 BIC             reg_p_bank, reg_p_bank,#0xFF
3580                 MOV             rscratch, #0xEA
3581                 ORR             rscratch, rscratch, #0xFF00
3582                 S9xGetWordLow
3583                 S9xSetPCBase
3584                 ADD2CYCLE
3585                 B 2124f
3586 2123:@ else
3587                 SUB             rscratch2, rpc, regpcbase
3588                 PushWLow        rscratch2
3589                 @  PackStatus
3590                 PushB           rstatus
3591                 ClearDecimal
3592                 SetIRQ
3593                 BIC             reg_p_bank,reg_p_bank, #0xFF
3594                 MOV             rscratch, #0xFA
3595                 ORR             rscratch, rscratch, #0xFF00
3596                 S9xGetWordLow
3597                 S9xSetPCBase
3598                 ADD1CYCLE
3599 2124:
3600 .endm
3601 /*
3602 void asm_S9xOpcode_NMI(void)
3603 {
3604         if (!CheckEmulation())
3605     {
3606         PushB (Registers.PB);
3607         PushW (CPU.PC - CPU.PCBase);
3608         PushB (Registers.PL);
3609         ClearDecimal ();
3610         SetIRQ ();
3611
3612         Registers.PB = 0;
3613         S9xSetPCBase (S9xGetWord (0xFFEA));
3614         CPU.Cycles += TWO_CYCLES;
3615     }
3616     else
3617     {
3618         PushW (CPU.PC - CPU.PCBase);
3619         PushB (Registers.PL);
3620         ClearDecimal ();
3621         SetIRQ ();
3622
3623         Registers.PB = 0;
3624         S9xSetPCBase (S9xGetWord (0xFFFA));
3625         CPU.Cycles += ONE_CYCLE;
3626     }
3627 }
3628 */
3629
3630 /**********************************************************************************************/
3631 /* COP *************************************************************************************** */
3632 .macro          Op02            /*COP*/
3633                 TST             rstatus, #MASK_EMUL
3634                 @  EQ is flag to zero (!CheckEmu)
3635                 BNE             2021f@ elseOp02
3636                 PushBLow        reg_p_bank
3637                 SUB             rscratch, rpc, regpcbase
3638                 ADD             rscratch2, rscratch, #1
3639                 PushWLow        rscratch2
3640                 @  PackStatus
3641                 PushB           rstatus
3642                 ClearDecimal
3643                 SetIRQ
3644                 BIC             reg_p_bank, reg_p_bank,#0xFF
3645                 MOV             rscratch, #0xE4
3646                 ORR             rscratch, rscratch, #0xFF00
3647                 S9xGetWordLow
3648                 S9xSetPCBase
3649                 ADD2CYCLE
3650                 B 2022f@ endOp02
3651 2021:@ elseOp02
3652                 SUB             rscratch2, rpc, regpcbase
3653                 PushWLow        rscratch2
3654                 @  PackStatus
3655                 PushB           rstatus
3656                 ClearDecimal
3657                 SetIRQ
3658                 BIC             reg_p_bank,reg_p_bank, #0xFF
3659                 MOV             rscratch, #0xF4
3660                 ORR             rscratch, rscratch, #0xFF00
3661                 S9xGetWordLow
3662                 S9xSetPCBase
3663                 ADD1CYCLE
3664 2022:@ endOp02
3665 .endm
3666
3667 /**********************************************************************************************/
3668 /* JML *************************************************************************************** */
3669 .macro          OpDC
3670                 AbsoluteIndirectLong
3671                 BIC             reg_p_bank,reg_p_bank,#0xFF
3672                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3673                 S9xSetPCBase
3674                 ADD2CYCLE
3675 .endm
3676 .macro          Op5C
3677                 AbsoluteLong
3678                 BIC             reg_p_bank,reg_p_bank,#0xFF
3679                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3680                 S9xSetPCBase
3681 .endm
3682
3683 /**********************************************************************************************/
3684 /* JMP *************************************************************************************** */
3685 .macro          Op4C
3686                 Absolute
3687                 BIC             rscratch, rscratch, #0xFF0000
3688                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3689                 S9xSetPCBase
3690                 CPUShutdown
3691 .endm
3692 .macro          Op6C
3693                 AbsoluteIndirect
3694                 BIC             rscratch, rscratch, #0xFF0000
3695                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3696                 S9xSetPCBase
3697 .endm
3698 .macro          Op7C
3699                 ADD             rscratch, rscratch, reg_p_bank, LSL #16
3700                 S9xSetPCBase
3701                 ADD1CYCLE
3702 .endm
3703
3704 /**********************************************************************************************/
3705 /* JSL/RTL *********************************************************************************** */
3706 .macro          Op22
3707                 PushBlow        reg_p_bank
3708                 SUB             rscratch, rpc, regpcbase
3709                 @ SUB           rscratch2, rscratch2, #1
3710                 ADD             rscratch2, rscratch, #2
3711                 PushWlow        rscratch2
3712                 AbsoluteLong
3713                 BIC             reg_p_bank,reg_p_bank,#0xFF
3714                 ORR             reg_p_bank, reg_p_bank, rscratch, LSR #16
3715                 S9xSetPCBase
3716 .endm
3717 .macro          Op6B
3718                 PullWLow        rpc
3719                 BIC             reg_p_bank,reg_p_bank,#0xFF
3720                 PullBrLow
3721                 ORR             reg_p_bank, reg_p_bank, rscratch
3722                 ADD             rscratch, rpc, #1
3723                 BIC             rscratch, rscratch,#0xFF0000
3724                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3725                 S9xSetPCBase
3726                 ADD2CYCLE
3727 .endm
3728 /**********************************************************************************************/
3729 /* JSR/RTS *********************************************************************************** */
3730 .macro          Op20
3731                 SUB             rscratch, rpc, regpcbase
3732                 @ SUB           rscratch2, rscratch2, #1
3733                 ADD             rscratch2, rscratch, #1
3734                 PushWlow        rscratch2
3735                 Absolute
3736                 BIC             rscratch, rscratch, #0xFF0000
3737                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3738                 S9xSetPCBase
3739                 ADD1CYCLE
3740 .endm
3741 .macro          OpFCX0
3742                 SUB             rscratch, rpc, regpcbase
3743                 @ SUB           rscratch2, rscratch2, #1
3744                 ADD             rscratch2, rscratch, #1
3745                 PushWlow        rscratch2
3746                 AbsoluteIndexedIndirectX0
3747                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3748                 S9xSetPCBase
3749                 ADD1CYCLE
3750 .endm
3751 .macro          OpFCX1
3752                 SUB             rscratch, rpc, regpcbase
3753                 @ SUB           rscratch2, rscratch2, #1
3754                 ADD             rscratch2, rscratch, #1
3755                 PushWlow        rscratch2
3756                 AbsoluteIndexedIndirectX1
3757                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3758                 S9xSetPCBase
3759                 ADD1CYCLE
3760 .endm
3761 .macro          Op60
3762                 PullWLow        rpc
3763                 ADD             rscratch, rpc, #1
3764                 BIC             rscratch, rscratch,#0x10000
3765                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3766                 S9xSetPCBase
3767                 ADD3CYCLE
3768 .endm
3769
3770 /**********************************************************************************************/
3771 /* MVN/MVP *********************************************************************************** */
3772 .macro          Op54X1M1
3773                 @ Save RegStatus = reg_d_bank >> 24
3774                 MOV             rscratch, reg_d_bank, LSR #16
3775                 LDRB            reg_d_bank    , [rpc], #1
3776                 LDRB            rscratch2    , [rpc], #1
3777                 @ Restore RegStatus = reg_d_bank >> 24
3778                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3779                 MOV             rscratch    , reg_x, LSR #24
3780                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3781                 S9xGetByteLow
3782                 MOV             rscratch2, rscratch
3783                 MOV             rscratch   , reg_y, LSR #24
3784                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3785                 S9xSetByteLow   rscratch2
3786                 @ load 16bits A
3787                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3788                 MOV             reg_a,reg_a,LSR #8
3789                 ORR             reg_a,reg_a,rscratch, LSL #24
3790                 ADD             reg_x, reg_x, #0x01000000
3791                 SUB             reg_a, reg_a, #0x00010000
3792                 ADD             reg_y, reg_y, #0x01000000
3793                 CMP             reg_a, #0xFFFF0000
3794                 SUBNE           rpc, rpc, #3
3795                 @ update AH
3796                 MOV             rscratch, reg_a, LSR #24
3797                 MOV             reg_a,reg_a,LSL #8
3798                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3799                 ADD2CYCLE2MEM
3800 .endm
3801 .macro          Op54X1M0
3802                 @ Save RegStatus = reg_d_bank >> 24
3803                 MOV             rscratch, reg_d_bank, LSR #16
3804                 LDRB            reg_d_bank    , [rpc], #1
3805                 LDRB            rscratch2    , [rpc], #1
3806                 @ Restore RegStatus = reg_d_bank >> 24
3807                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3808                 MOV             rscratch    , reg_x, LSR #24
3809                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3810                 S9xGetByteLow
3811                 MOV             rscratch2, rscratch
3812                 MOV             rscratch   , reg_y, LSR #24
3813                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3814                 S9xSetByteLow   rscratch2
3815                 ADD             reg_x, reg_x, #0x01000000
3816                 SUB             reg_a, reg_a, #0x00010000
3817                 ADD             reg_y, reg_y, #0x01000000
3818                 CMP             reg_a, #0xFFFF0000
3819                 SUBNE           rpc, rpc, #3
3820                 ADD2CYCLE2MEM
3821 .endm
3822 .macro          Op54X0M1
3823                 @ Save RegStatus = reg_d_bank >> 24
3824                 MOV             rscratch, reg_d_bank, LSR #16
3825                 LDRB            reg_d_bank    , [rpc], #1
3826                 LDRB            rscratch2    , [rpc], #1
3827                 @ Restore RegStatus = reg_d_bank >> 24
3828                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3829                 MOV             rscratch    , reg_x, LSR #16
3830                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3831                 S9xGetByteLow
3832                 MOV             rscratch2, rscratch
3833                 MOV             rscratch   , reg_y, LSR #16
3834                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3835                 S9xSetByteLow   rscratch2
3836                 @ load 16bits A
3837                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3838                 MOV             reg_a,reg_a,LSR #8
3839                 ORR             reg_a,reg_a,rscratch, LSL #24
3840                 ADD             reg_x, reg_x, #0x00010000
3841                 SUB             reg_a, reg_a, #0x00010000
3842                 ADD             reg_y, reg_y, #0x00010000
3843                 CMP             reg_a, #0xFFFF0000
3844                 SUBNE           rpc, rpc, #3
3845                 @ update AH
3846                 MOV             rscratch, reg_a, LSR #24
3847                 MOV             reg_a,reg_a,LSL #8
3848                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3849                 ADD2CYCLE2MEM
3850 .endm
3851 .macro          Op54X0M0
3852                 @ Save RegStatus = reg_d_bank >> 24
3853                 MOV             rscratch, reg_d_bank, LSR #16
3854                 LDRB            reg_d_bank    , [rpc], #1
3855                 LDRB            rscratch2    , [rpc], #1
3856                 @ Restore RegStatus = reg_d_bank >> 24
3857                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3858                 MOV             rscratch    , reg_x, LSR #16
3859                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3860                 S9xGetByteLow
3861                 MOV             rscratch2, rscratch
3862                 MOV             rscratch   , reg_y, LSR #16
3863                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3864                 S9xSetByteLow   rscratch2
3865                 ADD             reg_x, reg_x, #0x00010000
3866                 SUB             reg_a, reg_a, #0x00010000
3867                 ADD             reg_y, reg_y, #0x00010000
3868                 CMP             reg_a, #0xFFFF0000
3869                 SUBNE           rpc, rpc, #3
3870                 ADD2CYCLE2MEM
3871 .endm
3872
3873 .macro          Op44X1M1
3874                 @ Save RegStatus = reg_d_bank >> 24
3875                 MOV             rscratch, reg_d_bank, LSR #16
3876                 LDRB            reg_d_bank    , [rpc], #1
3877                 LDRB            rscratch2    , [rpc], #1
3878                 @ Restore RegStatus = reg_d_bank >> 24
3879                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3880                 MOV             rscratch    , reg_x, LSR #24
3881                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3882                 S9xGetByteLow
3883                 MOV             rscratch2, rscratch
3884                 MOV             rscratch   , reg_y, LSR #24
3885                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3886                 S9xSetByteLow   rscratch2
3887                 @ load 16bits A
3888                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3889                 MOV             reg_a,reg_a,LSR #8
3890                 ORR             reg_a,reg_a,rscratch, LSL #24
3891                 SUB             reg_x, reg_x, #0x01000000
3892                 SUB             reg_a, reg_a, #0x00010000
3893                 SUB             reg_y, reg_y, #0x01000000
3894                 CMP             reg_a, #0xFFFF0000
3895                 SUBNE           rpc, rpc, #3
3896                 @ update AH
3897                 MOV             rscratch, reg_a, LSR #24
3898                 MOV             reg_a,reg_a,LSL #8
3899                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3900                 ADD2CYCLE2MEM
3901 .endm
3902 .macro          Op44X1M0
3903                 @ Save RegStatus = reg_d_bank >> 24
3904                 MOV             rscratch, reg_d_bank, LSR #16
3905                 LDRB            reg_d_bank    , [rpc], #1
3906                 LDRB            rscratch2    , [rpc], #1
3907                 @ Restore RegStatus = reg_d_bank >> 24
3908                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3909                 MOV             rscratch    , reg_x, LSR #24
3910                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3911                 S9xGetByteLow
3912                 MOV             rscratch2, rscratch
3913                 MOV             rscratch   , reg_y, LSR #24
3914                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3915                 S9xSetByteLow   rscratch2
3916                 SUB             reg_x, reg_x, #0x01000000
3917                 SUB             reg_a, reg_a, #0x00010000
3918                 SUB             reg_y, reg_y, #0x01000000
3919                 CMP             reg_a, #0xFFFF0000
3920                 SUBNE           rpc, rpc, #3
3921                 ADD2CYCLE2MEM
3922 .endm
3923 .macro          Op44X0M1
3924                 @ Save RegStatus = reg_d_bank >> 24
3925                 MOV             rscratch, reg_d_bank, LSR #16
3926                 LDRB            reg_d_bank    , [rpc], #1
3927                 LDRB            rscratch2    , [rpc], #1
3928                 @ Restore RegStatus = reg_d_bank >> 24
3929                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3930                 MOV             rscratch    , reg_x, LSR #16
3931                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3932                 S9xGetByteLow
3933                 MOV             rscratch2, rscratch
3934                 MOV             rscratch   , reg_y, LSR #16
3935                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3936                 S9xSetByteLow   rscratch2
3937                 @ load 16bits A
3938                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3939                 MOV             reg_a,reg_a,LSR #8
3940                 ORR             reg_a,reg_a,rscratch, LSL #24
3941                 SUB             reg_x, reg_x, #0x00010000
3942                 SUB             reg_a, reg_a, #0x00010000
3943                 SUB             reg_y, reg_y, #0x00010000
3944                 CMP             reg_a, #0xFFFF0000
3945                 SUBNE           rpc, rpc, #3
3946                 @ update AH
3947                 MOV             rscratch, reg_a, LSR #24
3948                 MOV             reg_a,reg_a,LSL #8
3949                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3950                 ADD2CYCLE2MEM
3951 .endm
3952 .macro          Op44X0M0
3953                 @ Save RegStatus = reg_d_bank >> 24
3954                 MOV             rscratch, reg_d_bank, LSR #16
3955                 LDRB            reg_d_bank    , [rpc], #1
3956                 LDRB            rscratch2    , [rpc], #1
3957                 @ Restore RegStatus = reg_d_bank >> 24
3958                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3959                 MOV             rscratch    , reg_x, LSR #16
3960                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3961                 S9xGetByteLow
3962                 MOV             rscratch2, rscratch
3963                 MOV             rscratch   , reg_y, LSR #16
3964                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3965                 S9xSetByteLow   rscratch2
3966                 SUB             reg_x, reg_x, #0x00010000
3967                 SUB             reg_a, reg_a, #0x00010000
3968                 SUB             reg_y, reg_y, #0x00010000
3969                 CMP             reg_a, #0xFFFF0000
3970                 SUBNE           rpc, rpc, #3
3971                 ADD2CYCLE2MEM
3972 .endm
3973
3974 /**********************************************************************************************/
3975 /* REP/SEP *********************************************************************************** */
3976 .macro          OpC2
3977                 @  status&=~(*rpc++);
3978                 @  so possible changes are :
3979                 @  INDEX = 1 -> 0  : X,Y 8bits -> 16bits
3980                 @  MEM = 1 -> 0 : A 8bits -> 16bits
3981                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3982                 MOV             rscratch3, rstatus
3983                 LDRB            rscratch, [rpc], #1
3984                 MVN             rscratch, rscratch
3985                 AND             rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3986                 TST             rstatus,#MASK_EMUL
3987                 BEQ             1111f
3988                 @ emulation mode on : no changes since it was on before opcode
3989                 @ just be sure to reset MEM & INDEX accordingly
3990                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3991                 B               1112f
3992 1111:
3993                 @ NOT in Emulation mode, check INDEX & MEMORY bits
3994                 @ Now check INDEX
3995                 TST             rscratch3,#MASK_INDEX
3996                 BEQ             1113f
3997                 @  X & Y were 8bit before
3998                 TST             rstatus,#MASK_INDEX
3999                 BNE             1113f
4000                 @  X & Y are now 16bits
4001                 MOV             reg_x,reg_x,LSR #8
4002                 MOV             reg_y,reg_y,LSR #8
4003 1113:           @ X & Y still in 16bits
4004                 @ Now check MEMORY
4005                 TST             rscratch3,#MASK_MEM
4006                 BEQ             1112f
4007                 @  A was 8bit before
4008                 TST             rstatus,#MASK_MEM
4009                 BNE             1112f
4010                 @  A is now 16bits
4011                 MOV             reg_a,reg_a,LSR #8
4012                 @ restore AH
4013                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4014                 ORREQ           reg_a,reg_a,rscratch,LSL #24
4015 1112:
4016                 S9xFixCycles
4017                 ADD1CYCLE1MEM
4018 .endm
4019 .macro          OpE2
4020                 @  status|=*rpc++;
4021                 @  so possible changes are :
4022                 @  INDEX = 0 -> 1  : X,Y 16bits -> 8bits
4023                 @  MEM = 0 -> 1 : A 16bits -> 8bits
4024                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4025                 MOV             rscratch3, rstatus
4026                 LDRB            rscratch, [rpc], #1
4027                 ORR             rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4028                 TST             rstatus,#MASK_EMUL
4029                 BEQ             10111f
4030                 @ emulation mode on : no changes sinc eit was on before opcode
4031                 @ just be sure to have mem & index set accordingly
4032                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4033                 B               10112f
4034 10111:
4035                 @ NOT in Emulation mode, check INDEX & MEMORY bits
4036                 @ Now check INDEX
4037                 TST             rscratch3,#MASK_INDEX
4038                 BNE             10113f
4039                 @  X & Y were 16bit before
4040                 TST             rstatus,#MASK_INDEX
4041                 BEQ             10113f
4042                 @  X & Y are now 8bits
4043                 MOV             reg_x,reg_x,LSL #8
4044                 MOV             reg_y,reg_y,LSL #8
4045 10113:          @ X & Y still in 16bits
4046                 @ Now check MEMORY
4047                 TST             rscratch3,#MASK_MEM
4048                 BNE             10112f
4049                 @  A was 16bit before
4050                 TST             rstatus,#MASK_MEM
4051                 BEQ             10112f
4052                 @  A is now 8bits
4053                 @  save AH
4054                 MOV             rscratch,reg_a,LSR #24
4055                 MOV             reg_a,reg_a,LSL #8
4056                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
4057 10112:
4058                 S9xFixCycles
4059                 ADD1CYCLE1MEM
4060 .endm
4061
4062 /**********************************************************************************************/
4063 /* XBA *************************************************************************************** */
4064 .macro          OpEBM1
4065                 @ A is 8bits
4066                 ADD             rscratch,reg_cpu_var,#RAH_ofs
4067                 MOV             reg_a,reg_a, LSR #24
4068                 SWPB            reg_a,reg_a,[rscratch]
4069                 MOVS            reg_a,reg_a, LSL #24
4070                 UPDATE_ZN
4071                 ADD2CYCLE
4072 .endm
4073 .macro          OpEBM0
4074                 @ A is 16bits
4075                 MOV             rscratch, reg_a, ROR #24 @  ll0000hh
4076                 ORR             rscratch, rscratch, reg_a, LSR #8@  ll0000hh + 00hhll00 -> llhhllhh
4077                 MOV             reg_a, rscratch, LSL #16@  llhhllhh -> llhh0000
4078                 MOVS            rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4079                 UPDATE_ZN
4080                 ADD2CYCLE
4081 .endm
4082
4083
4084 /**********************************************************************************************/
4085 /* RTI *************************************************************************************** */
4086 .macro          Op40X1M1
4087                 @ INDEX set, MEMORY set
4088                 BIC             rstatus,rstatus,#0xFF000000
4089                 PullBr
4090                 ORR             rstatus,rscratch,rstatus
4091                 PullWlow        rpc
4092                 TST             rstatus, #MASK_EMUL
4093                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4094                 BNE             2401f
4095                 PullBrLow
4096                 BIC             reg_p_bank,reg_p_bank,#0xFF
4097                 ORR             reg_p_bank,reg_p_bank,rscratch
4098 2401:
4099                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4100                 S9xSetPCBase
4101                 TST             rstatus, #MASK_INDEX
4102                 @ INDEX cleared & was set : 8->16
4103                 MOVEQ           reg_x,reg_x,LSR #8
4104                 MOVEQ           reg_y,reg_y,LSR #8
4105                 TST             rstatus, #MASK_MEM
4106                 @ MEMORY cleared & was set : 8->16
4107                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4108                 MOVEQ           reg_a,reg_a,LSR #8
4109                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4110                 ADD2CYCLE
4111                 S9xFixCycles
4112 .endm
4113 .macro          Op40X0M1
4114                 @ INDEX cleared, MEMORY set
4115                 BIC             rstatus,rstatus,#0xFF000000
4116                 PullBr
4117                 ORR             rstatus,rscratch,rstatus
4118                 PullWlow        rpc
4119                 TST             rstatus, #MASK_EMUL
4120                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4121                 BNE             2401f
4122                 PullBrLow
4123                 BIC             reg_p_bank,reg_p_bank,#0xFF
4124                 ORR             reg_p_bank,reg_p_bank,rscratch
4125 2401:
4126                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4127                 S9xSetPCBase
4128                 TST             rstatus, #MASK_INDEX
4129                 @ INDEX set & was cleared : 16->8
4130                 MOVNE           reg_x,reg_x,LSL #8
4131                 MOVNE           reg_y,reg_y,LSL #8
4132                 TST             rstatus, #MASK_MEM
4133                 @ MEMORY cleared & was set : 8->16
4134                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4135                 MOVEQ           reg_a,reg_a,LSR #8
4136                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4137                 ADD2CYCLE
4138                 S9xFixCycles
4139 .endm
4140 .macro          Op40X1M0
4141                 @ INDEX set, MEMORY cleared
4142                 BIC             rstatus,rstatus,#0xFF000000
4143                 PullBr
4144                 ORR             rstatus,rscratch,rstatus
4145                 PullWlow        rpc
4146                 TST             rstatus, #MASK_EMUL
4147                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4148                 BNE             2401f
4149                 PullBrLow
4150                 BIC             reg_p_bank,reg_p_bank,#0xFF
4151                 ORR             reg_p_bank,reg_p_bank,rscratch
4152 2401:
4153                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4154                 S9xSetPCBase
4155                 TST             rstatus, #MASK_INDEX
4156                 @ INDEX cleared & was set : 8->16
4157                 MOVEQ           reg_x,reg_x,LSR #8
4158                 MOVEQ           reg_y,reg_y,LSR #8
4159                 TST             rstatus, #MASK_MEM
4160                 @ MEMORY set & was cleared : 16->8
4161                 MOVNE           rscratch,reg_a,LSR #24
4162                 MOVNE           reg_a,reg_a,LSL #8
4163                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4164                 ADD2CYCLE
4165                 S9xFixCycles
4166 .endm
4167 .macro          Op40X0M0
4168                 @ INDEX cleared, MEMORY cleared
4169                 BIC             rstatus,rstatus,#0xFF000000
4170                 PullBr
4171                 ORR             rstatus,rscratch,rstatus
4172                 PullWlow        rpc
4173                 TST             rstatus, #MASK_EMUL
4174                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4175                 BNE             2401f
4176                 PullBrLow
4177                 BIC             reg_p_bank,reg_p_bank,#0xFF
4178                 ORR             reg_p_bank,reg_p_bank,rscratch
4179 2401:
4180                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4181                 S9xSetPCBase
4182                 TST             rstatus, #MASK_INDEX
4183                 @ INDEX set & was cleared : 16->8
4184                 MOVNE           reg_x,reg_x,LSL #8
4185                 MOVNE           reg_y,reg_y,LSL #8
4186                 TST             rstatus, #MASK_MEM
4187                 @ MEMORY set & was cleared : 16->8
4188                 @ MEMORY set & was cleared : 16->8
4189                 MOVNE           rscratch,reg_a,LSR #24
4190                 MOVNE           reg_a,reg_a,LSL #8
4191                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4192                 ADD2CYCLE
4193                 S9xFixCycles
4194 .endm
4195
4196
4197 /**********************************************************************************************/
4198 /* STP/WAI/DB ******************************************************************************** */
4199 @  WAI
4200 .macro          OpCB    /*WAI*/
4201         LDRB            rscratch,[reg_cpu_var,#IRQActive_ofs]
4202         MOVS            rscratch,rscratch
4203         @ (CPU.IRQActive)
4204         ADD2CYCLENE
4205         BNE             1234f
4206 /*
4207         CPU.WaitingForInterrupt = TRUE;
4208         CPU.PC--;*/
4209         MOV             rscratch,#1
4210         SUB             rpc,rpc,#1
4211 /*
4212             CPU.Cycles = CPU.NextEvent;
4213 */
4214         STRB            rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4215         LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4216 /*
4217         if (IAPU.APUExecuting)
4218             {
4219                 ICPU.CPUExecuting = FALSE;
4220                 do
4221                 {
4222                     APU_EXECUTE1 ();
4223                 } while (APU.Cycles < CPU.NextEvent);
4224                 ICPU.CPUExecuting = TRUE;
4225             }
4226 */
4227         LDRB            rscratch,[reg_cpu_var,#APUExecuting_ofs]
4228         MOVS            rscratch,rscratch
4229         BEQ             1234f
4230         asmAPU_EXECUTE2
4231
4232 1234:
4233 .endm
4234 .macro          OpDB    /*STP*/
4235                 SUB     rpc,rpc,#1
4236                 @ CPU.Flags |= DEBUG_MODE_FLAG;
4237 .endm
4238 .macro          Op42   /*Reserved Snes9X*/
4239 .endm
4240
4241 /**********************************************************************************************/
4242 /* AND ******************************************************************************** */
4243 .macro          Op29M1
4244                 LDRB    rscratch    , [rpc], #1
4245                 ANDS    reg_a    , reg_a,       rscratch, LSL #24
4246                 UPDATE_ZN
4247                 ADD1MEM
4248 .endm
4249 .macro          Op29M0
4250                 LDRB    rscratch2  , [rpc,#1]
4251                 LDRB    rscratch   , [rpc], #2
4252                 ORR     rscratch, rscratch, rscratch2, LSL #8
4253                 ANDS    reg_a    , reg_a,       rscratch, LSL #16
4254                 UPDATE_ZN
4255                 ADD2MEM
4256 .endm
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272 /**********************************************************************************************/
4273 /* EOR ******************************************************************************** */
4274 .macro          Op49M0
4275                 LDRB    rscratch2 , [rpc, #1]
4276                 LDRB    rscratch , [rpc], #2
4277                 ORR     rscratch, rscratch, rscratch2,LSL #8
4278                 EORS    reg_a, reg_a, rscratch,LSL #16
4279                 UPDATE_ZN
4280                 ADD2MEM
4281 .endm
4282
4283
4284 .macro          Op49M1
4285                 LDRB    rscratch , [rpc], #1
4286                 EORS    reg_a, reg_a, rscratch,LSL #24
4287                 UPDATE_ZN
4288                 ADD1MEM
4289 .endm
4290
4291
4292 /**********************************************************************************************/
4293 /* STA *************************************************************************************** */
4294 .macro          Op81M1
4295                 STA8
4296                 @ TST           rstatus, #MASK_INDEX
4297                 @ ADD1CYCLENE
4298 .endm
4299 .macro          Op81M0
4300                 STA16
4301                 @ TST rstatus, #MASK_INDEX
4302                 @ ADD1CYCLENE
4303 .endm
4304
4305
4306 /**********************************************************************************************/
4307 /* BIT *************************************************************************************** */
4308 .macro          Op89M1
4309                 LDRB    rscratch , [rpc], #1
4310                 TST     reg_a, rscratch, LSL #24
4311                 UPDATE_Z
4312                 ADD1MEM
4313 .endm
4314 .macro          Op89M0
4315                 LDRB    rscratch2 , [rpc, #1]
4316                 LDRB    rscratch , [rpc], #2
4317                 ORR     rscratch, rscratch, rscratch2, LSL #8
4318                 TST     reg_a, rscratch, LSL #16
4319                 UPDATE_Z
4320                 ADD2MEM
4321 .endm
4322
4323
4324
4325
4326
4327
4328 /**********************************************************************************************/
4329 /* LDY *************************************************************************************** */
4330 .macro          OpA0X1
4331                 LDRB    rscratch , [rpc], #1
4332                 MOVS    reg_y, rscratch, LSL #24
4333                 UPDATE_ZN
4334                 ADD1MEM
4335 .endm
4336 .macro          OpA0X0
4337                 LDRB    rscratch2 , [rpc, #1]
4338                 LDRB    rscratch , [rpc], #2
4339                 ORR     rscratch, rscratch, rscratch2, LSL #8
4340                 MOVS    reg_y, rscratch, LSL #16
4341                 UPDATE_ZN
4342                 ADD2MEM
4343 .endm
4344
4345 /**********************************************************************************************/
4346 /* LDX *************************************************************************************** */
4347 .macro          OpA2X1
4348                 LDRB    rscratch , [rpc], #1
4349                 MOVS    reg_x, rscratch, LSL #24
4350                 UPDATE_ZN
4351                 ADD1MEM
4352 .endm
4353 .macro          OpA2X0
4354                 LDRB    rscratch2 , [rpc, #1]
4355                 LDRB    rscratch , [rpc], #2
4356                 ORR     rscratch, rscratch, rscratch2, LSL #8
4357                 MOVS    reg_x, rscratch, LSL #16
4358                 UPDATE_ZN
4359                 ADD2MEM
4360 .endm
4361
4362 /**********************************************************************************************/
4363 /* LDA *************************************************************************************** */
4364 .macro          OpA9M1
4365                 LDRB    rscratch , [rpc], #1
4366                 MOVS    reg_a, rscratch, LSL #24
4367                 UPDATE_ZN
4368                 ADD1MEM
4369 .endm
4370 .macro          OpA9M0
4371                 LDRB    rscratch2 , [rpc, #1]
4372                 LDRB    rscratch , [rpc], #2
4373                 ORR     rscratch, rscratch, rscratch2, LSL #8
4374                 MOVS    reg_a, rscratch, LSL #16
4375                 UPDATE_ZN
4376                 ADD2MEM
4377 .endm
4378
4379 /**********************************************************************************************/
4380 /* CMY *************************************************************************************** */
4381 .macro          OpC0X1
4382                 LDRB    rscratch    , [rpc], #1
4383                 SUBS    rscratch2   , reg_y , rscratch, LSL #24
4384                 BICCC   rstatus, rstatus, #MASK_CARRY
4385                 ORRCS   rstatus, rstatus, #MASK_CARRY
4386                 UPDATE_ZN
4387                 ADD1MEM
4388 .endm
4389 .macro          OpC0X0
4390                 LDRB    rscratch2   , [rpc, #1]
4391                 LDRB    rscratch   , [rpc], #2
4392                 ORR     rscratch, rscratch, rscratch2, LSL #8
4393                 SUBS    rscratch2   , reg_y, rscratch, LSL #16
4394                 BICCC   rstatus, rstatus, #MASK_CARRY
4395                 ORRCS   rstatus, rstatus, #MASK_CARRY
4396                 UPDATE_ZN
4397                 ADD2MEM
4398 .endm
4399
4400
4401
4402
4403
4404 /**********************************************************************************************/
4405 /* CMP *************************************************************************************** */
4406 .macro          OpC9M1
4407                 LDRB    rscratch    , [rpc], #1
4408                 SUBS    rscratch2   , reg_a , rscratch, LSL #24
4409                 BICCC   rstatus, rstatus, #MASK_CARRY
4410                 ORRCS   rstatus, rstatus, #MASK_CARRY
4411                 UPDATE_ZN
4412                 ADD1MEM
4413 .endm
4414 .macro          OpC9M0
4415                 LDRB    rscratch2   , [rpc,#1]
4416                 LDRB    rscratch   , [rpc], #2
4417                 ORR     rscratch, rscratch, rscratch2, LSL #8
4418                 SUBS    rscratch2   , reg_a, rscratch, LSL #16
4419                 BICCC   rstatus, rstatus, #MASK_CARRY
4420                 ORRCS   rstatus, rstatus, #MASK_CARRY
4421                 UPDATE_ZN
4422                 ADD2MEM
4423 .endm
4424
4425 /**********************************************************************************************/
4426 /* CMX *************************************************************************************** */
4427 .macro          OpE0X1
4428                 LDRB    rscratch    , [rpc], #1
4429                 SUBS    rscratch2   , reg_x , rscratch, LSL #24
4430                 BICCC   rstatus, rstatus, #MASK_CARRY
4431                 ORRCS   rstatus, rstatus, #MASK_CARRY
4432                 UPDATE_ZN
4433                 ADD1MEM
4434 .endm
4435 .macro          OpE0X0
4436                 LDRB    rscratch2   , [rpc,#1]
4437                 LDRB    rscratch   , [rpc], #2
4438                 ORR     rscratch, rscratch, rscratch2, LSL #8
4439                 SUBS    rscratch2   , reg_x, rscratch, LSL #16
4440                 BICCC   rstatus, rstatus, #MASK_CARRY
4441                 ORRCS   rstatus, rstatus, #MASK_CARRY
4442                 UPDATE_ZN
4443                 ADD2MEM
4444 .endm
4445
4446 /*
4447
4448
4449 CLI_OPE_REC_Nos_Layer0
4450         nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103)
4451         nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103)
4452
4453 CLI_OPE_Nos_Ope_Layer0
4454         n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
4455         n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
4456
4457 CLI_OPE_Nos_Layer0
4458         nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
4459         nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
4460
4461 Ecrans:
4462 ------
4463
4464
4465 [GNV] : utilisation de la lard (laccdate) pour afficher les openings.
4466    +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate
4467
4468 [Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée
4469 sinon :
4470   +données nécessaires : opening date tréso=date compta=laccdate=BD-1
4471   +données nécessaires : opening date tréso=date compta=laccdate-1
4472   +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate
4473    */
4474
4475
4476
4477 /****************************************************************
4478         GLOBAL
4479 ****************************************************************/
4480         .globl   test_opcode
4481         .globl   asmMainLoop
4482
4483
4484 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4485 asmMainLoop:
4486         @ save registers
4487         STMFD           R13!,{R4-R11,LR}
4488         @ init pointer to CPUvar structure
4489         MOV             reg_cpu_var,R0
4490         @ init registers
4491         LOAD_REGS
4492         @ get cpu mode from flag and init jump table
4493         S9xFixCycles
4494
4495 mainLoop:
4496         @ APU Execute
4497         asmAPU_EXECUTE
4498
4499         @ Test Flags
4500         LDR             rscratch,[reg_cpu_var,#Flags_ofs]
4501         MOVS            rscratch,rscratch
4502         BNE             CPUFlags_set    @ If flags => check for irq/nmi/scan_keys...
4503
4504         EXEC_OP                                         @ Execute next opcode
4505
4506 CPUFlags_set:   @ Check flags (!=0)
4507                 TST     rscratch,#NMI_FLAG              @ Check NMI
4508                 BEQ     CPUFlagsNMI_FLAG_cleared
4509                 LDR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4510                 SUBS    rscratch2,rscratch2,#1
4511                 STR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4512                 BNE     CPUFlagsNMI_FLAG_cleared
4513                 BIC     rscratch,rscratch,#NMI_FLAG
4514                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4515                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4516                 MOVS    rscratch2,rscratch2
4517                 BEQ     NotCPUaitingForInterruptNMI
4518                 MOV     rscratch2,#0
4519                 ADD     rpc,rpc,#1
4520                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4521 NotCPUaitingForInterruptNMI:
4522                 S9xOpcode_NMI
4523                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4524 CPUFlagsNMI_FLAG_cleared:
4525                 TST     rscratch,#IRQ_PENDING_FLAG   @ Check IRQ_PENDING_FLAG
4526                 BEQ     CPUFlagsIRQ_PENDING_FLAG_cleared
4527                 LDR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4528                 MOVS    rscratch2,rscratch2
4529                 BNE     CPUIRQCycleCount_NotZero
4530                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4531                 MOVS    rscratch2,rscratch2
4532                 BEQ     NotCPUaitingForInterruptIRQ
4533                 MOV     rscratch2,#0
4534                 ADD     rpc,rpc,#1
4535                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4536 NotCPUaitingForInterruptIRQ:
4537                 LDRB    rscratch2,[reg_cpu_var,#IRQActive_ofs]
4538                 MOVS    rscratch2,rscratch2
4539                 BEQ     CPUIRQActive_cleared
4540                 TST     rstatus,#MASK_IRQ
4541                 BNE     CPUFlagsIRQ_PENDING_FLAG_cleared
4542                 S9xOpcode_IRQ
4543                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4544                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4545 CPUIRQActive_cleared:
4546                 BIC     rscratch,rscratch,#IRQ_PENDING_FLAG
4547                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4548                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4549 CPUIRQCycleCount_NotZero:
4550                 SUB     rscratch2,rscratch2,#1
4551                 STR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4552 CPUFlagsIRQ_PENDING_FLAG_cleared:
4553
4554                 TST     rscratch,#SCAN_KEYS_FLAG   @ Check SCAN_KEYS_FLAG
4555                 BNE     endmainLoop
4556
4557         EXEC_OP @ Execute next opcode
4558
4559 endmainLoop:
4560
4561     /*Registers.PC = CPU.PC - CPU.PCBase;
4562     S9xPackStatus ();
4563     APURegisters.PC = IAPU.PC - IAPU.RAM;
4564     S9xAPUPackStatus ();
4565
4566     if (CPU.Flags & SCAN_KEYS_FLAG)
4567     {
4568             S9xSyncSpeed ();
4569         CPU.Flags &= ~SCAN_KEYS_FLAG;
4570     }   */
4571 /********end*/
4572         SAVE_REGS
4573         LDMFD           R13!,{R4-R11,LR}
4574         MOV             PC,LR
4575 .pool
4576
4577 @ void test_opcode(struct asm_cpu_var *asm_var);
4578 test_opcode:
4579         @ save registers
4580         STMFD           R13!,{R4-R11,LR}
4581         @ init pointer to CPUvar structure
4582         MOV             reg_cpu_var,R0
4583         @ init registers
4584         LOAD_REGS
4585         @ get cpu mode from flag and init jump table
4586         S9xFixCycles
4587
4588         EXEC_OP
4589 .pool
4590
4591 /*****************************************************************
4592        ASM CODE
4593 *****************************************************************/
4594
4595
4596 jumptable1:             .long   Op00mod1
4597                         .long   Op01M1mod1
4598                         .long   Op02mod1
4599                         .long   Op03M1mod1
4600                         .long   Op04M1mod1
4601                         .long   Op05M1mod1
4602                         .long   Op06M1mod1
4603                         .long   Op07M1mod1
4604                         .long   Op08mod1
4605                         .long   Op09M1mod1
4606                         .long   Op0AM1mod1
4607                         .long   Op0Bmod1
4608                         .long   Op0CM1mod1
4609                         .long   Op0DM1mod1
4610                         .long   Op0EM1mod1
4611                         .long   Op0FM1mod1
4612                         .long   Op10mod1
4613                         .long   Op11M1mod1
4614                         .long   Op12M1mod1
4615                         .long   Op13M1mod1
4616                         .long   Op14M1mod1
4617                         .long   Op15M1mod1
4618                         .long   Op16M1mod1
4619                         .long   Op17M1mod1
4620                         .long   Op18mod1
4621                         .long   Op19M1mod1
4622                         .long   Op1AM1mod1
4623                         .long   Op1Bmod1
4624                         .long   Op1CM1mod1
4625                         .long   Op1DM1mod1
4626                         .long   Op1EM1mod1
4627                         .long   Op1FM1mod1
4628                         .long   Op20mod1
4629                         .long   Op21M1mod1
4630                         .long   Op22mod1
4631                         .long   Op23M1mod1
4632                         .long   Op24M1mod1
4633                         .long   Op25M1mod1
4634                         .long   Op26M1mod1
4635                         .long   Op27M1mod1
4636                         .long   Op28mod1
4637                         .long   Op29M1mod1
4638                         .long   Op2AM1mod1
4639                         .long   Op2Bmod1
4640                         .long   Op2CM1mod1
4641                         .long   Op2DM1mod1
4642                         .long   Op2EM1mod1
4643                         .long   Op2FM1mod1
4644                         .long   Op30mod1
4645                         .long   Op31M1mod1
4646                         .long   Op32M1mod1
4647                         .long   Op33M1mod1
4648                         .long   Op34M1mod1
4649                         .long   Op35M1mod1
4650                         .long   Op36M1mod1
4651                         .long   Op37M1mod1
4652                         .long   Op38mod1
4653                         .long   Op39M1mod1
4654                         .long   Op3AM1mod1
4655                         .long   Op3Bmod1
4656                         .long   Op3CM1mod1
4657                         .long   Op3DM1mod1
4658                         .long   Op3EM1mod1
4659                         .long   Op3FM1mod1
4660                         .long   Op40mod1
4661                         .long   Op41M1mod1
4662                         .long   Op42mod1
4663                         .long   Op43M1mod1
4664                         .long   Op44X1mod1
4665                         .long   Op45M1mod1
4666                         .long   Op46M1mod1
4667                         .long   Op47M1mod1
4668                         .long   Op48M1mod1
4669                         .long   Op49M1mod1
4670                         .long   Op4AM1mod1
4671                         .long   Op4Bmod1
4672                         .long   Op4Cmod1
4673                         .long   Op4DM1mod1
4674                         .long   Op4EM1mod1
4675                         .long   Op4FM1mod1
4676                         .long   Op50mod1
4677                         .long   Op51M1mod1
4678                         .long   Op52M1mod1
4679                         .long   Op53M1mod1
4680                         .long   Op54X1mod1
4681                         .long   Op55M1mod1
4682                         .long   Op56M1mod1
4683                         .long   Op57M1mod1
4684                         .long   Op58mod1
4685                         .long   Op59M1mod1
4686                         .long   Op5AX1mod1
4687                         .long   Op5Bmod1
4688                         .long   Op5Cmod1
4689                         .long   Op5DM1mod1
4690                         .long   Op5EM1mod1
4691                         .long   Op5FM1mod1
4692                         .long   Op60mod1
4693                         .long   Op61M1mod1
4694                         .long   Op62mod1
4695                         .long   Op63M1mod1
4696                         .long   Op64M1mod1
4697                         .long   Op65M1mod1
4698                         .long   Op66M1mod1
4699                         .long   Op67M1mod1
4700                         .long   Op68M1mod1
4701                         .long   Op69M1mod1
4702                         .long   Op6AM1mod1
4703                         .long   Op6Bmod1
4704                         .long   Op6Cmod1
4705                         .long   Op6DM1mod1
4706                         .long   Op6EM1mod1
4707                         .long   Op6FM1mod1
4708                         .long   Op70mod1
4709                         .long   Op71M1mod1
4710                         .long   Op72M1mod1
4711                         .long   Op73M1mod1
4712                         .long   Op74M1mod1
4713                         .long   Op75M1mod1
4714                         .long   Op76M1mod1
4715                         .long   Op77M1mod1
4716                         .long   Op78mod1
4717                         .long   Op79M1mod1
4718                         .long   Op7AX1mod1
4719                         .long   Op7Bmod1
4720                         .long   Op7Cmod1
4721                         .long   Op7DM1mod1
4722                         .long   Op7EM1mod1
4723                         .long   Op7FM1mod1
4724                         .long   Op80mod1
4725                         .long   Op81M1mod1
4726                         .long   Op82mod1
4727                         .long   Op83M1mod1
4728                         .long   Op84X1mod1
4729                         .long   Op85M1mod1
4730                         .long   Op86X1mod1
4731                         .long   Op87M1mod1
4732                         .long   Op88X1mod1
4733                         .long   Op89M1mod1
4734                         .long   Op8AM1mod1
4735                         .long   Op8Bmod1
4736                         .long   Op8CX1mod1
4737                         .long   Op8DM1mod1
4738                         .long   Op8EX1mod1
4739                         .long   Op8FM1mod1
4740                         .long   Op90mod1
4741                         .long   Op91M1mod1
4742                         .long   Op92M1mod1
4743                         .long   Op93M1mod1
4744                         .long   Op94X1mod1
4745                         .long   Op95M1mod1
4746                         .long   Op96X1mod1
4747                         .long   Op97M1mod1
4748                         .long   Op98M1mod1
4749                         .long   Op99M1mod1
4750                         .long   Op9Amod1
4751                         .long   Op9BX1mod1
4752                         .long   Op9CM1mod1
4753                         .long   Op9DM1mod1
4754                         .long   Op9EM1mod1
4755                         .long   Op9FM1mod1
4756                         .long   OpA0X1mod1
4757                         .long   OpA1M1mod1
4758                         .long   OpA2X1mod1
4759                         .long   OpA3M1mod1
4760                         .long   OpA4X1mod1
4761                         .long   OpA5M1mod1
4762                         .long   OpA6X1mod1
4763                         .long   OpA7M1mod1
4764                         .long   OpA8X1mod1
4765                         .long   OpA9M1mod1
4766                         .long   OpAAX1mod1
4767                         .long   OpABmod1
4768                         .long   OpACX1mod1
4769                         .long   OpADM1mod1
4770                         .long   OpAEX1mod1
4771                         .long   OpAFM1mod1
4772                         .long   OpB0mod1
4773                         .long   OpB1M1mod1
4774                         .long   OpB2M1mod1
4775                         .long   OpB3M1mod1
4776                         .long   OpB4X1mod1
4777                         .long   OpB5M1mod1
4778                         .long   OpB6X1mod1
4779                         .long   OpB7M1mod1
4780                         .long   OpB8mod1
4781                         .long   OpB9M1mod1
4782                         .long   OpBAX1mod1
4783                         .long   OpBBX1mod1
4784                         .long   OpBCX1mod1
4785                         .long   OpBDM1mod1
4786                         .long   OpBEX1mod1
4787                         .long   OpBFM1mod1
4788                         .long   OpC0X1mod1
4789                         .long   OpC1M1mod1
4790                         .long   OpC2mod1
4791                         .long   OpC3M1mod1
4792                         .long   OpC4X1mod1
4793                         .long   OpC5M1mod1
4794                         .long   OpC6M1mod1
4795                         .long   OpC7M1mod1
4796                         .long   OpC8X1mod1
4797                         .long   OpC9M1mod1
4798                         .long   OpCAX1mod1
4799                         .long   OpCBmod1
4800                         .long   OpCCX1mod1
4801                         .long   OpCDM1mod1
4802                         .long   OpCEM1mod1
4803                         .long   OpCFM1mod1
4804                         .long   OpD0mod1
4805                         .long   OpD1M1mod1
4806                         .long   OpD2M1mod1
4807                         .long   OpD3M1mod1
4808                         .long   OpD4mod1
4809                         .long   OpD5M1mod1
4810                         .long   OpD6M1mod1
4811                         .long   OpD7M1mod1
4812                         .long   OpD8mod1
4813                         .long   OpD9M1mod1
4814                         .long   OpDAX1mod1
4815                         .long   OpDBmod1
4816                         .long   OpDCmod1
4817                         .long   OpDDM1mod1
4818                         .long   OpDEM1mod1
4819                         .long   OpDFM1mod1
4820                         .long   OpE0X1mod1
4821                         .long   OpE1M1mod1
4822                         .long   OpE2mod1
4823                         .long   OpE3M1mod1
4824                         .long   OpE4X1mod1
4825                         .long   OpE5M1mod1
4826                         .long   OpE6M1mod1
4827                         .long   OpE7M1mod1
4828                         .long   OpE8X1mod1
4829                         .long   OpE9M1mod1
4830                         .long   OpEAmod1
4831                         .long   OpEBmod1
4832                         .long   OpECX1mod1
4833                         .long   OpEDM1mod1
4834                         .long   OpEEM1mod1
4835                         .long   OpEFM1mod1
4836                         .long   OpF0mod1
4837                         .long   OpF1M1mod1
4838                         .long   OpF2M1mod1
4839                         .long   OpF3M1mod1
4840                         .long   OpF4mod1
4841                         .long   OpF5M1mod1
4842                         .long   OpF6M1mod1
4843                         .long   OpF7M1mod1
4844                         .long   OpF8mod1
4845                         .long   OpF9M1mod1
4846                         .long   OpFAX1mod1
4847                         .long   OpFBmod1
4848                         .long   OpFCmod1
4849                         .long   OpFDM1mod1
4850                         .long   OpFEM1mod1
4851                         .long   OpFFM1mod1
4852
4853 Op00mod1:
4854 lbl00mod1:      Op00
4855                         NEXTOPCODE
4856 Op01M1mod1:
4857 lbl01mod1a:     DirectIndexedIndirect1
4858 lbl01mod1b:     ORA8
4859                         NEXTOPCODE
4860 Op02mod1:
4861 lbl02mod1:      Op02
4862                         NEXTOPCODE
4863 Op03M1mod1:
4864 lbl03mod1a:     StackasmRelative
4865 lbl03mod1b:     ORA8
4866                         NEXTOPCODE
4867 Op04M1mod1:
4868 lbl04mod1a:     Direct
4869 lbl04mod1b:     TSB8
4870                         NEXTOPCODE
4871 Op05M1mod1:
4872 lbl05mod1a:     Direct
4873 lbl05mod1b:     ORA8
4874                         NEXTOPCODE
4875 Op06M1mod1:
4876 lbl06mod1a:     Direct
4877 lbl06mod1b:     ASL8
4878                         NEXTOPCODE
4879 Op07M1mod1:
4880 lbl07mod1a:     DirectIndirectLong
4881 lbl07mod1b:     ORA8
4882                         NEXTOPCODE
4883 Op08mod1:
4884 lbl08mod1:      Op08
4885                         NEXTOPCODE
4886 Op09M1mod1:
4887 lbl09mod1:      Op09M1
4888                         NEXTOPCODE
4889 Op0AM1mod1:
4890 lbl0Amod1a:     A_ASL8
4891                         NEXTOPCODE
4892 Op0Bmod1:
4893 lbl0Bmod1:      Op0B
4894                         NEXTOPCODE
4895 Op0CM1mod1:
4896 lbl0Cmod1a:     Absolute
4897 lbl0Cmod1b:     TSB8
4898                         NEXTOPCODE
4899 Op0DM1mod1:
4900 lbl0Dmod1a:     Absolute
4901 lbl0Dmod1b:     ORA8
4902                         NEXTOPCODE
4903 Op0EM1mod1:
4904 lbl0Emod1a:     Absolute
4905 lbl0Emod1b:     ASL8
4906                         NEXTOPCODE
4907 Op0FM1mod1:
4908 lbl0Fmod1a:     AbsoluteLong
4909 lbl0Fmod1b:     ORA8
4910                         NEXTOPCODE
4911 Op10mod1:
4912 lbl10mod1:      Op10
4913                         NEXTOPCODE
4914 Op11M1mod1:
4915 lbl11mod1a:     DirectIndirectIndexed1
4916 lbl11mod1b:     ORA8
4917                         NEXTOPCODE
4918 Op12M1mod1:
4919 lbl12mod1a:     DirectIndirect
4920 lbl12mod1b:     ORA8
4921                         NEXTOPCODE
4922 Op13M1mod1:
4923 lbl13mod1a:     StackasmRelativeIndirectIndexed1
4924 lbl13mod1b:     ORA8
4925                         NEXTOPCODE
4926 Op14M1mod1:
4927 lbl14mod1a:     Direct
4928 lbl14mod1b:     TRB8
4929                         NEXTOPCODE
4930 Op15M1mod1:
4931 lbl15mod1a:     DirectIndexedX1
4932 lbl15mod1b:     ORA8
4933                         NEXTOPCODE
4934 Op16M1mod1:
4935 lbl16mod1a:     DirectIndexedX1
4936 lbl16mod1b:     ASL8
4937                         NEXTOPCODE
4938 Op17M1mod1:
4939 lbl17mod1a:     DirectIndirectIndexedLong1
4940 lbl17mod1b:     ORA8
4941                         NEXTOPCODE
4942 Op18mod1:
4943 lbl18mod1:      Op18
4944                         NEXTOPCODE
4945 Op19M1mod1:
4946 lbl19mod1a:     AbsoluteIndexedY1
4947 lbl19mod1b:     ORA8
4948                         NEXTOPCODE
4949 Op1AM1mod1:
4950 lbl1Amod1a:     A_INC8
4951                         NEXTOPCODE
4952 Op1Bmod1:
4953 lbl1Bmod1:      Op1BM1
4954                         NEXTOPCODE
4955 Op1CM1mod1:
4956 lbl1Cmod1a:     Absolute
4957 lbl1Cmod1b:     TRB8
4958                         NEXTOPCODE
4959 Op1DM1mod1:
4960 lbl1Dmod1a:     AbsoluteIndexedX1
4961 lbl1Dmod1b:     ORA8
4962                         NEXTOPCODE
4963 Op1EM1mod1:
4964 lbl1Emod1a:     AbsoluteIndexedX1
4965 lbl1Emod1b:     ASL8
4966                         NEXTOPCODE
4967 Op1FM1mod1:
4968 lbl1Fmod1a:     AbsoluteLongIndexedX1
4969 lbl1Fmod1b:     ORA8
4970                         NEXTOPCODE
4971 Op20mod1:
4972 lbl20mod1:      Op20
4973                         NEXTOPCODE
4974 Op21M1mod1:
4975 lbl21mod1a:     DirectIndexedIndirect1
4976 lbl21mod1b:     AND8
4977                         NEXTOPCODE
4978 Op22mod1:
4979 lbl22mod1:      Op22
4980                         NEXTOPCODE
4981 Op23M1mod1:
4982 lbl23mod1a:     StackasmRelative
4983 lbl23mod1b:     AND8
4984                         NEXTOPCODE
4985 Op24M1mod1:
4986 lbl24mod1a:     Direct
4987 lbl24mod1b:     BIT8
4988                         NEXTOPCODE
4989 Op25M1mod1:
4990 lbl25mod1a:     Direct
4991 lbl25mod1b:     AND8
4992                         NEXTOPCODE
4993 Op26M1mod1:
4994 lbl26mod1a:     Direct
4995 lbl26mod1b:     ROL8
4996                         NEXTOPCODE
4997 Op27M1mod1:
4998 lbl27mod1a:     DirectIndirectLong
4999 lbl27mod1b:     AND8
5000                         NEXTOPCODE
5001 Op28mod1:
5002 lbl28mod1:      Op28X1M1
5003                         NEXTOPCODE
5004 .pool
5005 Op29M1mod1:
5006 lbl29mod1:      Op29M1
5007                         NEXTOPCODE
5008 Op2AM1mod1:
5009 lbl2Amod1a:     A_ROL8
5010                         NEXTOPCODE
5011 Op2Bmod1:
5012 lbl2Bmod1:      Op2B
5013                         NEXTOPCODE
5014 Op2CM1mod1:
5015 lbl2Cmod1a:     Absolute
5016 lbl2Cmod1b:     BIT8
5017                         NEXTOPCODE
5018 Op2DM1mod1:
5019 lbl2Dmod1a:     Absolute
5020 lbl2Dmod1b:     AND8
5021                         NEXTOPCODE
5022 Op2EM1mod1:
5023 lbl2Emod1a:     Absolute
5024 lbl2Emod1b:     ROL8
5025                         NEXTOPCODE
5026 Op2FM1mod1:
5027 lbl2Fmod1a:     AbsoluteLong
5028 lbl2Fmod1b:     AND8
5029                         NEXTOPCODE
5030 Op30mod1:
5031 lbl30mod1:      Op30
5032                         NEXTOPCODE
5033 Op31M1mod1:
5034 lbl31mod1a:     DirectIndirectIndexed1
5035 lbl31mod1b:     AND8
5036                         NEXTOPCODE
5037 Op32M1mod1:
5038 lbl32mod1a:     DirectIndirect
5039 lbl32mod1b:     AND8
5040                         NEXTOPCODE
5041 Op33M1mod1:
5042 lbl33mod1a:     StackasmRelativeIndirectIndexed1
5043 lbl33mod1b:     AND8
5044                         NEXTOPCODE
5045 Op34M1mod1:
5046 lbl34mod1a:     DirectIndexedX1
5047 lbl34mod1b:     BIT8
5048                         NEXTOPCODE
5049 Op35M1mod1:
5050 lbl35mod1a:     DirectIndexedX1
5051 lbl35mod1b:     AND8
5052                         NEXTOPCODE
5053 Op36M1mod1:
5054 lbl36mod1a:     DirectIndexedX1
5055 lbl36mod1b:     ROL8
5056                         NEXTOPCODE
5057 Op37M1mod1:
5058 lbl37mod1a:     DirectIndirectIndexedLong1
5059 lbl37mod1b:     AND8
5060                         NEXTOPCODE
5061 Op38mod1:
5062 lbl38mod1:      Op38
5063                         NEXTOPCODE
5064 Op39M1mod1:
5065 lbl39mod1a:     AbsoluteIndexedY1
5066 lbl39mod1b:     AND8
5067                         NEXTOPCODE
5068 Op3AM1mod1:
5069 lbl3Amod1a:     A_DEC8
5070                         NEXTOPCODE
5071 Op3Bmod1:
5072 lbl3Bmod1:      Op3BM1
5073                         NEXTOPCODE
5074 Op3CM1mod1:
5075 lbl3Cmod1a:     AbsoluteIndexedX1
5076 lbl3Cmod1b:     BIT8
5077                         NEXTOPCODE
5078 Op3DM1mod1:
5079 lbl3Dmod1a:     AbsoluteIndexedX1
5080 lbl3Dmod1b:     AND8
5081                         NEXTOPCODE
5082 Op3EM1mod1:
5083 lbl3Emod1a:     AbsoluteIndexedX1
5084 lbl3Emod1b:     ROL8
5085                         NEXTOPCODE
5086 Op3FM1mod1:
5087 lbl3Fmod1a:     AbsoluteLongIndexedX1
5088 lbl3Fmod1b:     AND8
5089                         NEXTOPCODE
5090 Op40mod1:
5091 lbl40mod1:      Op40X1M1
5092                         NEXTOPCODE
5093 .pool
5094 Op41M1mod1:
5095 lbl41mod1a:     DirectIndexedIndirect1
5096 lbl41mod1b:     EOR8
5097                         NEXTOPCODE
5098 Op42mod1:
5099 lbl42mod1:      Op42
5100                         NEXTOPCODE
5101 Op43M1mod1:
5102 lbl43mod1a:     StackasmRelative
5103 lbl43mod1b:     EOR8
5104                         NEXTOPCODE
5105 Op44X1mod1:
5106 lbl44mod1:      Op44X1M1
5107                         NEXTOPCODE
5108 Op45M1mod1:
5109 lbl45mod1a:     Direct
5110 lbl45mod1b:     EOR8
5111                         NEXTOPCODE
5112 Op46M1mod1:
5113 lbl46mod1a:     Direct
5114 lbl46mod1b:     LSR8
5115                         NEXTOPCODE
5116 Op47M1mod1:
5117 lbl47mod1a:     DirectIndirectLong
5118 lbl47mod1b:     EOR8
5119                         NEXTOPCODE
5120 Op48M1mod1:
5121 lbl48mod1:      Op48M1
5122                         NEXTOPCODE
5123 Op49M1mod1:
5124 lbl49mod1:      Op49M1
5125                         NEXTOPCODE
5126 Op4AM1mod1:
5127 lbl4Amod1a:     A_LSR8
5128                         NEXTOPCODE
5129 Op4Bmod1:
5130 lbl4Bmod1:      Op4B
5131                         NEXTOPCODE
5132 Op4Cmod1:
5133 lbl4Cmod1:      Op4C
5134                         NEXTOPCODE
5135 Op4DM1mod1:
5136 lbl4Dmod1a:     Absolute
5137 lbl4Dmod1b:     EOR8
5138                         NEXTOPCODE
5139 Op4EM1mod1:
5140 lbl4Emod1a:     Absolute
5141 lbl4Emod1b:     LSR8
5142                         NEXTOPCODE
5143 Op4FM1mod1:
5144 lbl4Fmod1a:     AbsoluteLong
5145 lbl4Fmod1b:     EOR8
5146                         NEXTOPCODE
5147 Op50mod1:
5148 lbl50mod1:      Op50
5149                         NEXTOPCODE
5150 Op51M1mod1:
5151 lbl51mod1a:     DirectIndirectIndexed1
5152 lbl51mod1b:     EOR8
5153                         NEXTOPCODE
5154 Op52M1mod1:
5155 lbl52mod1a:     DirectIndirect
5156 lbl52mod1b:     EOR8
5157                         NEXTOPCODE
5158 Op53M1mod1:
5159 lbl53mod1a:     StackasmRelativeIndirectIndexed1
5160 lbl53mod1b:     EOR8
5161                         NEXTOPCODE
5162 Op54X1mod1:
5163 lbl54mod1:      Op54X1M1
5164                         NEXTOPCODE
5165 Op55M1mod1:
5166 lbl55mod1a:     DirectIndexedX1
5167 lbl55mod1b:     EOR8
5168                         NEXTOPCODE
5169 Op56M1mod1:
5170 lbl56mod1a:     DirectIndexedX1
5171 lbl56mod1b:     LSR8
5172                         NEXTOPCODE
5173 Op57M1mod1:
5174 lbl57mod1a:     DirectIndirectIndexedLong1
5175 lbl57mod1b:     EOR8
5176                         NEXTOPCODE
5177 Op58mod1:
5178 lbl58mod1:      Op58
5179                         NEXTOPCODE
5180 Op59M1mod1:
5181 lbl59mod1a:     AbsoluteIndexedY1
5182 lbl59mod1b:     EOR8
5183                         NEXTOPCODE
5184 Op5AX1mod1:
5185 lbl5Amod1:      Op5AX1
5186                         NEXTOPCODE
5187 Op5Bmod1:
5188 lbl5Bmod1:      Op5BM1
5189                         NEXTOPCODE
5190 Op5Cmod1:
5191 lbl5Cmod1:      Op5C
5192                         NEXTOPCODE
5193 Op5DM1mod1:
5194 lbl5Dmod1a:     AbsoluteIndexedX1
5195 lbl5Dmod1b:     EOR8
5196                         NEXTOPCODE
5197 Op5EM1mod1:
5198 lbl5Emod1a:     AbsoluteIndexedX1
5199 lbl5Emod1b:     LSR8
5200                         NEXTOPCODE
5201 Op5FM1mod1:
5202 lbl5Fmod1a:     AbsoluteLongIndexedX1
5203 lbl5Fmod1b:     EOR8
5204                         NEXTOPCODE
5205 Op60mod1:
5206 lbl60mod1:      Op60
5207                         NEXTOPCODE
5208 Op61M1mod1:
5209 lbl61mod1a:     DirectIndexedIndirect1
5210 lbl61mod1b:     ADC8
5211                         NEXTOPCODE
5212 Op62mod1:
5213 lbl62mod1:      Op62
5214                         NEXTOPCODE
5215 Op63M1mod1:
5216 lbl63mod1a:     StackasmRelative
5217 lbl63mod1b:     ADC8
5218                         NEXTOPCODE
5219 Op64M1mod1:
5220 lbl64mod1a:     Direct
5221 lbl64mod1b:     STZ8
5222                         NEXTOPCODE
5223 Op65M1mod1:
5224 lbl65mod1a:     Direct
5225 lbl65mod1b:     ADC8
5226                         NEXTOPCODE
5227 Op66M1mod1:
5228 lbl66mod1a:     Direct
5229 lbl66mod1b:     ROR8
5230                         NEXTOPCODE
5231 Op67M1mod1:
5232 lbl67mod1a:     DirectIndirectLong
5233 lbl67mod1b:     ADC8
5234                         NEXTOPCODE
5235 Op68M1mod1:
5236 lbl68mod1:      Op68M1
5237                         NEXTOPCODE
5238 Op69M1mod1:
5239 lbl69mod1a:     Immediate8
5240 lbl69mod1b:     ADC8
5241                         NEXTOPCODE
5242 Op6AM1mod1:
5243 lbl6Amod1a:     A_ROR8
5244                         NEXTOPCODE
5245 Op6Bmod1:
5246 lbl6Bmod1:      Op6B
5247                         NEXTOPCODE
5248 Op6Cmod1:
5249 lbl6Cmod1:      Op6C
5250                         NEXTOPCODE
5251 Op6DM1mod1:
5252 lbl6Dmod1a:     Absolute
5253 lbl6Dmod1b:     ADC8
5254                         NEXTOPCODE
5255 Op6EM1mod1:
5256 lbl6Emod1a:     Absolute
5257 lbl6Emod1b:     ROR8
5258                         NEXTOPCODE
5259 Op6FM1mod1:
5260 lbl6Fmod1a:     AbsoluteLong
5261 lbl6Fmod1b:     ADC8
5262                         NEXTOPCODE
5263 Op70mod1:
5264 lbl70mod1:      Op70
5265                         NEXTOPCODE
5266 Op71M1mod1:
5267 lbl71mod1a:     DirectIndirectIndexed1
5268 lbl71mod1b:     ADC8
5269                         NEXTOPCODE
5270 Op72M1mod1:
5271 lbl72mod1a:     DirectIndirect
5272 lbl72mod1b:     ADC8
5273                         NEXTOPCODE
5274 Op73M1mod1:
5275 lbl73mod1a:     StackasmRelativeIndirectIndexed1
5276 lbl73mod1b:     ADC8
5277                         NEXTOPCODE
5278
5279 Op74M1mod1:
5280 lbl74mod1a:     DirectIndexedX1
5281 lbl74mod1b:     STZ8
5282                         NEXTOPCODE
5283 Op75M1mod1:
5284 lbl75mod1a:     DirectIndexedX1
5285 lbl75mod1b:     ADC8
5286                         NEXTOPCODE
5287 Op76M1mod1:
5288 lbl76mod1a:     DirectIndexedX1
5289 lbl76mod1b:     ROR8
5290                         NEXTOPCODE
5291 Op77M1mod1:
5292 lbl77mod1a:     DirectIndirectIndexedLong1
5293 lbl77mod1b:     ADC8
5294                         NEXTOPCODE
5295 Op78mod1:
5296 lbl78mod1:      Op78
5297                         NEXTOPCODE
5298 Op79M1mod1:
5299 lbl79mod1a:     AbsoluteIndexedY1
5300 lbl79mod1b:     ADC8
5301                         NEXTOPCODE
5302 Op7AX1mod1:
5303 lbl7Amod1:      Op7AX1
5304                         NEXTOPCODE
5305 Op7Bmod1:
5306 lbl7Bmod1:      Op7BM1
5307                         NEXTOPCODE
5308 Op7Cmod1:
5309 lbl7Cmod1:      AbsoluteIndexedIndirectX1
5310                 Op7C
5311                         NEXTOPCODE
5312 Op7DM1mod1:
5313 lbl7Dmod1a:     AbsoluteIndexedX1
5314 lbl7Dmod1b:     ADC8
5315                         NEXTOPCODE
5316 Op7EM1mod1:
5317 lbl7Emod1a:     AbsoluteIndexedX1
5318 lbl7Emod1b:     ROR8
5319                         NEXTOPCODE
5320 Op7FM1mod1:
5321 lbl7Fmod1a:     AbsoluteLongIndexedX1
5322 lbl7Fmod1b:     ADC8
5323                         NEXTOPCODE
5324
5325
5326 Op80mod1:
5327 lbl80mod1:      Op80
5328                         NEXTOPCODE
5329 Op81M1mod1:
5330 lbl81mod1a:     DirectIndexedIndirect1
5331 lbl81mod1b:     Op81M1
5332                         NEXTOPCODE
5333 Op82mod1:
5334 lbl82mod1:      Op82
5335                         NEXTOPCODE
5336 Op83M1mod1:
5337 lbl83mod1a:     StackasmRelative
5338 lbl83mod1b:     STA8
5339                         NEXTOPCODE
5340 Op84X1mod1:
5341 lbl84mod1a:     Direct
5342 lbl84mod1b:     STY8
5343                         NEXTOPCODE
5344 Op85M1mod1:
5345 lbl85mod1a:     Direct
5346 lbl85mod1b:     STA8
5347                         NEXTOPCODE
5348 Op86X1mod1:
5349 lbl86mod1a:     Direct
5350 lbl86mod1b:     STX8
5351                         NEXTOPCODE
5352 Op87M1mod1:
5353 lbl87mod1a:     DirectIndirectLong
5354 lbl87mod1b:     STA8
5355                         NEXTOPCODE
5356 Op88X1mod1:
5357 lbl88mod1:      Op88X1
5358                         NEXTOPCODE
5359 Op89M1mod1:
5360 lbl89mod1:      Op89M1
5361                         NEXTOPCODE
5362 Op8AM1mod1:
5363 lbl8Amod1:      Op8AM1X1
5364                         NEXTOPCODE
5365 Op8Bmod1:
5366 lbl8Bmod1:      Op8B
5367                         NEXTOPCODE
5368 Op8CX1mod1:
5369 lbl8Cmod1a:     Absolute
5370 lbl8Cmod1b:     STY8
5371                         NEXTOPCODE
5372 Op8DM1mod1:
5373 lbl8Dmod1a:     Absolute
5374 lbl8Dmod1b:     STA8
5375                         NEXTOPCODE
5376 Op8EX1mod1:
5377 lbl8Emod1a:     Absolute
5378 lbl8Emod1b:     STX8
5379                         NEXTOPCODE
5380 Op8FM1mod1:
5381 lbl8Fmod1a:     AbsoluteLong
5382 lbl8Fmod1b:     STA8
5383                         NEXTOPCODE
5384 Op90mod1:
5385 lbl90mod1:      Op90
5386                         NEXTOPCODE
5387 Op91M1mod1:
5388 lbl91mod1a:     DirectIndirectIndexed1
5389 lbl91mod1b:     STA8
5390                         NEXTOPCODE
5391 Op92M1mod1:
5392 lbl92mod1a:     DirectIndirect
5393 lbl92mod1b:     STA8
5394                         NEXTOPCODE
5395 Op93M1mod1:
5396 lbl93mod1a:     StackasmRelativeIndirectIndexed1
5397 lbl93mod1b:     STA8
5398                         NEXTOPCODE
5399 Op94X1mod1:
5400 lbl94mod1a:     DirectIndexedX1
5401 lbl94mod1b:     STY8
5402                         NEXTOPCODE
5403 Op95M1mod1:
5404 lbl95mod1a:     DirectIndexedX1
5405 lbl95mod1b:     STA8
5406                         NEXTOPCODE
5407 Op96X1mod1:
5408 lbl96mod1a:     DirectIndexedY1
5409 lbl96mod1b:     STX8
5410                         NEXTOPCODE
5411 Op97M1mod1:
5412 lbl97mod1a:     DirectIndirectIndexedLong1
5413 lbl97mod1b:     STA8
5414                         NEXTOPCODE
5415 Op98M1mod1:
5416 lbl98mod1:      Op98M1X1
5417                         NEXTOPCODE
5418 Op99M1mod1:
5419 lbl99mod1a:     AbsoluteIndexedY1
5420 lbl99mod1b:     STA8
5421                         NEXTOPCODE
5422 Op9Amod1:
5423 lbl9Amod1:      Op9AX1
5424                         NEXTOPCODE
5425 Op9BX1mod1:
5426 lbl9Bmod1:      Op9BX1
5427                         NEXTOPCODE
5428 Op9CM1mod1:
5429 lbl9Cmod1a:     Absolute
5430 lbl9Cmod1b:     STZ8
5431                         NEXTOPCODE
5432 Op9DM1mod1:
5433 lbl9Dmod1a:     AbsoluteIndexedX1
5434 lbl9Dmod1b:     STA8
5435                         NEXTOPCODE
5436 Op9EM1mod1:
5437 lbl9Emod1:      AbsoluteIndexedX1
5438                 STZ8
5439                         NEXTOPCODE
5440 Op9FM1mod1:
5441 lbl9Fmod1a:     AbsoluteLongIndexedX1
5442 lbl9Fmod1b:     STA8
5443                         NEXTOPCODE
5444 OpA0X1mod1:
5445 lblA0mod1:      OpA0X1
5446                         NEXTOPCODE
5447 OpA1M1mod1:
5448 lblA1mod1a:     DirectIndexedIndirect1
5449 lblA1mod1b:     LDA8
5450                         NEXTOPCODE
5451 OpA2X1mod1:
5452 lblA2mod1:      OpA2X1
5453                         NEXTOPCODE
5454 OpA3M1mod1:
5455 lblA3mod1a:     StackasmRelative
5456 lblA3mod1b:     LDA8
5457                         NEXTOPCODE
5458 OpA4X1mod1:
5459 lblA4mod1a:     Direct
5460 lblA4mod1b:     LDY8
5461                         NEXTOPCODE
5462 OpA5M1mod1:
5463 lblA5mod1a:     Direct
5464 lblA5mod1b:     LDA8
5465                         NEXTOPCODE
5466 OpA6X1mod1:
5467 lblA6mod1a:     Direct
5468 lblA6mod1b:     LDX8
5469                         NEXTOPCODE
5470 OpA7M1mod1:
5471 lblA7mod1a:     DirectIndirectLong
5472 lblA7mod1b:     LDA8
5473                         NEXTOPCODE
5474 OpA8X1mod1:
5475 lblA8mod1:      OpA8X1M1
5476                         NEXTOPCODE
5477 OpA9M1mod1:
5478 lblA9mod1:      OpA9M1
5479                         NEXTOPCODE
5480 OpAAX1mod1:
5481 lblAAmod1:      OpAAX1M1
5482                         NEXTOPCODE
5483 OpABmod1:
5484 lblABmod1:      OpAB
5485                         NEXTOPCODE
5486 OpACX1mod1:
5487 lblACmod1a:     Absolute
5488 lblACmod1b:     LDY8
5489                         NEXTOPCODE
5490 OpADM1mod1:
5491 lblADmod1a:     Absolute
5492 lblADmod1b:     LDA8
5493                         NEXTOPCODE
5494 OpAEX1mod1:
5495 lblAEmod1a:     Absolute
5496 lblAEmod1b:     LDX8
5497                         NEXTOPCODE
5498 OpAFM1mod1:
5499 lblAFmod1a:     AbsoluteLong
5500 lblAFmod1b:     LDA8
5501                         NEXTOPCODE
5502 OpB0mod1:
5503 lblB0mod1:      OpB0
5504                         NEXTOPCODE
5505 OpB1M1mod1:
5506 lblB1mod1a:     DirectIndirectIndexed1
5507 lblB1mod1b:     LDA8
5508                         NEXTOPCODE
5509 OpB2M1mod1:
5510 lblB2mod1a:     DirectIndirect
5511 lblB2mod1b:     LDA8
5512                         NEXTOPCODE
5513 OpB3M1mod1:
5514 lblB3mod1a:     StackasmRelativeIndirectIndexed1
5515 lblB3mod1b:     LDA8
5516                         NEXTOPCODE
5517 OpB4X1mod1:
5518 lblB4mod1a:     DirectIndexedX1
5519 lblB4mod1b:     LDY8
5520                         NEXTOPCODE
5521 OpB5M1mod1:
5522 lblB5mod1a:     DirectIndexedX1
5523 lblB5mod1b:     LDA8
5524                         NEXTOPCODE
5525 OpB6X1mod1:
5526 lblB6mod1a:     DirectIndexedY1
5527 lblB6mod1b:     LDX8
5528                         NEXTOPCODE
5529 OpB7M1mod1:
5530 lblB7mod1a:     DirectIndirectIndexedLong1
5531 lblB7mod1b:     LDA8
5532                         NEXTOPCODE
5533 OpB8mod1:
5534 lblB8mod1:      OpB8
5535                         NEXTOPCODE
5536 OpB9M1mod1:
5537 lblB9mod1a:     AbsoluteIndexedY1
5538 lblB9mod1b:     LDA8
5539                         NEXTOPCODE
5540 OpBAX1mod1:
5541 lblBAmod1:      OpBAX1
5542                         NEXTOPCODE
5543 OpBBX1mod1:
5544 lblBBmod1:      OpBBX1
5545                         NEXTOPCODE
5546 OpBCX1mod1:
5547 lblBCmod1a:     AbsoluteIndexedX1
5548 lblBCmod1b:     LDY8
5549                         NEXTOPCODE
5550 OpBDM1mod1:
5551 lblBDmod1a:     AbsoluteIndexedX1
5552 lblBDmod1b:     LDA8
5553                         NEXTOPCODE
5554 OpBEX1mod1:
5555 lblBEmod1a:     AbsoluteIndexedY1
5556 lblBEmod1b:     LDX8
5557                         NEXTOPCODE
5558 OpBFM1mod1:
5559 lblBFmod1a:     AbsoluteLongIndexedX1
5560 lblBFmod1b:     LDA8
5561                         NEXTOPCODE
5562 OpC0X1mod1:
5563 lblC0mod1:      OpC0X1
5564                         NEXTOPCODE
5565 OpC1M1mod1:
5566 lblC1mod1a:     DirectIndexedIndirect1
5567 lblC1mod1b:     CMP8
5568                         NEXTOPCODE
5569 OpC2mod1:
5570 lblC2mod1:      OpC2
5571                         NEXTOPCODE
5572 .pool
5573 OpC3M1mod1:
5574 lblC3mod1a:     StackasmRelative
5575 lblC3mod1b:     CMP8
5576                         NEXTOPCODE
5577 OpC4X1mod1:
5578 lblC4mod1a:     Direct
5579 lblC4mod1b:     CMY8
5580                         NEXTOPCODE
5581 OpC5M1mod1:
5582 lblC5mod1a:     Direct
5583 lblC5mod1b:     CMP8
5584                         NEXTOPCODE
5585 OpC6M1mod1:
5586 lblC6mod1a:     Direct
5587 lblC6mod1b:     DEC8
5588                         NEXTOPCODE
5589 OpC7M1mod1:
5590 lblC7mod1a:     DirectIndirectLong
5591 lblC7mod1b:     CMP8
5592                         NEXTOPCODE
5593 OpC8X1mod1:
5594 lblC8mod1:      OpC8X1
5595                         NEXTOPCODE
5596 OpC9M1mod1:
5597 lblC9mod1:      OpC9M1
5598                         NEXTOPCODE
5599 OpCAX1mod1:
5600 lblCAmod1:      OpCAX1
5601                         NEXTOPCODE
5602 OpCBmod1:
5603 lblCBmod1:      OpCB
5604                         NEXTOPCODE
5605 OpCCX1mod1:
5606 lblCCmod1a:     Absolute
5607 lblCCmod1b:     CMY8
5608                         NEXTOPCODE
5609 OpCDM1mod1:
5610 lblCDmod1a:     Absolute
5611 lblCDmod1b:     CMP8
5612                         NEXTOPCODE
5613 OpCEM1mod1:
5614 lblCEmod1a:     Absolute
5615 lblCEmod1b:     DEC8
5616                         NEXTOPCODE
5617 OpCFM1mod1:
5618 lblCFmod1a:     AbsoluteLong
5619 lblCFmod1b:     CMP8
5620                         NEXTOPCODE
5621 OpD0mod1:
5622 lblD0mod1:      OpD0
5623                         NEXTOPCODE
5624 OpD1M1mod1:
5625 lblD1mod1a:     DirectIndirectIndexed1
5626 lblD1mod1b:     CMP8
5627                         NEXTOPCODE
5628 OpD2M1mod1:
5629 lblD2mod1a:     DirectIndirect
5630 lblD2mod1b:     CMP8
5631                         NEXTOPCODE
5632 OpD3M1mod1:
5633 lblD3mod1a:     StackasmRelativeIndirectIndexed1
5634 lblD3mod1b:     CMP8
5635                         NEXTOPCODE
5636 OpD4mod1:
5637 lblD4mod1:      OpD4
5638                         NEXTOPCODE
5639 OpD5M1mod1:
5640 lblD5mod1a:     DirectIndexedX1
5641 lblD5mod1b:     CMP8
5642                         NEXTOPCODE
5643 OpD6M1mod1:
5644 lblD6mod1a:     DirectIndexedX1
5645 lblD6mod1b:     DEC8
5646                         NEXTOPCODE
5647 OpD7M1mod1:
5648 lblD7mod1a:     DirectIndirectIndexedLong1
5649 lblD7mod1b:     CMP8
5650                         NEXTOPCODE
5651 OpD8mod1:
5652 lblD8mod1:      OpD8
5653                         NEXTOPCODE
5654 OpD9M1mod1:
5655 lblD9mod1a:     AbsoluteIndexedY1
5656 lblD9mod1b:     CMP8
5657                         NEXTOPCODE
5658 OpDAX1mod1:
5659 lblDAmod1:      OpDAX1
5660                         NEXTOPCODE
5661 OpDBmod1:
5662 lblDBmod1:      OpDB
5663                         NEXTOPCODE
5664 OpDCmod1:
5665 lblDCmod1:      OpDC
5666                         NEXTOPCODE
5667 OpDDM1mod1:
5668 lblDDmod1a:     AbsoluteIndexedX1
5669 lblDDmod1b:     CMP8
5670                         NEXTOPCODE
5671 OpDEM1mod1:
5672 lblDEmod1a:     AbsoluteIndexedX1
5673 lblDEmod1b:     DEC8
5674                         NEXTOPCODE
5675 OpDFM1mod1:
5676 lblDFmod1a:     AbsoluteLongIndexedX1
5677 lblDFmod1b:     CMP8
5678                         NEXTOPCODE
5679 OpE0X1mod1:
5680 lblE0mod1:      OpE0X1
5681                         NEXTOPCODE
5682 OpE1M1mod1:
5683 lblE1mod1a:     DirectIndexedIndirect1
5684 lblE1mod1b:     SBC8
5685                         NEXTOPCODE
5686 OpE2mod1:
5687 lblE2mod1:      OpE2
5688                         NEXTOPCODE
5689 .pool
5690 OpE3M1mod1:
5691 lblE3mod1a:     StackasmRelative
5692 lblE3mod1b:     SBC8
5693                         NEXTOPCODE
5694 OpE4X1mod1:
5695 lblE4mod1a:     Direct
5696 lblE4mod1b:     CMX8
5697                         NEXTOPCODE
5698 OpE5M1mod1:
5699 lblE5mod1a:     Direct
5700 lblE5mod1b:     SBC8
5701                         NEXTOPCODE
5702 OpE6M1mod1:
5703 lblE6mod1a:     Direct
5704 lblE6mod1b:     INC8
5705                         NEXTOPCODE
5706 OpE7M1mod1:
5707 lblE7mod1a:     DirectIndirectLong
5708 lblE7mod1b:     SBC8
5709                         NEXTOPCODE
5710 OpE8X1mod1:
5711 lblE8mod1:      OpE8X1
5712                         NEXTOPCODE
5713 OpE9M1mod1:
5714 lblE9mod1a:     Immediate8
5715 lblE9mod1b:     SBC8
5716                         NEXTOPCODE
5717 OpEAmod1:
5718 lblEAmod1:      OpEA
5719                         NEXTOPCODE
5720 OpEBmod1:
5721 lblEBmod1:      OpEBM1
5722                         NEXTOPCODE
5723 OpECX1mod1:
5724 lblECmod1a:     Absolute
5725 lblECmod1b:     CMX8
5726                         NEXTOPCODE
5727 OpEDM1mod1:
5728 lblEDmod1a:     Absolute
5729 lblEDmod1b:     SBC8
5730                         NEXTOPCODE
5731 OpEEM1mod1:
5732 lblEEmod1a:     Absolute
5733 lblEEmod1b:     INC8
5734                         NEXTOPCODE
5735 OpEFM1mod1:
5736 lblEFmod1a:     AbsoluteLong
5737 lblEFmod1b:     SBC8
5738                         NEXTOPCODE
5739 OpF0mod1:
5740 lblF0mod1:      OpF0
5741                         NEXTOPCODE
5742 OpF1M1mod1:
5743 lblF1mod1a:     DirectIndirectIndexed1
5744 lblF1mod1b:     SBC8
5745                         NEXTOPCODE
5746 OpF2M1mod1:
5747 lblF2mod1a:     DirectIndirect
5748 lblF2mod1b:     SBC8
5749                         NEXTOPCODE
5750 OpF3M1mod1:
5751 lblF3mod1a:     StackasmRelativeIndirectIndexed1
5752 lblF3mod1b:     SBC8
5753                         NEXTOPCODE
5754 OpF4mod1:
5755 lblF4mod1:      OpF4
5756                         NEXTOPCODE
5757 OpF5M1mod1:
5758 lblF5mod1a:     DirectIndexedX1
5759 lblF5mod1b:     SBC8
5760                         NEXTOPCODE
5761 OpF6M1mod1:
5762 lblF6mod1a:     DirectIndexedX1
5763 lblF6mod1b:     INC8
5764                         NEXTOPCODE
5765 OpF7M1mod1:
5766 lblF7mod1a:     DirectIndirectIndexedLong1
5767 lblF7mod1b:     SBC8
5768                         NEXTOPCODE
5769 OpF8mod1:
5770 lblF8mod1:      OpF8
5771                         NEXTOPCODE
5772 OpF9M1mod1:
5773 lblF9mod1a:     AbsoluteIndexedY1
5774 lblF9mod1b:     SBC8
5775                         NEXTOPCODE
5776 OpFAX1mod1:
5777 lblFAmod1:      OpFAX1
5778                         NEXTOPCODE
5779 OpFBmod1:
5780 lblFBmod1:      OpFB
5781                         NEXTOPCODE
5782 OpFCmod1:
5783 lblFCmod1:      OpFCX1
5784                         NEXTOPCODE
5785 OpFDM1mod1:
5786 lblFDmod1a:     AbsoluteIndexedX1
5787 lblFDmod1b:     SBC8
5788                         NEXTOPCODE
5789 OpFEM1mod1:
5790 lblFEmod1a:     AbsoluteIndexedX1
5791 lblFEmod1b:     INC8
5792                         NEXTOPCODE
5793 OpFFM1mod1:
5794 lblFFmod1a:     AbsoluteLongIndexedX1
5795 lblFFmod1b:     SBC8
5796                         NEXTOPCODE
5797 .pool
5798
5799
5800 jumptable2:             .long   Op00mod2
5801                         .long   Op01M1mod2
5802                         .long   Op02mod2
5803                         .long   Op03M1mod2
5804                         .long   Op04M1mod2
5805                         .long   Op05M1mod2
5806                         .long   Op06M1mod2
5807                         .long   Op07M1mod2
5808                         .long   Op08mod2
5809                         .long   Op09M1mod2
5810                         .long   Op0AM1mod2
5811                         .long   Op0Bmod2
5812                         .long   Op0CM1mod2
5813                         .long   Op0DM1mod2
5814                         .long   Op0EM1mod2
5815                         .long   Op0FM1mod2
5816                         .long   Op10mod2
5817                         .long   Op11M1mod2
5818                         .long   Op12M1mod2
5819                         .long   Op13M1mod2
5820                         .long   Op14M1mod2
5821                         .long   Op15M1mod2
5822                         .long   Op16M1mod2
5823                         .long   Op17M1mod2
5824                         .long   Op18mod2
5825                         .long   Op19M1mod2
5826                         .long   Op1AM1mod2
5827                         .long   Op1Bmod2
5828                         .long   Op1CM1mod2
5829                         .long   Op1DM1mod2
5830                         .long   Op1EM1mod2
5831                         .long   Op1FM1mod2
5832                         .long   Op20mod2
5833                         .long   Op21M1mod2
5834                         .long   Op22mod2
5835                         .long   Op23M1mod2
5836                         .long   Op24M1mod2
5837                         .long   Op25M1mod2
5838                         .long   Op26M1mod2
5839                         .long   Op27M1mod2
5840                         .long   Op28mod2
5841                         .long   Op29M1mod2
5842                         .long   Op2AM1mod2
5843                         .long   Op2Bmod2
5844                         .long   Op2CM1mod2
5845                         .long   Op2DM1mod2
5846                         .long   Op2EM1mod2
5847                         .long   Op2FM1mod2
5848                         .long   Op30mod2
5849                         .long   Op31M1mod2
5850                         .long   Op32M1mod2
5851                         .long   Op33M1mod2
5852                         .long   Op34M1mod2
5853                         .long   Op35M1mod2
5854                         .long   Op36M1mod2
5855                         .long   Op37M1mod2
5856                         .long   Op38mod2
5857                         .long   Op39M1mod2
5858                         .long   Op3AM1mod2
5859                         .long   Op3Bmod2
5860                         .long   Op3CM1mod2
5861                         .long   Op3DM1mod2
5862                         .long   Op3EM1mod2
5863                         .long   Op3FM1mod2
5864                         .long   Op40mod2
5865                         .long   Op41M1mod2
5866                         .long   Op42mod2
5867                         .long   Op43M1mod2
5868                         .long   Op44X0mod2
5869                         .long   Op45M1mod2
5870                         .long   Op46M1mod2
5871                         .long   Op47M1mod2
5872                         .long   Op48M1mod2
5873                         .long   Op49M1mod2
5874                         .long   Op4AM1mod2
5875                         .long   Op4Bmod2
5876                         .long   Op4Cmod2
5877                         .long   Op4DM1mod2
5878                         .long   Op4EM1mod2
5879                         .long   Op4FM1mod2
5880                         .long   Op50mod2
5881                         .long   Op51M1mod2
5882                         .long   Op52M1mod2
5883                         .long   Op53M1mod2
5884                         .long   Op54X0mod2
5885                         .long   Op55M1mod2
5886                         .long   Op56M1mod2
5887                         .long   Op57M1mod2
5888                         .long   Op58mod2
5889                         .long   Op59M1mod2
5890                         .long   Op5AX0mod2
5891                         .long   Op5Bmod2
5892                         .long   Op5Cmod2
5893                         .long   Op5DM1mod2
5894                         .long   Op5EM1mod2
5895                         .long   Op5FM1mod2
5896                         .long   Op60mod2
5897                         .long   Op61M1mod2
5898                         .long   Op62mod2
5899                         .long   Op63M1mod2
5900                         .long   Op64M1mod2
5901                         .long   Op65M1mod2
5902                         .long   Op66M1mod2
5903                         .long   Op67M1mod2
5904                         .long   Op68M1mod2
5905                         .long   Op69M1mod2
5906                         .long   Op6AM1mod2
5907                         .long   Op6Bmod2
5908                         .long   Op6Cmod2
5909                         .long   Op6DM1mod2
5910                         .long   Op6EM1mod2
5911                         .long   Op6FM1mod2
5912                         .long   Op70mod2
5913                         .long   Op71M1mod2
5914                         .long   Op72M1mod2
5915                         .long   Op73M1mod2
5916                         .long   Op74M1mod2
5917                         .long   Op75M1mod2
5918                         .long   Op76M1mod2
5919                         .long   Op77M1mod2
5920                         .long   Op78mod2
5921                         .long   Op79M1mod2
5922                         .long   Op7AX0mod2
5923                         .long   Op7Bmod2
5924                         .long   Op7Cmod2
5925                         .long   Op7DM1mod2
5926                         .long   Op7EM1mod2
5927                         .long   Op7FM1mod2
5928                         .long   Op80mod2
5929                         .long   Op81M1mod2
5930                         .long   Op82mod2
5931                         .long   Op83M1mod2
5932                         .long   Op84X0mod2
5933                         .long   Op85M1mod2
5934                         .long   Op86X0mod2
5935                         .long   Op87M1mod2
5936                         .long   Op88X0mod2
5937                         .long   Op89M1mod2
5938                         .long   Op8AM1mod2
5939                         .long   Op8Bmod2
5940                         .long   Op8CX0mod2
5941                         .long   Op8DM1mod2
5942                         .long   Op8EX0mod2
5943                         .long   Op8FM1mod2
5944                         .long   Op90mod2
5945                         .long   Op91M1mod2
5946                         .long   Op92M1mod2
5947                         .long   Op93M1mod2
5948                         .long   Op94X0mod2
5949                         .long   Op95M1mod2
5950                         .long   Op96X0mod2
5951                         .long   Op97M1mod2
5952                         .long   Op98M1mod2
5953                         .long   Op99M1mod2
5954                         .long   Op9Amod2
5955                         .long   Op9BX0mod2
5956                         .long   Op9CM1mod2
5957                         .long   Op9DM1mod2
5958                         .long   Op9EM1mod2
5959                         .long   Op9FM1mod2
5960                         .long   OpA0X0mod2
5961                         .long   OpA1M1mod2
5962                         .long   OpA2X0mod2
5963                         .long   OpA3M1mod2
5964                         .long   OpA4X0mod2
5965                         .long   OpA5M1mod2
5966                         .long   OpA6X0mod2
5967                         .long   OpA7M1mod2
5968                         .long   OpA8X0mod2
5969                         .long   OpA9M1mod2
5970                         .long   OpAAX0mod2
5971                         .long   OpABmod2
5972                         .long   OpACX0mod2
5973                         .long   OpADM1mod2
5974                         .long   OpAEX0mod2
5975                         .long   OpAFM1mod2
5976                         .long   OpB0mod2
5977                         .long   OpB1M1mod2
5978                         .long   OpB2M1mod2
5979                         .long   OpB3M1mod2
5980                         .long   OpB4X0mod2
5981                         .long   OpB5M1mod2
5982                         .long   OpB6X0mod2
5983                         .long   OpB7M1mod2
5984                         .long   OpB8mod2
5985                         .long   OpB9M1mod2
5986                         .long   OpBAX0mod2
5987                         .long   OpBBX0mod2
5988                         .long   OpBCX0mod2
5989                         .long   OpBDM1mod2
5990                         .long   OpBEX0mod2
5991                         .long   OpBFM1mod2
5992                         .long   OpC0X0mod2
5993                         .long   OpC1M1mod2
5994                         .long   OpC2mod2
5995                         .long   OpC3M1mod2
5996                         .long   OpC4X0mod2
5997                         .long   OpC5M1mod2
5998                         .long   OpC6M1mod2
5999                         .long   OpC7M1mod2
6000                         .long   OpC8X0mod2
6001                         .long   OpC9M1mod2
6002                         .long   OpCAX0mod2
6003                         .long   OpCBmod2
6004                         .long   OpCCX0mod2
6005                         .long   OpCDM1mod2
6006                         .long   OpCEM1mod2
6007                         .long   OpCFM1mod2
6008                         .long   OpD0mod2
6009                         .long   OpD1M1mod2
6010                         .long   OpD2M1mod2
6011                         .long   OpD3M1mod2
6012                         .long   OpD4mod2
6013                         .long   OpD5M1mod2
6014                         .long   OpD6M1mod2
6015                         .long   OpD7M1mod2
6016                         .long   OpD8mod2
6017                         .long   OpD9M1mod2
6018                         .long   OpDAX0mod2
6019                         .long   OpDBmod2
6020                         .long   OpDCmod2
6021                         .long   OpDDM1mod2
6022                         .long   OpDEM1mod2
6023                         .long   OpDFM1mod2
6024                         .long   OpE0X0mod2
6025                         .long   OpE1M1mod2
6026                         .long   OpE2mod2
6027                         .long   OpE3M1mod2
6028                         .long   OpE4X0mod2
6029                         .long   OpE5M1mod2
6030                         .long   OpE6M1mod2
6031                         .long   OpE7M1mod2
6032                         .long   OpE8X0mod2
6033                         .long   OpE9M1mod2
6034                         .long   OpEAmod2
6035                         .long   OpEBmod2
6036                         .long   OpECX0mod2
6037                         .long   OpEDM1mod2
6038                         .long   OpEEM1mod2
6039                         .long   OpEFM1mod2
6040                         .long   OpF0mod2
6041                         .long   OpF1M1mod2
6042                         .long   OpF2M1mod2
6043                         .long   OpF3M1mod2
6044                         .long   OpF4mod2
6045                         .long   OpF5M1mod2
6046                         .long   OpF6M1mod2
6047                         .long   OpF7M1mod2
6048                         .long   OpF8mod2
6049                         .long   OpF9M1mod2
6050                         .long   OpFAX0mod2
6051                         .long   OpFBmod2
6052                         .long   OpFCmod2
6053                         .long   OpFDM1mod2
6054                         .long   OpFEM1mod2
6055                         .long   OpFFM1mod2
6056 Op00mod2:
6057 lbl00mod2:      Op00
6058                         NEXTOPCODE
6059 Op01M1mod2:
6060 lbl01mod2a:     DirectIndexedIndirect0
6061 lbl01mod2b:     ORA8
6062                         NEXTOPCODE
6063 Op02mod2:
6064 lbl02mod2:      Op02
6065                         NEXTOPCODE
6066 Op03M1mod2:
6067 lbl03mod2a:     StackasmRelative
6068 lbl03mod2b:     ORA8
6069                         NEXTOPCODE
6070 Op04M1mod2:
6071 lbl04mod2a:     Direct
6072 lbl04mod2b:     TSB8
6073                         NEXTOPCODE
6074 Op05M1mod2:
6075 lbl05mod2a:     Direct
6076 lbl05mod2b:     ORA8
6077                         NEXTOPCODE
6078 Op06M1mod2:
6079 lbl06mod2a:     Direct
6080 lbl06mod2b:     ASL8
6081                         NEXTOPCODE
6082 Op07M1mod2:
6083 lbl07mod2a:     DirectIndirectLong
6084 lbl07mod2b:     ORA8
6085                         NEXTOPCODE
6086 Op08mod2:
6087 lbl08mod2:      Op08
6088                         NEXTOPCODE
6089 Op09M1mod2:
6090 lbl09mod2:      Op09M1
6091                         NEXTOPCODE
6092 Op0AM1mod2:
6093 lbl0Amod2a:     A_ASL8
6094                         NEXTOPCODE
6095 Op0Bmod2:
6096 lbl0Bmod2:      Op0B
6097                         NEXTOPCODE
6098 Op0CM1mod2:
6099 lbl0Cmod2a:     Absolute
6100 lbl0Cmod2b:     TSB8
6101                         NEXTOPCODE
6102 Op0DM1mod2:
6103 lbl0Dmod2a:     Absolute
6104 lbl0Dmod2b:     ORA8
6105                         NEXTOPCODE
6106 Op0EM1mod2:
6107 lbl0Emod2a:     Absolute
6108 lbl0Emod2b:     ASL8
6109                         NEXTOPCODE
6110 Op0FM1mod2:
6111 lbl0Fmod2a:     AbsoluteLong
6112 lbl0Fmod2b:     ORA8
6113                         NEXTOPCODE
6114 Op10mod2:
6115 lbl10mod2:      Op10
6116                         NEXTOPCODE
6117 Op11M1mod2:
6118 lbl11mod2a:     DirectIndirectIndexed0
6119 lbl11mod2b:     ORA8
6120                         NEXTOPCODE
6121 Op12M1mod2:
6122 lbl12mod2a:     DirectIndirect
6123 lbl12mod2b:     ORA8
6124                         NEXTOPCODE
6125 Op13M1mod2:
6126 lbl13mod2a:     StackasmRelativeIndirectIndexed0
6127 lbl13mod2b:     ORA8
6128                         NEXTOPCODE
6129 Op14M1mod2:
6130 lbl14mod2a:     Direct
6131 lbl14mod2b:     TRB8
6132                         NEXTOPCODE
6133 Op15M1mod2:
6134 lbl15mod2a:     DirectIndexedX0
6135 lbl15mod2b:     ORA8
6136                         NEXTOPCODE
6137 Op16M1mod2:
6138 lbl16mod2a:     DirectIndexedX0
6139 lbl16mod2b:     ASL8
6140                         NEXTOPCODE
6141 Op17M1mod2:
6142 lbl17mod2a:     DirectIndirectIndexedLong0
6143 lbl17mod2b:     ORA8
6144                         NEXTOPCODE
6145 Op18mod2:
6146 lbl18mod2:      Op18
6147                         NEXTOPCODE
6148 Op19M1mod2:
6149 lbl19mod2a:     AbsoluteIndexedY0
6150 lbl19mod2b:     ORA8
6151                         NEXTOPCODE
6152 Op1AM1mod2:
6153 lbl1Amod2a:     A_INC8
6154                         NEXTOPCODE
6155 Op1Bmod2:
6156 lbl1Bmod2:      Op1BM1
6157                         NEXTOPCODE
6158 Op1CM1mod2:
6159 lbl1Cmod2a:     Absolute
6160 lbl1Cmod2b:     TRB8
6161                         NEXTOPCODE
6162 Op1DM1mod2:
6163 lbl1Dmod2a:     AbsoluteIndexedX0
6164 lbl1Dmod2b:     ORA8
6165                         NEXTOPCODE
6166 Op1EM1mod2:
6167 lbl1Emod2a:     AbsoluteIndexedX0
6168 lbl1Emod2b:     ASL8
6169                         NEXTOPCODE
6170 Op1FM1mod2:
6171 lbl1Fmod2a:     AbsoluteLongIndexedX0
6172 lbl1Fmod2b:     ORA8
6173                         NEXTOPCODE
6174 Op20mod2:
6175 lbl20mod2:      Op20
6176                         NEXTOPCODE
6177 Op21M1mod2:
6178 lbl21mod2a:     DirectIndexedIndirect0
6179 lbl21mod2b:     AND8
6180                         NEXTOPCODE
6181 Op22mod2:
6182 lbl22mod2:      Op22
6183                         NEXTOPCODE
6184 Op23M1mod2:
6185 lbl23mod2a:     StackasmRelative
6186 lbl23mod2b:     AND8
6187                         NEXTOPCODE
6188 Op24M1mod2:
6189 lbl24mod2a:     Direct
6190 lbl24mod2b:     BIT8
6191                         NEXTOPCODE
6192 Op25M1mod2:
6193 lbl25mod2a:     Direct
6194 lbl25mod2b:     AND8
6195                         NEXTOPCODE
6196 Op26M1mod2:
6197 lbl26mod2a:     Direct
6198 lbl26mod2b:     ROL8
6199                         NEXTOPCODE
6200 Op27M1mod2:
6201 lbl27mod2a:     DirectIndirectLong
6202 lbl27mod2b:     AND8
6203                         NEXTOPCODE
6204 Op28mod2:
6205 lbl28mod2:      Op28X0M1
6206                         NEXTOPCODE
6207 .pool
6208 Op29M1mod2:
6209 lbl29mod2:      Op29M1
6210                         NEXTOPCODE
6211 Op2AM1mod2:
6212 lbl2Amod2a:     A_ROL8
6213                         NEXTOPCODE
6214 Op2Bmod2:
6215 lbl2Bmod2:      Op2B
6216                         NEXTOPCODE
6217 Op2CM1mod2:
6218 lbl2Cmod2a:     Absolute
6219 lbl2Cmod2b:     BIT8
6220                         NEXTOPCODE
6221 Op2DM1mod2:
6222 lbl2Dmod2a:     Absolute
6223 lbl2Dmod2b:     AND8
6224                         NEXTOPCODE
6225 Op2EM1mod2:
6226 lbl2Emod2a:     Absolute
6227 lbl2Emod2b:     ROL8
6228                         NEXTOPCODE
6229 Op2FM1mod2:
6230 lbl2Fmod2a:     AbsoluteLong
6231 lbl2Fmod2b:     AND8
6232                         NEXTOPCODE
6233 Op30mod2:
6234 lbl30mod2:      Op30
6235                         NEXTOPCODE
6236 Op31M1mod2:
6237 lbl31mod2a:     DirectIndirectIndexed0
6238 lbl31mod2b:     AND8
6239                         NEXTOPCODE
6240 Op32M1mod2:
6241 lbl32mod2a:     DirectIndirect
6242 lbl32mod2b:     AND8
6243                         NEXTOPCODE
6244 Op33M1mod2:
6245 lbl33mod2a:     StackasmRelativeIndirectIndexed0
6246 lbl33mod2b:     AND8
6247                         NEXTOPCODE
6248 Op34M1mod2:
6249 lbl34mod2a:     DirectIndexedX0
6250 lbl34mod2b:     BIT8
6251                         NEXTOPCODE
6252 Op35M1mod2:
6253 lbl35mod2a:     DirectIndexedX0
6254 lbl35mod2b:     AND8
6255                         NEXTOPCODE
6256 Op36M1mod2:
6257 lbl36mod2a:     DirectIndexedX0
6258 lbl36mod2b:     ROL8
6259                         NEXTOPCODE
6260 Op37M1mod2:
6261 lbl37mod2a:     DirectIndirectIndexedLong0
6262 lbl37mod2b:     AND8
6263                         NEXTOPCODE
6264 Op38mod2:
6265 lbl38mod2:      Op38
6266                         NEXTOPCODE
6267 Op39M1mod2:
6268 lbl39mod2a:     AbsoluteIndexedY0
6269 lbl39mod2b:     AND8
6270                         NEXTOPCODE
6271 Op3AM1mod2:
6272 lbl3Amod2a:     A_DEC8
6273                         NEXTOPCODE
6274 Op3Bmod2:
6275 lbl3Bmod2:      Op3BM1
6276                         NEXTOPCODE
6277 Op3CM1mod2:
6278 lbl3Cmod2a:     AbsoluteIndexedX0
6279 lbl3Cmod2b:     BIT8
6280                         NEXTOPCODE
6281 Op3DM1mod2:
6282 lbl3Dmod2a:     AbsoluteIndexedX0
6283 lbl3Dmod2b:     AND8
6284                         NEXTOPCODE
6285 Op3EM1mod2:
6286 lbl3Emod2a:     AbsoluteIndexedX0
6287 lbl3Emod2b:     ROL8
6288                         NEXTOPCODE
6289 Op3FM1mod2:
6290 lbl3Fmod2a:     AbsoluteLongIndexedX0
6291 lbl3Fmod2b:     AND8
6292                         NEXTOPCODE
6293 Op40mod2:
6294 lbl40mod2:      Op40X0M1
6295                         NEXTOPCODE
6296 .pool
6297 Op41M1mod2:
6298 lbl41mod2a:     DirectIndexedIndirect0
6299 lbl41mod2b:     EOR8
6300                         NEXTOPCODE
6301 Op42mod2:
6302 lbl42mod2:      Op42
6303                         NEXTOPCODE
6304 Op43M1mod2:
6305 lbl43mod2a:     StackasmRelative
6306 lbl43mod2b:     EOR8
6307                         NEXTOPCODE
6308 Op44X0mod2:
6309 lbl44mod2:      Op44X0M1
6310                         NEXTOPCODE
6311 Op45M1mod2:
6312 lbl45mod2a:     Direct
6313 lbl45mod2b:     EOR8
6314                         NEXTOPCODE
6315 Op46M1mod2:
6316 lbl46mod2a:     Direct
6317 lbl46mod2b:     LSR8
6318                         NEXTOPCODE
6319 Op47M1mod2:
6320 lbl47mod2a:     DirectIndirectLong
6321 lbl47mod2b:     EOR8
6322                         NEXTOPCODE
6323 Op48M1mod2:
6324 lbl48mod2:      Op48M1
6325                         NEXTOPCODE
6326 Op49M1mod2:
6327 lbl49mod2:      Op49M1
6328                         NEXTOPCODE
6329 Op4AM1mod2:
6330 lbl4Amod2a:     A_LSR8
6331                         NEXTOPCODE
6332 Op4Bmod2:
6333 lbl4Bmod2:      Op4B
6334                         NEXTOPCODE
6335 Op4Cmod2:
6336 lbl4Cmod2:      Op4C
6337                         NEXTOPCODE
6338 Op4DM1mod2:
6339 lbl4Dmod2a:     Absolute
6340 lbl4Dmod2b:     EOR8
6341                         NEXTOPCODE
6342 Op4EM1mod2:
6343 lbl4Emod2a:     Absolute
6344 lbl4Emod2b:     LSR8
6345                         NEXTOPCODE
6346 Op4FM1mod2:
6347 lbl4Fmod2a:     AbsoluteLong
6348 lbl4Fmod2b:     EOR8
6349                         NEXTOPCODE
6350 Op50mod2:
6351 lbl50mod2:      Op50
6352                         NEXTOPCODE
6353 Op51M1mod2:
6354 lbl51mod2a:     DirectIndirectIndexed0
6355 lbl51mod2b:     EOR8
6356                         NEXTOPCODE
6357 Op52M1mod2:
6358 lbl52mod2a:     DirectIndirect
6359 lbl52mod2b:     EOR8
6360                         NEXTOPCODE
6361 Op53M1mod2:
6362 lbl53mod2a:     StackasmRelativeIndirectIndexed0
6363 lbl53mod2b:     EOR8
6364                         NEXTOPCODE
6365 Op54X0mod2:
6366 lbl54mod2:      Op54X0M1
6367                         NEXTOPCODE
6368 Op55M1mod2:
6369 lbl55mod2a:     DirectIndexedX0
6370 lbl55mod2b:     EOR8
6371                         NEXTOPCODE
6372 Op56M1mod2:
6373 lbl56mod2a:     DirectIndexedX0
6374 lbl56mod2b:     LSR8
6375                         NEXTOPCODE
6376 Op57M1mod2:
6377 lbl57mod2a:     DirectIndirectIndexedLong0
6378 lbl57mod2b:     EOR8
6379                         NEXTOPCODE
6380 Op58mod2:
6381 lbl58mod2:      Op58
6382                         NEXTOPCODE
6383 Op59M1mod2:
6384 lbl59mod2a:     AbsoluteIndexedY0
6385 lbl59mod2b:     EOR8
6386                         NEXTOPCODE
6387 Op5AX0mod2:
6388 lbl5Amod2:      Op5AX0
6389                         NEXTOPCODE
6390 Op5Bmod2:
6391 lbl5Bmod2:      Op5BM1
6392                         NEXTOPCODE
6393 Op5Cmod2:
6394 lbl5Cmod2:      Op5C
6395                         NEXTOPCODE
6396 Op5DM1mod2:
6397 lbl5Dmod2a:     AbsoluteIndexedX0
6398 lbl5Dmod2b:     EOR8
6399                         NEXTOPCODE
6400 Op5EM1mod2:
6401 lbl5Emod2a:     AbsoluteIndexedX0
6402 lbl5Emod2b:     LSR8
6403                         NEXTOPCODE
6404 Op5FM1mod2:
6405 lbl5Fmod2a:     AbsoluteLongIndexedX0
6406 lbl5Fmod2b:     EOR8
6407                         NEXTOPCODE
6408 Op60mod2:
6409 lbl60mod2:      Op60
6410                         NEXTOPCODE
6411 Op61M1mod2:
6412 lbl61mod2a:     DirectIndexedIndirect0
6413 lbl61mod2b:     ADC8
6414                         NEXTOPCODE
6415 Op62mod2:
6416 lbl62mod2:      Op62
6417                         NEXTOPCODE
6418 Op63M1mod2:
6419 lbl63mod2a:     StackasmRelative
6420 lbl63mod2b:     ADC8
6421                         NEXTOPCODE
6422 Op64M1mod2:
6423 lbl64mod2a:     Direct
6424 lbl64mod2b:     STZ8
6425                         NEXTOPCODE
6426 Op65M1mod2:
6427 lbl65mod2a:     Direct
6428 lbl65mod2b:     ADC8
6429                         NEXTOPCODE
6430 Op66M1mod2:
6431 lbl66mod2a:     Direct
6432 lbl66mod2b:     ROR8
6433                         NEXTOPCODE
6434 Op67M1mod2:
6435 lbl67mod2a:     DirectIndirectLong
6436 lbl67mod2b:     ADC8
6437                         NEXTOPCODE
6438 Op68M1mod2:
6439 lbl68mod2:      Op68M1
6440                         NEXTOPCODE
6441 Op69M1mod2:
6442 lbl69mod2a:     Immediate8
6443 lbl69mod2b:     ADC8
6444                         NEXTOPCODE
6445 Op6AM1mod2:
6446 lbl6Amod2a:     A_ROR8
6447                         NEXTOPCODE
6448 Op6Bmod2:
6449 lbl6Bmod2:      Op6B
6450                         NEXTOPCODE
6451 Op6Cmod2:
6452 lbl6Cmod2:      Op6C
6453                         NEXTOPCODE
6454 Op6DM1mod2:
6455 lbl6Dmod2a:     Absolute
6456 lbl6Dmod2b:     ADC8
6457                         NEXTOPCODE
6458 Op6EM1mod2:
6459 lbl6Emod2a:     Absolute
6460 lbl6Emod2b:     ROR8
6461                         NEXTOPCODE
6462 Op6FM1mod2:
6463 lbl6Fmod2a:     AbsoluteLong
6464 lbl6Fmod2b:     ADC8
6465                         NEXTOPCODE
6466 Op70mod2:
6467 lbl70mod2:      Op70
6468                         NEXTOPCODE
6469 Op71M1mod2:
6470 lbl71mod2a:     DirectIndirectIndexed0
6471 lbl71mod2b:     ADC8
6472                         NEXTOPCODE
6473 Op72M1mod2:
6474 lbl72mod2a:     DirectIndirect
6475 lbl72mod2b:     ADC8
6476                         NEXTOPCODE
6477 Op73M1mod2:
6478 lbl73mod2a:     StackasmRelativeIndirectIndexed0
6479 lbl73mod2b:     ADC8
6480                         NEXTOPCODE
6481 Op74M1mod2:
6482 lbl74mod2a:     DirectIndexedX0
6483 lbl74mod2b:     STZ8
6484                         NEXTOPCODE
6485 Op75M1mod2:
6486 lbl75mod2a:     DirectIndexedX0
6487 lbl75mod2b:     ADC8
6488                         NEXTOPCODE
6489 Op76M1mod2:
6490 lbl76mod2a:     DirectIndexedX0
6491 lbl76mod2b:     ROR8
6492                         NEXTOPCODE
6493 Op77M1mod2:
6494 lbl77mod2a:     DirectIndirectIndexedLong0
6495 lbl77mod2b:     ADC8
6496                         NEXTOPCODE
6497 Op78mod2:
6498 lbl78mod2:      Op78
6499                         NEXTOPCODE
6500 Op79M1mod2:
6501 lbl79mod2a:     AbsoluteIndexedY0
6502 lbl79mod2b:     ADC8
6503                         NEXTOPCODE
6504 Op7AX0mod2:
6505 lbl7Amod2:      Op7AX0
6506                         NEXTOPCODE
6507 Op7Bmod2:
6508 lbl7Bmod2:      Op7BM1
6509                         NEXTOPCODE
6510 Op7Cmod2:
6511 lbl7Cmod2:      AbsoluteIndexedIndirectX0
6512                 Op7C
6513                         NEXTOPCODE
6514 Op7DM1mod2:
6515 lbl7Dmod2a:     AbsoluteIndexedX0
6516 lbl7Dmod2b:     ADC8
6517                         NEXTOPCODE
6518 Op7EM1mod2:
6519 lbl7Emod2a:     AbsoluteIndexedX0
6520 lbl7Emod2b:     ROR8
6521                         NEXTOPCODE
6522 Op7FM1mod2:
6523 lbl7Fmod2a:     AbsoluteLongIndexedX0
6524 lbl7Fmod2b:     ADC8
6525                         NEXTOPCODE
6526
6527
6528 Op80mod2:
6529 lbl80mod2:      Op80
6530                         NEXTOPCODE
6531 Op81M1mod2:
6532 lbl81mod2a:     DirectIndexedIndirect0
6533 lbl81mod2b:     Op81M1
6534                         NEXTOPCODE
6535 Op82mod2:
6536 lbl82mod2:      Op82
6537                         NEXTOPCODE
6538 Op83M1mod2:
6539 lbl83mod2a:     StackasmRelative
6540 lbl83mod2b:     STA8
6541                         NEXTOPCODE
6542 Op84X0mod2:
6543 lbl84mod2a:     Direct
6544 lbl84mod2b:     STY16
6545                         NEXTOPCODE
6546 Op85M1mod2:
6547 lbl85mod2a:     Direct
6548 lbl85mod2b:     STA8
6549                         NEXTOPCODE
6550 Op86X0mod2:
6551 lbl86mod2a:     Direct
6552 lbl86mod2b:     STX16
6553                         NEXTOPCODE
6554 Op87M1mod2:
6555 lbl87mod2a:     DirectIndirectLong
6556 lbl87mod2b:     STA8
6557                         NEXTOPCODE
6558 Op88X0mod2:
6559 lbl88mod2:      Op88X0
6560                         NEXTOPCODE
6561 Op89M1mod2:
6562 lbl89mod2:      Op89M1
6563                         NEXTOPCODE
6564 Op8AM1mod2:
6565 lbl8Amod2:      Op8AM1X0
6566                         NEXTOPCODE
6567 Op8Bmod2:
6568 lbl8Bmod2:      Op8B
6569                         NEXTOPCODE
6570 Op8CX0mod2:
6571 lbl8Cmod2a:     Absolute
6572 lbl8Cmod2b:     STY16
6573                         NEXTOPCODE
6574 Op8DM1mod2:
6575 lbl8Dmod2a:     Absolute
6576 lbl8Dmod2b:     STA8
6577                         NEXTOPCODE
6578 Op8EX0mod2:
6579 lbl8Emod2a:     Absolute
6580 lbl8Emod2b:     STX16
6581                         NEXTOPCODE
6582 Op8FM1mod2:
6583 lbl8Fmod2a:     AbsoluteLong
6584 lbl8Fmod2b:     STA8
6585                         NEXTOPCODE
6586 Op90mod2:
6587 lbl90mod2:      Op90
6588                         NEXTOPCODE
6589 Op91M1mod2:
6590 lbl91mod2a:     DirectIndirectIndexed0
6591 lbl91mod2b:     STA8
6592                         NEXTOPCODE
6593 Op92M1mod2:
6594 lbl92mod2a:     DirectIndirect
6595 lbl92mod2b:     STA8
6596                         NEXTOPCODE
6597 Op93M1mod2:
6598 lbl93mod2a:     StackasmRelativeIndirectIndexed0
6599 lbl93mod2b:     STA8
6600                         NEXTOPCODE
6601 Op94X0mod2:
6602 lbl94mod2a:     DirectIndexedX0
6603 lbl94mod2b:     STY16
6604                         NEXTOPCODE
6605 Op95M1mod2:
6606 lbl95mod2a:     DirectIndexedX0
6607 lbl95mod2b:     STA8
6608                         NEXTOPCODE
6609 Op96X0mod2:
6610 lbl96mod2a:     DirectIndexedY0
6611 lbl96mod2b:     STX16
6612                         NEXTOPCODE
6613 Op97M1mod2:
6614 lbl97mod2a:     DirectIndirectIndexedLong0
6615 lbl97mod2b:     STA8
6616                         NEXTOPCODE
6617 Op98M1mod2:
6618 lbl98mod2:      Op98M1X0
6619                         NEXTOPCODE
6620 Op99M1mod2:
6621 lbl99mod2a:     AbsoluteIndexedY0
6622 lbl99mod2b:     STA8
6623                         NEXTOPCODE
6624 Op9Amod2:
6625 lbl9Amod2:      Op9AX0
6626                         NEXTOPCODE
6627 Op9BX0mod2:
6628 lbl9Bmod2:      Op9BX0
6629                         NEXTOPCODE
6630 Op9CM1mod2:
6631 lbl9Cmod2a:     Absolute
6632 lbl9Cmod2b:     STZ8
6633                         NEXTOPCODE
6634 Op9DM1mod2:
6635 lbl9Dmod2a:     AbsoluteIndexedX0
6636 lbl9Dmod2b:     STA8
6637                         NEXTOPCODE
6638 Op9EM1mod2:
6639 lbl9Emod2:      AbsoluteIndexedX0
6640                 STZ8
6641                         NEXTOPCODE
6642 Op9FM1mod2:
6643 lbl9Fmod2a:     AbsoluteLongIndexedX0
6644 lbl9Fmod2b:     STA8
6645                         NEXTOPCODE
6646 OpA0X0mod2:
6647 lblA0mod2:      OpA0X0
6648                         NEXTOPCODE
6649 OpA1M1mod2:
6650 lblA1mod2a:     DirectIndexedIndirect0
6651 lblA1mod2b:     LDA8
6652                         NEXTOPCODE
6653 OpA2X0mod2:
6654 lblA2mod2:      OpA2X0
6655                         NEXTOPCODE
6656 OpA3M1mod2:
6657 lblA3mod2a:     StackasmRelative
6658 lblA3mod2b:     LDA8
6659                         NEXTOPCODE
6660 OpA4X0mod2:
6661 lblA4mod2a:     Direct
6662 lblA4mod2b:     LDY16
6663                         NEXTOPCODE
6664 OpA5M1mod2:
6665 lblA5mod2a:     Direct
6666 lblA5mod2b:     LDA8
6667                         NEXTOPCODE
6668 OpA6X0mod2:
6669 lblA6mod2a:     Direct
6670 lblA6mod2b:     LDX16
6671                         NEXTOPCODE
6672 OpA7M1mod2:
6673 lblA7mod2a:     DirectIndirectLong
6674 lblA7mod2b:     LDA8
6675                         NEXTOPCODE
6676 OpA8X0mod2:
6677 lblA8mod2:      OpA8X0M1
6678                         NEXTOPCODE
6679 OpA9M1mod2:
6680 lblA9mod2:      OpA9M1
6681                         NEXTOPCODE
6682 OpAAX0mod2:
6683 lblAAmod2:      OpAAX0M1
6684                         NEXTOPCODE
6685 OpABmod2:
6686 lblABmod2:      OpAB
6687                         NEXTOPCODE
6688 OpACX0mod2:
6689 lblACmod2a:     Absolute
6690 lblACmod2b:     LDY16
6691                         NEXTOPCODE
6692 OpADM1mod2:
6693 lblADmod2a:     Absolute
6694 lblADmod2b:     LDA8
6695                         NEXTOPCODE
6696 OpAEX0mod2:
6697 lblAEmod2a:     Absolute
6698 lblAEmod2b:     LDX16
6699                         NEXTOPCODE
6700 OpAFM1mod2:
6701 lblAFmod2a:     AbsoluteLong
6702 lblAFmod2b:     LDA8
6703                         NEXTOPCODE
6704 OpB0mod2:
6705 lblB0mod2:      OpB0
6706                         NEXTOPCODE
6707 OpB1M1mod2:
6708 lblB1mod2a:     DirectIndirectIndexed0
6709 lblB1mod2b:     LDA8
6710                         NEXTOPCODE
6711 OpB2M1mod2:
6712 lblB2mod2a:     DirectIndirect
6713 lblB2mod2b:     LDA8
6714                         NEXTOPCODE
6715 OpB3M1mod2:
6716 lblB3mod2a:     StackasmRelativeIndirectIndexed0
6717 lblB3mod2b:     LDA8
6718                         NEXTOPCODE
6719 OpB4X0mod2:
6720 lblB4mod2a:     DirectIndexedX0
6721 lblB4mod2b:     LDY16
6722                         NEXTOPCODE
6723 OpB5M1mod2:
6724 lblB5mod2a:     DirectIndexedX0
6725 lblB5mod2b:     LDA8
6726                         NEXTOPCODE
6727 OpB6X0mod2:
6728 lblB6mod2a:     DirectIndexedY0
6729 lblB6mod2b:     LDX16
6730                         NEXTOPCODE
6731 OpB7M1mod2:
6732 lblB7mod2a:     DirectIndirectIndexedLong0
6733 lblB7mod2b:     LDA8
6734                         NEXTOPCODE
6735 OpB8mod2:
6736 lblB8mod2:      OpB8
6737                         NEXTOPCODE
6738 OpB9M1mod2:
6739 lblB9mod2a:     AbsoluteIndexedY0
6740 lblB9mod2b:     LDA8
6741                         NEXTOPCODE
6742 OpBAX0mod2:
6743 lblBAmod2:      OpBAX0
6744                         NEXTOPCODE
6745 OpBBX0mod2:
6746 lblBBmod2:      OpBBX0
6747                         NEXTOPCODE
6748 OpBCX0mod2:
6749 lblBCmod2a:     AbsoluteIndexedX0
6750 lblBCmod2b:     LDY16
6751                         NEXTOPCODE
6752 OpBDM1mod2:
6753 lblBDmod2a:     AbsoluteIndexedX0
6754 lblBDmod2b:     LDA8
6755                         NEXTOPCODE
6756 OpBEX0mod2:
6757 lblBEmod2a:     AbsoluteIndexedY0
6758 lblBEmod2b:     LDX16
6759                         NEXTOPCODE
6760 OpBFM1mod2:
6761 lblBFmod2a:     AbsoluteLongIndexedX0
6762 lblBFmod2b:     LDA8
6763                         NEXTOPCODE
6764 OpC0X0mod2:
6765 lblC0mod2:      OpC0X0
6766                         NEXTOPCODE
6767 OpC1M1mod2:
6768 lblC1mod2a:     DirectIndexedIndirect0
6769 lblC1mod2b:     CMP8
6770                         NEXTOPCODE
6771 OpC2mod2:
6772 lblC2mod2:      OpC2
6773                         NEXTOPCODE
6774 .pool
6775 OpC3M1mod2:
6776 lblC3mod2a:     StackasmRelative
6777 lblC3mod2b:     CMP8
6778                         NEXTOPCODE
6779 OpC4X0mod2:
6780 lblC4mod2a:     Direct
6781 lblC4mod2b:     CMY16
6782                         NEXTOPCODE
6783 OpC5M1mod2:
6784 lblC5mod2a:     Direct
6785 lblC5mod2b:     CMP8
6786                         NEXTOPCODE
6787 OpC6M1mod2:
6788 lblC6mod2a:     Direct
6789 lblC6mod2b:     DEC8
6790                         NEXTOPCODE
6791 OpC7M1mod2:
6792 lblC7mod2a:     DirectIndirectLong
6793 lblC7mod2b:     CMP8
6794                         NEXTOPCODE
6795 OpC8X0mod2:
6796 lblC8mod2:      OpC8X0
6797                         NEXTOPCODE
6798 OpC9M1mod2:
6799 lblC9mod2:      OpC9M1
6800                         NEXTOPCODE
6801 OpCAX0mod2:
6802 lblCAmod2:      OpCAX0
6803                         NEXTOPCODE
6804 OpCBmod2:
6805 lblCBmod2:      OpCB
6806                         NEXTOPCODE
6807 OpCCX0mod2:
6808 lblCCmod2a:     Absolute
6809 lblCCmod2b:     CMY16
6810                         NEXTOPCODE
6811 OpCDM1mod2:
6812 lblCDmod2a:     Absolute
6813 lblCDmod2b:     CMP8
6814                         NEXTOPCODE
6815 OpCEM1mod2:
6816 lblCEmod2a:     Absolute
6817 lblCEmod2b:     DEC8
6818                         NEXTOPCODE
6819 OpCFM1mod2:
6820 lblCFmod2a:     AbsoluteLong
6821 lblCFmod2b:     CMP8
6822                         NEXTOPCODE
6823 OpD0mod2:
6824 lblD0mod2:      OpD0
6825                         NEXTOPCODE
6826 OpD1M1mod2:
6827 lblD1mod2a:     DirectIndirectIndexed0
6828 lblD1mod2b:     CMP8
6829                         NEXTOPCODE
6830 OpD2M1mod2:
6831 lblD2mod2a:     DirectIndirect
6832 lblD2mod2b:     CMP8
6833                         NEXTOPCODE
6834 OpD3M1mod2:
6835 lblD3mod2a:     StackasmRelativeIndirectIndexed0
6836 lblD3mod2b:     CMP8
6837                         NEXTOPCODE
6838 OpD4mod2:
6839 lblD4mod2:      OpD4
6840                         NEXTOPCODE
6841 OpD5M1mod2:
6842 lblD5mod2a:     DirectIndexedX0
6843 lblD5mod2b:     CMP8
6844                         NEXTOPCODE
6845 OpD6M1mod2:
6846 lblD6mod2a:     DirectIndexedX0
6847 lblD6mod2b:     DEC8
6848                         NEXTOPCODE
6849 OpD7M1mod2:
6850 lblD7mod2a:     DirectIndirectIndexedLong0
6851 lblD7mod2b:     CMP8
6852                         NEXTOPCODE
6853 OpD8mod2:
6854 lblD8mod2:      OpD8
6855                         NEXTOPCODE
6856 OpD9M1mod2:
6857 lblD9mod2a:     AbsoluteIndexedY0
6858 lblD9mod2b:     CMP8
6859                         NEXTOPCODE
6860 OpDAX0mod2:
6861 lblDAmod2:      OpDAX0
6862                         NEXTOPCODE
6863 OpDBmod2:
6864 lblDBmod2:      OpDB
6865                         NEXTOPCODE
6866 OpDCmod2:
6867 lblDCmod2:      OpDC
6868                         NEXTOPCODE
6869 OpDDM1mod2:
6870 lblDDmod2a:     AbsoluteIndexedX0
6871 lblDDmod2b:     CMP8
6872                         NEXTOPCODE
6873 OpDEM1mod2:
6874 lblDEmod2a:     AbsoluteIndexedX0
6875 lblDEmod2b:     DEC8
6876                         NEXTOPCODE
6877 OpDFM1mod2:
6878 lblDFmod2a:     AbsoluteLongIndexedX0
6879 lblDFmod2b:     CMP8
6880                         NEXTOPCODE
6881 OpE0X0mod2:
6882 lblE0mod2:      OpE0X0
6883                         NEXTOPCODE
6884 OpE1M1mod2:
6885 lblE1mod2a:     DirectIndexedIndirect0
6886 lblE1mod2b:     SBC8
6887                         NEXTOPCODE
6888 OpE2mod2:
6889 lblE2mod2:      OpE2
6890                         NEXTOPCODE
6891 .pool
6892 OpE3M1mod2:
6893 lblE3mod2a:     StackasmRelative
6894 lblE3mod2b:     SBC8
6895                         NEXTOPCODE
6896 OpE4X0mod2:
6897 lblE4mod2a:     Direct
6898 lblE4mod2b:     CMX16
6899                         NEXTOPCODE
6900 OpE5M1mod2:
6901 lblE5mod2a:     Direct
6902 lblE5mod2b:     SBC8
6903                         NEXTOPCODE
6904 OpE6M1mod2:
6905 lblE6mod2a:     Direct
6906 lblE6mod2b:     INC8
6907                         NEXTOPCODE
6908 OpE7M1mod2:
6909 lblE7mod2a:     DirectIndirectLong
6910 lblE7mod2b:     SBC8
6911                         NEXTOPCODE
6912 OpE8X0mod2:
6913 lblE8mod2:      OpE8X0
6914                         NEXTOPCODE
6915 OpE9M1mod2:
6916 lblE9mod2a:     Immediate8
6917 lblE9mod2b:     SBC8
6918                         NEXTOPCODE
6919 OpEAmod2:
6920 lblEAmod2:      OpEA
6921                         NEXTOPCODE
6922 OpEBmod2:
6923 lblEBmod2:      OpEBM1
6924                         NEXTOPCODE
6925 OpECX0mod2:
6926 lblECmod2a:     Absolute
6927 lblECmod2b:     CMX16
6928                         NEXTOPCODE
6929 OpEDM1mod2:
6930 lblEDmod2a:     Absolute
6931 lblEDmod2b:     SBC8
6932                         NEXTOPCODE
6933 OpEEM1mod2:
6934 lblEEmod2a:     Absolute
6935 lblEEmod2b:     INC8
6936                         NEXTOPCODE
6937 OpEFM1mod2:
6938 lblEFmod2a:     AbsoluteLong
6939 lblEFmod2b:     SBC8
6940                         NEXTOPCODE
6941 OpF0mod2:
6942 lblF0mod2:      OpF0
6943                         NEXTOPCODE
6944 OpF1M1mod2:
6945 lblF1mod2a:     DirectIndirectIndexed0
6946 lblF1mod2b:     SBC8
6947                         NEXTOPCODE
6948 OpF2M1mod2:
6949 lblF2mod2a:     DirectIndirect
6950 lblF2mod2b:     SBC8
6951                         NEXTOPCODE
6952 OpF3M1mod2:
6953 lblF3mod2a:     StackasmRelativeIndirectIndexed0
6954 lblF3mod2b:     SBC8
6955                         NEXTOPCODE
6956 OpF4mod2:
6957 lblF4mod2:      OpF4
6958                         NEXTOPCODE
6959 OpF5M1mod2:
6960 lblF5mod2a:     DirectIndexedX0
6961 lblF5mod2b:     SBC8
6962                         NEXTOPCODE
6963 OpF6M1mod2:
6964 lblF6mod2a:     DirectIndexedX0
6965 lblF6mod2b:     INC8
6966                         NEXTOPCODE
6967 OpF7M1mod2:
6968 lblF7mod2a:     DirectIndirectIndexedLong0
6969 lblF7mod2b:     SBC8
6970                         NEXTOPCODE
6971 OpF8mod2:
6972 lblF8mod2:      OpF8
6973                         NEXTOPCODE
6974 OpF9M1mod2:
6975 lblF9mod2a:     AbsoluteIndexedY0
6976 lblF9mod2b:     SBC8
6977                         NEXTOPCODE
6978 OpFAX0mod2:
6979 lblFAmod2:      OpFAX0
6980                         NEXTOPCODE
6981 OpFBmod2:
6982 lblFBmod2:      OpFB
6983                         NEXTOPCODE
6984 OpFCmod2:
6985 lblFCmod2:      OpFCX0
6986                         NEXTOPCODE
6987 OpFDM1mod2:
6988 lblFDmod2a:     AbsoluteIndexedX0
6989 lblFDmod2b:     SBC8
6990                         NEXTOPCODE
6991 OpFEM1mod2:
6992 lblFEmod2a:     AbsoluteIndexedX0
6993 lblFEmod2b:     INC8
6994                         NEXTOPCODE
6995 OpFFM1mod2:
6996 lblFFmod2a:     AbsoluteLongIndexedX0
6997 lblFFmod2b:     SBC8
6998                         NEXTOPCODE
6999
7000 .pool
7001
7002
7003 jumptable3:             .long   Op00mod3
7004                         .long   Op01M0mod3
7005                         .long   Op02mod3
7006                         .long   Op03M0mod3
7007                         .long   Op04M0mod3
7008                         .long   Op05M0mod3
7009                         .long   Op06M0mod3
7010                         .long   Op07M0mod3
7011                         .long   Op08mod3
7012                         .long   Op09M0mod3
7013                         .long   Op0AM0mod3
7014                         .long   Op0Bmod3
7015                         .long   Op0CM0mod3
7016                         .long   Op0DM0mod3
7017                         .long   Op0EM0mod3
7018                         .long   Op0FM0mod3
7019                         .long   Op10mod3
7020                         .long   Op11M0mod3
7021                         .long   Op12M0mod3
7022                         .long   Op13M0mod3
7023                         .long   Op14M0mod3
7024                         .long   Op15M0mod3
7025                         .long   Op16M0mod3
7026                         .long   Op17M0mod3
7027                         .long   Op18mod3
7028                         .long   Op19M0mod3
7029                         .long   Op1AM0mod3
7030                         .long   Op1Bmod3
7031                         .long   Op1CM0mod3
7032                         .long   Op1DM0mod3
7033                         .long   Op1EM0mod3
7034                         .long   Op1FM0mod3
7035                         .long   Op20mod3
7036                         .long   Op21M0mod3
7037                         .long   Op22mod3
7038                         .long   Op23M0mod3
7039                         .long   Op24M0mod3
7040                         .long   Op25M0mod3
7041                         .long   Op26M0mod3
7042                         .long   Op27M0mod3
7043                         .long   Op28mod3
7044                         .long   Op29M0mod3
7045                         .long   Op2AM0mod3
7046                         .long   Op2Bmod3
7047                         .long   Op2CM0mod3
7048                         .long   Op2DM0mod3
7049                         .long   Op2EM0mod3
7050                         .long   Op2FM0mod3
7051                         .long   Op30mod3
7052                         .long   Op31M0mod3
7053                         .long   Op32M0mod3
7054                         .long   Op33M0mod3
7055                         .long   Op34M0mod3
7056                         .long   Op35M0mod3
7057                         .long   Op36M0mod3
7058                         .long   Op37M0mod3
7059                         .long   Op38mod3
7060                         .long   Op39M0mod3
7061                         .long   Op3AM0mod3
7062                         .long   Op3Bmod3
7063                         .long   Op3CM0mod3
7064                         .long   Op3DM0mod3
7065                         .long   Op3EM0mod3
7066                         .long   Op3FM0mod3
7067                         .long   Op40mod3
7068                         .long   Op41M0mod3
7069                         .long   Op42mod3
7070                         .long   Op43M0mod3
7071                         .long   Op44X0mod3
7072                         .long   Op45M0mod3
7073                         .long   Op46M0mod3
7074                         .long   Op47M0mod3
7075                         .long   Op48M0mod3
7076                         .long   Op49M0mod3
7077                         .long   Op4AM0mod3
7078                         .long   Op4Bmod3
7079                         .long   Op4Cmod3
7080                         .long   Op4DM0mod3
7081                         .long   Op4EM0mod3
7082                         .long   Op4FM0mod3
7083                         .long   Op50mod3
7084                         .long   Op51M0mod3
7085                         .long   Op52M0mod3
7086                         .long   Op53M0mod3
7087                         .long   Op54X0mod3
7088                         .long   Op55M0mod3
7089                         .long   Op56M0mod3
7090                         .long   Op57M0mod3
7091                         .long   Op58mod3
7092                         .long   Op59M0mod3
7093                         .long   Op5AX0mod3
7094                         .long   Op5Bmod3
7095                         .long   Op5Cmod3
7096                         .long   Op5DM0mod3
7097                         .long   Op5EM0mod3
7098                         .long   Op5FM0mod3
7099                         .long   Op60mod3
7100                         .long   Op61M0mod3
7101                         .long   Op62mod3
7102                         .long   Op63M0mod3
7103                         .long   Op64M0mod3
7104                         .long   Op65M0mod3
7105                         .long   Op66M0mod3
7106                         .long   Op67M0mod3
7107                         .long   Op68M0mod3
7108                         .long   Op69M0mod3
7109                         .long   Op6AM0mod3
7110                         .long   Op6Bmod3
7111                         .long   Op6Cmod3
7112                         .long   Op6DM0mod3
7113                         .long   Op6EM0mod3
7114                         .long   Op6FM0mod3
7115                         .long   Op70mod3
7116                         .long   Op71M0mod3
7117                         .long   Op72M0mod3
7118                         .long   Op73M0mod3
7119                         .long   Op74M0mod3
7120                         .long   Op75M0mod3
7121                         .long   Op76M0mod3
7122                         .long   Op77M0mod3
7123                         .long   Op78mod3
7124                         .long   Op79M0mod3
7125                         .long   Op7AX0mod3
7126                         .long   Op7Bmod3
7127                         .long   Op7Cmod3
7128                         .long   Op7DM0mod3
7129                         .long   Op7EM0mod3
7130                         .long   Op7FM0mod3
7131                         .long   Op80mod3
7132                         .long   Op81M0mod3
7133                         .long   Op82mod3
7134                         .long   Op83M0mod3
7135                         .long   Op84X0mod3
7136                         .long   Op85M0mod3
7137                         .long   Op86X0mod3
7138                         .long   Op87M0mod3
7139                         .long   Op88X0mod3
7140                         .long   Op89M0mod3
7141                         .long   Op8AM0mod3
7142                         .long   Op8Bmod3
7143                         .long   Op8CX0mod3
7144                         .long   Op8DM0mod3
7145                         .long   Op8EX0mod3
7146                         .long   Op8FM0mod3
7147                         .long   Op90mod3
7148                         .long   Op91M0mod3
7149                         .long   Op92M0mod3
7150                         .long   Op93M0mod3
7151                         .long   Op94X0mod3
7152                         .long   Op95M0mod3
7153                         .long   Op96X0mod3
7154                         .long   Op97M0mod3
7155                         .long   Op98M0mod3
7156                         .long   Op99M0mod3
7157                         .long   Op9Amod3
7158                         .long   Op9BX0mod3
7159                         .long   Op9CM0mod3
7160                         .long   Op9DM0mod3
7161                         .long   Op9EM0mod3
7162                         .long   Op9FM0mod3
7163                         .long   OpA0X0mod3
7164                         .long   OpA1M0mod3
7165                         .long   OpA2X0mod3
7166                         .long   OpA3M0mod3
7167                         .long   OpA4X0mod3
7168                         .long   OpA5M0mod3
7169                         .long   OpA6X0mod3
7170                         .long   OpA7M0mod3
7171                         .long   OpA8X0mod3
7172                         .long   OpA9M0mod3
7173                         .long   OpAAX0mod3
7174                         .long   OpABmod3
7175                         .long   OpACX0mod3
7176                         .long   OpADM0mod3
7177                         .long   OpAEX0mod3
7178                         .long   OpAFM0mod3
7179                         .long   OpB0mod3
7180                         .long   OpB1M0mod3
7181                         .long   OpB2M0mod3
7182                         .long   OpB3M0mod3
7183                         .long   OpB4X0mod3
7184                         .long   OpB5M0mod3
7185                         .long   OpB6X0mod3
7186                         .long   OpB7M0mod3
7187                         .long   OpB8mod3
7188                         .long   OpB9M0mod3
7189                         .long   OpBAX0mod3
7190                         .long   OpBBX0mod3
7191                         .long   OpBCX0mod3
7192                         .long   OpBDM0mod3
7193                         .long   OpBEX0mod3
7194                         .long   OpBFM0mod3
7195                         .long   OpC0X0mod3
7196                         .long   OpC1M0mod3
7197                         .long   OpC2mod3
7198                         .long   OpC3M0mod3
7199                         .long   OpC4X0mod3
7200                         .long   OpC5M0mod3
7201                         .long   OpC6M0mod3
7202                         .long   OpC7M0mod3
7203                         .long   OpC8X0mod3
7204                         .long   OpC9M0mod3
7205                         .long   OpCAX0mod3
7206                         .long   OpCBmod3
7207                         .long   OpCCX0mod3
7208                         .long   OpCDM0mod3
7209                         .long   OpCEM0mod3
7210                         .long   OpCFM0mod3
7211                         .long   OpD0mod3
7212                         .long   OpD1M0mod3
7213                         .long   OpD2M0mod3
7214                         .long   OpD3M0mod3
7215                         .long   OpD4mod3
7216                         .long   OpD5M0mod3
7217                         .long   OpD6M0mod3
7218                         .long   OpD7M0mod3
7219                         .long   OpD8mod3
7220                         .long   OpD9M0mod3
7221                         .long   OpDAX0mod3
7222                         .long   OpDBmod3
7223                         .long   OpDCmod3
7224                         .long   OpDDM0mod3
7225                         .long   OpDEM0mod3
7226                         .long   OpDFM0mod3
7227                         .long   OpE0X0mod3
7228                         .long   OpE1M0mod3
7229                         .long   OpE2mod3
7230                         .long   OpE3M0mod3
7231                         .long   OpE4X0mod3
7232                         .long   OpE5M0mod3
7233                         .long   OpE6M0mod3
7234                         .long   OpE7M0mod3
7235                         .long   OpE8X0mod3
7236                         .long   OpE9M0mod3
7237                         .long   OpEAmod3
7238                         .long   OpEBmod3
7239                         .long   OpECX0mod3
7240                         .long   OpEDM0mod3
7241                         .long   OpEEM0mod3
7242                         .long   OpEFM0mod3
7243                         .long   OpF0mod3
7244                         .long   OpF1M0mod3
7245                         .long   OpF2M0mod3
7246                         .long   OpF3M0mod3
7247                         .long   OpF4mod3
7248                         .long   OpF5M0mod3
7249                         .long   OpF6M0mod3
7250                         .long   OpF7M0mod3
7251                         .long   OpF8mod3
7252                         .long   OpF9M0mod3
7253                         .long   OpFAX0mod3
7254                         .long   OpFBmod3
7255                         .long   OpFCmod3
7256                         .long   OpFDM0mod3
7257                         .long   OpFEM0mod3
7258                         .long   OpFFM0mod3
7259 Op00mod3:
7260 lbl00mod3:      Op00
7261                         NEXTOPCODE
7262 Op01M0mod3:
7263 lbl01mod3a:     DirectIndexedIndirect0
7264 lbl01mod3b:     ORA16
7265                         NEXTOPCODE
7266 Op02mod3:
7267 lbl02mod3:      Op02
7268                         NEXTOPCODE
7269 Op03M0mod3:
7270 lbl03mod3a:     StackasmRelative
7271 lbl03mod3b:     ORA16
7272                         NEXTOPCODE
7273 Op04M0mod3:
7274 lbl04mod3a:     Direct
7275 lbl04mod3b:     TSB16
7276                         NEXTOPCODE
7277 Op05M0mod3:
7278 lbl05mod3a:     Direct
7279 lbl05mod3b:     ORA16
7280                         NEXTOPCODE
7281 Op06M0mod3:
7282 lbl06mod3a:     Direct
7283 lbl06mod3b:     ASL16
7284                         NEXTOPCODE
7285 Op07M0mod3:
7286 lbl07mod3a:     DirectIndirectLong
7287 lbl07mod3b:     ORA16
7288                         NEXTOPCODE
7289 Op08mod3:
7290 lbl08mod3:      Op08
7291                         NEXTOPCODE
7292 Op09M0mod3:
7293 lbl09mod3:      Op09M0
7294                         NEXTOPCODE
7295 Op0AM0mod3:
7296 lbl0Amod3a:     A_ASL16
7297                         NEXTOPCODE
7298 Op0Bmod3:
7299 lbl0Bmod3:      Op0B
7300                         NEXTOPCODE
7301 Op0CM0mod3:
7302 lbl0Cmod3a:     Absolute
7303 lbl0Cmod3b:     TSB16
7304                         NEXTOPCODE
7305 Op0DM0mod3:
7306 lbl0Dmod3a:     Absolute
7307 lbl0Dmod3b:     ORA16
7308                         NEXTOPCODE
7309 Op0EM0mod3:
7310 lbl0Emod3a:     Absolute
7311 lbl0Emod3b:     ASL16
7312                         NEXTOPCODE
7313 Op0FM0mod3:
7314 lbl0Fmod3a:     AbsoluteLong
7315 lbl0Fmod3b:     ORA16
7316                         NEXTOPCODE
7317 Op10mod3:
7318 lbl10mod3:      Op10
7319                         NEXTOPCODE
7320 Op11M0mod3:
7321 lbl11mod3a:     DirectIndirectIndexed0
7322 lbl11mod3b:     ORA16
7323                         NEXTOPCODE
7324 Op12M0mod3:
7325 lbl12mod3a:     DirectIndirect
7326 lbl12mod3b:     ORA16
7327                         NEXTOPCODE
7328 Op13M0mod3:
7329 lbl13mod3a:     StackasmRelativeIndirectIndexed0
7330 lbl13mod3b:     ORA16
7331                         NEXTOPCODE
7332 Op14M0mod3:
7333 lbl14mod3a:     Direct
7334 lbl14mod3b:     TRB16
7335                         NEXTOPCODE
7336 Op15M0mod3:
7337 lbl15mod3a:     DirectIndexedX0
7338 lbl15mod3b:     ORA16
7339                         NEXTOPCODE
7340 Op16M0mod3:
7341 lbl16mod3a:     DirectIndexedX0
7342 lbl16mod3b:     ASL16
7343                         NEXTOPCODE
7344 Op17M0mod3:
7345 lbl17mod3a:     DirectIndirectIndexedLong0
7346 lbl17mod3b:     ORA16
7347                         NEXTOPCODE
7348 Op18mod3:
7349 lbl18mod3:      Op18
7350                         NEXTOPCODE
7351 Op19M0mod3:
7352 lbl19mod3a:     AbsoluteIndexedY0
7353 lbl19mod3b:     ORA16
7354                         NEXTOPCODE
7355 Op1AM0mod3:
7356 lbl1Amod3a:     A_INC16
7357                         NEXTOPCODE
7358 Op1Bmod3:
7359 lbl1Bmod3:      Op1BM0
7360                         NEXTOPCODE
7361 Op1CM0mod3:
7362 lbl1Cmod3a:     Absolute
7363 lbl1Cmod3b:     TRB16
7364                         NEXTOPCODE
7365 Op1DM0mod3:
7366 lbl1Dmod3a:     AbsoluteIndexedX0
7367 lbl1Dmod3b:     ORA16
7368                         NEXTOPCODE
7369 Op1EM0mod3:
7370 lbl1Emod3a:     AbsoluteIndexedX0
7371 lbl1Emod3b:     ASL16
7372                         NEXTOPCODE
7373 Op1FM0mod3:
7374 lbl1Fmod3a:     AbsoluteLongIndexedX0
7375 lbl1Fmod3b:     ORA16
7376                         NEXTOPCODE
7377 Op20mod3:
7378 lbl20mod3:      Op20
7379                         NEXTOPCODE
7380 Op21M0mod3:
7381 lbl21mod3a:     DirectIndexedIndirect0
7382 lbl21mod3b:     AND16
7383                         NEXTOPCODE
7384 Op22mod3:
7385 lbl22mod3:      Op22
7386                         NEXTOPCODE
7387 Op23M0mod3:
7388 lbl23mod3a:     StackasmRelative
7389 lbl23mod3b:     AND16
7390                         NEXTOPCODE
7391 Op24M0mod3:
7392 lbl24mod3a:     Direct
7393 lbl24mod3b:     BIT16
7394                         NEXTOPCODE
7395 Op25M0mod3:
7396 lbl25mod3a:     Direct
7397 lbl25mod3b:     AND16
7398                         NEXTOPCODE
7399 Op26M0mod3:
7400 lbl26mod3a:     Direct
7401 lbl26mod3b:     ROL16
7402                         NEXTOPCODE
7403 Op27M0mod3:
7404 lbl27mod3a:     DirectIndirectLong
7405 lbl27mod3b:     AND16
7406                         NEXTOPCODE
7407 Op28mod3:
7408 lbl28mod3:      Op28X0M0
7409                         NEXTOPCODE
7410 .pool
7411 Op29M0mod3:
7412 lbl29mod3:      Op29M0
7413                         NEXTOPCODE
7414 Op2AM0mod3:
7415 lbl2Amod3a:     A_ROL16
7416                         NEXTOPCODE
7417 Op2Bmod3:
7418 lbl2Bmod3:      Op2B
7419                         NEXTOPCODE
7420 Op2CM0mod3:
7421 lbl2Cmod3a:     Absolute
7422 lbl2Cmod3b:     BIT16
7423                         NEXTOPCODE
7424 Op2DM0mod3:
7425 lbl2Dmod3a:     Absolute
7426 lbl2Dmod3b:     AND16
7427                         NEXTOPCODE
7428 Op2EM0mod3:
7429 lbl2Emod3a:     Absolute
7430 lbl2Emod3b:     ROL16
7431                         NEXTOPCODE
7432 Op2FM0mod3:
7433 lbl2Fmod3a:     AbsoluteLong
7434 lbl2Fmod3b:     AND16
7435                         NEXTOPCODE
7436 Op30mod3:
7437 lbl30mod3:      Op30
7438                         NEXTOPCODE
7439 Op31M0mod3:
7440 lbl31mod3a:     DirectIndirectIndexed0
7441 lbl31mod3b:     AND16
7442                         NEXTOPCODE
7443 Op32M0mod3:
7444 lbl32mod3a:     DirectIndirect
7445 lbl32mod3b:     AND16
7446                         NEXTOPCODE
7447 Op33M0mod3:
7448 lbl33mod3a:     StackasmRelativeIndirectIndexed0
7449 lbl33mod3b:     AND16
7450                         NEXTOPCODE
7451 Op34M0mod3:
7452 lbl34mod3a:     DirectIndexedX0
7453 lbl34mod3b:     BIT16
7454                         NEXTOPCODE
7455 Op35M0mod3:
7456 lbl35mod3a:     DirectIndexedX0
7457 lbl35mod3b:     AND16
7458                         NEXTOPCODE
7459 Op36M0mod3:
7460 lbl36mod3a:     DirectIndexedX0
7461 lbl36mod3b:     ROL16
7462                         NEXTOPCODE
7463 Op37M0mod3:
7464 lbl37mod3a:     DirectIndirectIndexedLong0
7465 lbl37mod3b:     AND16
7466                         NEXTOPCODE
7467 Op38mod3:
7468 lbl38mod3:      Op38
7469                         NEXTOPCODE
7470 Op39M0mod3:
7471 lbl39mod3a:     AbsoluteIndexedY0
7472 lbl39mod3b:     AND16
7473                         NEXTOPCODE
7474 Op3AM0mod3:
7475 lbl3Amod3a:     A_DEC16
7476                         NEXTOPCODE
7477 Op3Bmod3:
7478 lbl3Bmod3:      Op3BM0
7479                         NEXTOPCODE
7480 Op3CM0mod3:
7481 lbl3Cmod3a:     AbsoluteIndexedX0
7482 lbl3Cmod3b:     BIT16
7483                         NEXTOPCODE
7484 Op3DM0mod3:
7485 lbl3Dmod3a:     AbsoluteIndexedX0
7486 lbl3Dmod3b:     AND16
7487                         NEXTOPCODE
7488 Op3EM0mod3:
7489 lbl3Emod3a:     AbsoluteIndexedX0
7490 lbl3Emod3b:     ROL16
7491                         NEXTOPCODE
7492 Op3FM0mod3:
7493 lbl3Fmod3a:     AbsoluteLongIndexedX0
7494 lbl3Fmod3b:     AND16
7495                         NEXTOPCODE
7496 Op40mod3:
7497 lbl40mod3:      Op40X0M0
7498                         NEXTOPCODE
7499 .pool
7500 Op41M0mod3:
7501 lbl41mod3a:     DirectIndexedIndirect0
7502 lbl41mod3b:     EOR16
7503                         NEXTOPCODE
7504 Op42mod3:
7505 lbl42mod3:      Op42
7506                         NEXTOPCODE
7507 Op43M0mod3:
7508 lbl43mod3a:     StackasmRelative
7509 lbl43mod3b:     EOR16
7510                         NEXTOPCODE
7511 Op44X0mod3:
7512 lbl44mod3:      Op44X0M0
7513                         NEXTOPCODE
7514 Op45M0mod3:
7515 lbl45mod3a:     Direct
7516 lbl45mod3b:     EOR16
7517                         NEXTOPCODE
7518 Op46M0mod3:
7519 lbl46mod3a:     Direct
7520 lbl46mod3b:     LSR16
7521                         NEXTOPCODE
7522 Op47M0mod3:
7523 lbl47mod3a:     DirectIndirectLong
7524 lbl47mod3b:     EOR16
7525                         NEXTOPCODE
7526 Op48M0mod3:
7527 lbl48mod3:      Op48M0
7528                         NEXTOPCODE
7529 Op49M0mod3:
7530 lbl49mod3:      Op49M0
7531                         NEXTOPCODE
7532 Op4AM0mod3:
7533 lbl4Amod3a:     A_LSR16
7534                         NEXTOPCODE
7535 Op4Bmod3:
7536 lbl4Bmod3:      Op4B
7537                         NEXTOPCODE
7538 Op4Cmod3:
7539 lbl4Cmod3:      Op4C
7540                         NEXTOPCODE
7541 Op4DM0mod3:
7542 lbl4Dmod3a:     Absolute
7543 lbl4Dmod3b:     EOR16
7544                         NEXTOPCODE
7545 Op4EM0mod3:
7546 lbl4Emod3a:     Absolute
7547 lbl4Emod3b:     LSR16
7548                         NEXTOPCODE
7549 Op4FM0mod3:
7550 lbl4Fmod3a:     AbsoluteLong
7551 lbl4Fmod3b:     EOR16
7552                         NEXTOPCODE
7553 Op50mod3:
7554 lbl50mod3:      Op50
7555                         NEXTOPCODE
7556 Op51M0mod3:
7557 lbl51mod3a:     DirectIndirectIndexed0
7558 lbl51mod3b:     EOR16
7559                         NEXTOPCODE
7560 Op52M0mod3:
7561 lbl52mod3a:     DirectIndirect
7562 lbl52mod3b:     EOR16
7563                         NEXTOPCODE
7564 Op53M0mod3:
7565 lbl53mod3a:     StackasmRelativeIndirectIndexed0
7566 lbl53mod3b:     EOR16
7567                         NEXTOPCODE
7568 Op54X0mod3:
7569 lbl54mod3:      Op54X0M0
7570                         NEXTOPCODE
7571 Op55M0mod3:
7572 lbl55mod3a:     DirectIndexedX0
7573 lbl55mod3b:     EOR16
7574                         NEXTOPCODE
7575 Op56M0mod3:
7576 lbl56mod3a:     DirectIndexedX0
7577 lbl56mod3b:     LSR16
7578                         NEXTOPCODE
7579 Op57M0mod3:
7580 lbl57mod3a:     DirectIndirectIndexedLong0
7581 lbl57mod3b:     EOR16
7582                         NEXTOPCODE
7583 Op58mod3:
7584 lbl58mod3:      Op58
7585                         NEXTOPCODE
7586 Op59M0mod3:
7587 lbl59mod3a:     AbsoluteIndexedY0
7588 lbl59mod3b:     EOR16
7589                         NEXTOPCODE
7590 Op5AX0mod3:
7591 lbl5Amod3:      Op5AX0
7592                         NEXTOPCODE
7593 Op5Bmod3:
7594 lbl5Bmod3:      Op5BM0
7595                         NEXTOPCODE
7596 Op5Cmod3:
7597 lbl5Cmod3:      Op5C
7598                         NEXTOPCODE
7599 Op5DM0mod3:
7600 lbl5Dmod3a:     AbsoluteIndexedX0
7601 lbl5Dmod3b:     EOR16
7602                         NEXTOPCODE
7603 Op5EM0mod3:
7604 lbl5Emod3a:     AbsoluteIndexedX0
7605 lbl5Emod3b:     LSR16
7606                         NEXTOPCODE
7607 Op5FM0mod3:
7608 lbl5Fmod3a:     AbsoluteLongIndexedX0
7609 lbl5Fmod3b:     EOR16
7610                         NEXTOPCODE
7611 Op60mod3:
7612 lbl60mod3:      Op60
7613                         NEXTOPCODE
7614 Op61M0mod3:
7615 lbl61mod3a:     DirectIndexedIndirect0
7616 lbl61mod3b:     ADC16
7617                         NEXTOPCODE
7618 Op62mod3:
7619 lbl62mod3:      Op62
7620                         NEXTOPCODE
7621 Op63M0mod3:
7622 lbl63mod3a:     StackasmRelative
7623 lbl63mod3b:     ADC16
7624                         NEXTOPCODE
7625 .pool
7626 Op64M0mod3:
7627 lbl64mod3a:     Direct
7628 lbl64mod3b:     STZ16
7629                         NEXTOPCODE
7630 Op65M0mod3:
7631 lbl65mod3a:     Direct
7632 lbl65mod3b:     ADC16
7633                         NEXTOPCODE
7634 .pool
7635 Op66M0mod3:
7636 lbl66mod3a:     Direct
7637 lbl66mod3b:     ROR16
7638                         NEXTOPCODE
7639 Op67M0mod3:
7640 lbl67mod3a:     DirectIndirectLong
7641 lbl67mod3b:     ADC16
7642                         NEXTOPCODE
7643 .pool
7644 Op68M0mod3:
7645 lbl68mod3:      Op68M0
7646                         NEXTOPCODE
7647 Op69M0mod3:
7648 lbl69mod3a:     Immediate16
7649 lbl69mod3b:     ADC16
7650                         NEXTOPCODE
7651 .pool
7652 Op6AM0mod3:
7653 lbl6Amod3a:     A_ROR16
7654                         NEXTOPCODE
7655 Op6Bmod3:
7656 lbl6Bmod3:      Op6B
7657                         NEXTOPCODE
7658 Op6Cmod3:
7659 lbl6Cmod3:      Op6C
7660                         NEXTOPCODE
7661 Op6DM0mod3:
7662 lbl6Dmod3a:     Absolute
7663 lbl6Dmod3b:     ADC16
7664                         NEXTOPCODE
7665 Op6EM0mod3:
7666 lbl6Emod3a:     Absolute
7667 lbl6Emod3b:     ROR16
7668                         NEXTOPCODE
7669 Op6FM0mod3:
7670 lbl6Fmod3a:     AbsoluteLong
7671 lbl6Fmod3b:     ADC16
7672                         NEXTOPCODE
7673 Op70mod3:
7674 lbl70mod3:      Op70
7675                         NEXTOPCODE
7676 Op71M0mod3:
7677 lbl71mod3a:     DirectIndirectIndexed0
7678 lbl71mod3b:     ADC16
7679                         NEXTOPCODE
7680 Op72M0mod3:
7681 lbl72mod3a:     DirectIndirect
7682 lbl72mod3b:     ADC16
7683                         NEXTOPCODE
7684 Op73M0mod3:
7685 lbl73mod3a:     StackasmRelativeIndirectIndexed0
7686 lbl73mod3b:     ADC16
7687                         NEXTOPCODE
7688 .pool
7689 Op74M0mod3:
7690 lbl74mod3a:     DirectIndexedX0
7691 lbl74mod3b:     STZ16
7692                         NEXTOPCODE
7693 Op75M0mod3:
7694 lbl75mod3a:     DirectIndexedX0
7695 lbl75mod3b:     ADC16
7696                         NEXTOPCODE
7697 .pool
7698 Op76M0mod3:
7699 lbl76mod3a:     DirectIndexedX0
7700 lbl76mod3b:     ROR16
7701                         NEXTOPCODE
7702 Op77M0mod3:
7703 lbl77mod3a:     DirectIndirectIndexedLong0
7704 lbl77mod3b:     ADC16
7705                         NEXTOPCODE
7706 Op78mod3:
7707 lbl78mod3:      Op78
7708                         NEXTOPCODE
7709 Op79M0mod3:
7710 lbl79mod3a:     AbsoluteIndexedY0
7711 lbl79mod3b:     ADC16
7712                         NEXTOPCODE
7713 Op7AX0mod3:
7714 lbl7Amod3:      Op7AX0
7715                         NEXTOPCODE
7716 Op7Bmod3:
7717 lbl7Bmod3:      Op7BM0
7718                         NEXTOPCODE
7719 Op7Cmod3:
7720 lbl7Cmod3:      AbsoluteIndexedIndirectX0
7721                 Op7C
7722                         NEXTOPCODE
7723 Op7DM0mod3:
7724 lbl7Dmod3a:     AbsoluteIndexedX0
7725 lbl7Dmod3b:     ADC16
7726                         NEXTOPCODE
7727 Op7EM0mod3:
7728 lbl7Emod3a:     AbsoluteIndexedX0
7729 lbl7Emod3b:     ROR16
7730                         NEXTOPCODE
7731 Op7FM0mod3:
7732 lbl7Fmod3a:     AbsoluteLongIndexedX0
7733 lbl7Fmod3b:     ADC16
7734                         NEXTOPCODE
7735 .pool
7736 Op80mod3:
7737 lbl80mod3:      Op80
7738                         NEXTOPCODE
7739 Op81M0mod3:
7740 lbl81mod3a:     DirectIndexedIndirect0
7741 lbl81mod3b:     Op81M0
7742                         NEXTOPCODE
7743 Op82mod3:
7744 lbl82mod3:      Op82
7745                         NEXTOPCODE
7746 Op83M0mod3:
7747 lbl83mod3a:     StackasmRelative
7748 lbl83mod3b:     STA16
7749                         NEXTOPCODE
7750 Op84X0mod3:
7751 lbl84mod3a:     Direct
7752 lbl84mod3b:     STY16
7753                         NEXTOPCODE
7754 Op85M0mod3:
7755 lbl85mod3a:     Direct
7756 lbl85mod3b:     STA16
7757                         NEXTOPCODE
7758 Op86X0mod3:
7759 lbl86mod3a:     Direct
7760 lbl86mod3b:     STX16
7761                         NEXTOPCODE
7762 Op87M0mod3:
7763 lbl87mod3a:     DirectIndirectLong
7764 lbl87mod3b:     STA16
7765                         NEXTOPCODE
7766 Op88X0mod3:
7767 lbl88mod3:      Op88X0
7768                         NEXTOPCODE
7769 Op89M0mod3:
7770 lbl89mod3:      Op89M0
7771                         NEXTOPCODE
7772 Op8AM0mod3:
7773 lbl8Amod3:      Op8AM0X0
7774                         NEXTOPCODE
7775 Op8Bmod3:
7776 lbl8Bmod3:      Op8B
7777                         NEXTOPCODE
7778 Op8CX0mod3:
7779 lbl8Cmod3a:     Absolute
7780 lbl8Cmod3b:     STY16
7781                         NEXTOPCODE
7782 Op8DM0mod3:
7783 lbl8Dmod3a:     Absolute
7784 lbl8Dmod3b:     STA16
7785                         NEXTOPCODE
7786 Op8EX0mod3:
7787 lbl8Emod3a:     Absolute
7788 lbl8Emod3b:     STX16
7789                         NEXTOPCODE
7790 Op8FM0mod3:
7791 lbl8Fmod3a:     AbsoluteLong
7792 lbl8Fmod3b:     STA16
7793                         NEXTOPCODE
7794 Op90mod3:
7795 lbl90mod3:      Op90
7796                         NEXTOPCODE
7797 Op91M0mod3:
7798 lbl91mod3a:     DirectIndirectIndexed0
7799 lbl91mod3b:     STA16
7800                         NEXTOPCODE
7801 Op92M0mod3:
7802 lbl92mod3a:     DirectIndirect
7803 lbl92mod3b:     STA16
7804                         NEXTOPCODE
7805 Op93M0mod3:
7806 lbl93mod3a:     StackasmRelativeIndirectIndexed0
7807 lbl93mod3b:     STA16
7808                         NEXTOPCODE
7809 Op94X0mod3:
7810 lbl94mod3a:     DirectIndexedX0
7811 lbl94mod3b:     STY16
7812                         NEXTOPCODE
7813 Op95M0mod3:
7814 lbl95mod3a:     DirectIndexedX0
7815 lbl95mod3b:     STA16
7816                         NEXTOPCODE
7817 Op96X0mod3:
7818 lbl96mod3a:     DirectIndexedY0
7819 lbl96mod3b:     STX16
7820                         NEXTOPCODE
7821 Op97M0mod3:
7822 lbl97mod3a:     DirectIndirectIndexedLong0
7823 lbl97mod3b:     STA16
7824                         NEXTOPCODE
7825 Op98M0mod3:
7826 lbl98mod3:      Op98M0X0
7827                         NEXTOPCODE
7828 Op99M0mod3:
7829 lbl99mod3a:     AbsoluteIndexedY0
7830 lbl99mod3b:     STA16
7831                         NEXTOPCODE
7832 Op9Amod3:
7833 lbl9Amod3:      Op9AX0
7834                         NEXTOPCODE
7835 Op9BX0mod3:
7836 lbl9Bmod3:      Op9BX0
7837                         NEXTOPCODE
7838 Op9CM0mod3:
7839 lbl9Cmod3a:     Absolute
7840 lbl9Cmod3b:     STZ16
7841                         NEXTOPCODE
7842 Op9DM0mod3:
7843 lbl9Dmod3a:     AbsoluteIndexedX0
7844 lbl9Dmod3b:     STA16
7845                         NEXTOPCODE
7846 Op9EM0mod3:
7847 lbl9Emod3:      AbsoluteIndexedX0
7848                 STZ16
7849                         NEXTOPCODE
7850 Op9FM0mod3:
7851 lbl9Fmod3a:     AbsoluteLongIndexedX0
7852 lbl9Fmod3b:     STA16
7853                         NEXTOPCODE
7854 OpA0X0mod3:
7855 lblA0mod3:      OpA0X0
7856                         NEXTOPCODE
7857 OpA1M0mod3:
7858 lblA1mod3a:     DirectIndexedIndirect0
7859 lblA1mod3b:     LDA16
7860                         NEXTOPCODE
7861 OpA2X0mod3:
7862 lblA2mod3:      OpA2X0
7863                         NEXTOPCODE
7864 OpA3M0mod3:
7865 lblA3mod3a:     StackasmRelative
7866 lblA3mod3b:     LDA16
7867                         NEXTOPCODE
7868 OpA4X0mod3:
7869 lblA4mod3a:     Direct
7870 lblA4mod3b:     LDY16
7871                         NEXTOPCODE
7872 OpA5M0mod3:
7873 lblA5mod3a:     Direct
7874 lblA5mod3b:     LDA16
7875                         NEXTOPCODE
7876 OpA6X0mod3:
7877 lblA6mod3a:     Direct
7878 lblA6mod3b:     LDX16
7879                         NEXTOPCODE
7880 OpA7M0mod3:
7881 lblA7mod3a:     DirectIndirectLong
7882 lblA7mod3b:     LDA16
7883                         NEXTOPCODE
7884 OpA8X0mod3:
7885 lblA8mod3:      OpA8X0M0
7886                         NEXTOPCODE
7887 OpA9M0mod3:
7888 lblA9mod3:      OpA9M0
7889                         NEXTOPCODE
7890 OpAAX0mod3:
7891 lblAAmod3:      OpAAX0M0
7892                         NEXTOPCODE
7893 OpABmod3:
7894 lblABmod3:      OpAB
7895                         NEXTOPCODE
7896 OpACX0mod3:
7897 lblACmod3a:     Absolute
7898 lblACmod3b:     LDY16
7899                         NEXTOPCODE
7900 OpADM0mod3:
7901 lblADmod3a:     Absolute
7902 lblADmod3b:     LDA16
7903                         NEXTOPCODE
7904 OpAEX0mod3:
7905 lblAEmod3a:     Absolute
7906 lblAEmod3b:     LDX16
7907                         NEXTOPCODE
7908 OpAFM0mod3:
7909 lblAFmod3a:     AbsoluteLong
7910 lblAFmod3b:     LDA16
7911                         NEXTOPCODE
7912 OpB0mod3:
7913 lblB0mod3:      OpB0
7914                         NEXTOPCODE
7915 OpB1M0mod3:
7916 lblB1mod3a:     DirectIndirectIndexed0
7917 lblB1mod3b:     LDA16
7918                         NEXTOPCODE
7919 OpB2M0mod3:
7920 lblB2mod3a:     DirectIndirect
7921 lblB2mod3b:     LDA16
7922                         NEXTOPCODE
7923 OpB3M0mod3:
7924 lblB3mod3a:     StackasmRelativeIndirectIndexed0
7925 lblB3mod3b:     LDA16
7926                         NEXTOPCODE
7927 OpB4X0mod3:
7928 lblB4mod3a:     DirectIndexedX0
7929 lblB4mod3b:     LDY16
7930                         NEXTOPCODE
7931 OpB5M0mod3:
7932 lblB5mod3a:     DirectIndexedX0
7933 lblB5mod3b:     LDA16
7934                         NEXTOPCODE
7935 OpB6X0mod3:
7936 lblB6mod3a:     DirectIndexedY0
7937 lblB6mod3b:     LDX16
7938                         NEXTOPCODE
7939 OpB7M0mod3:
7940 lblB7mod3a:     DirectIndirectIndexedLong0
7941 lblB7mod3b:     LDA16
7942                         NEXTOPCODE
7943 OpB8mod3:
7944 lblB8mod3:      OpB8
7945                         NEXTOPCODE
7946 OpB9M0mod3:
7947 lblB9mod3a:     AbsoluteIndexedY0
7948 lblB9mod3b:     LDA16
7949                         NEXTOPCODE
7950 OpBAX0mod3:
7951 lblBAmod3:      OpBAX0
7952                         NEXTOPCODE
7953 OpBBX0mod3:
7954 lblBBmod3:      OpBBX0
7955                         NEXTOPCODE
7956 OpBCX0mod3:
7957 lblBCmod3a:     AbsoluteIndexedX0
7958 lblBCmod3b:     LDY16
7959                         NEXTOPCODE
7960 OpBDM0mod3:
7961 lblBDmod3a:     AbsoluteIndexedX0
7962 lblBDmod3b:     LDA16
7963                         NEXTOPCODE
7964 OpBEX0mod3:
7965 lblBEmod3a:     AbsoluteIndexedY0
7966 lblBEmod3b:     LDX16
7967                         NEXTOPCODE
7968 OpBFM0mod3:
7969 lblBFmod3a:     AbsoluteLongIndexedX0
7970 lblBFmod3b:     LDA16
7971                         NEXTOPCODE
7972 OpC0X0mod3:
7973 lblC0mod3:      OpC0X0
7974                         NEXTOPCODE
7975 OpC1M0mod3:
7976 lblC1mod3a:     DirectIndexedIndirect0
7977 lblC1mod3b:     CMP16
7978                         NEXTOPCODE
7979 OpC2mod3:
7980 lblC2mod3:      OpC2
7981                         NEXTOPCODE
7982 .pool
7983 OpC3M0mod3:
7984 lblC3mod3a:     StackasmRelative
7985 lblC3mod3b:     CMP16
7986                         NEXTOPCODE
7987 OpC4X0mod3:
7988 lblC4mod3a:     Direct
7989 lblC4mod3b:     CMY16
7990                         NEXTOPCODE
7991 OpC5M0mod3:
7992 lblC5mod3a:     Direct
7993 lblC5mod3b:     CMP16
7994                         NEXTOPCODE
7995 OpC6M0mod3:
7996 lblC6mod3a:     Direct
7997 lblC6mod3b:     DEC16
7998                         NEXTOPCODE
7999 OpC7M0mod3:
8000 lblC7mod3a:     DirectIndirectLong
8001 lblC7mod3b:     CMP16
8002                         NEXTOPCODE
8003 OpC8X0mod3:
8004 lblC8mod3:      OpC8X0
8005                         NEXTOPCODE
8006 OpC9M0mod3:
8007 lblC9mod3:      OpC9M0
8008                         NEXTOPCODE
8009 OpCAX0mod3:
8010 lblCAmod3:      OpCAX0
8011                         NEXTOPCODE
8012 OpCBmod3:
8013 lblCBmod3:      OpCB
8014                         NEXTOPCODE
8015 OpCCX0mod3:
8016 lblCCmod3a:     Absolute
8017 lblCCmod3b:     CMY16
8018                         NEXTOPCODE
8019 OpCDM0mod3:
8020 lblCDmod3a:     Absolute
8021 lblCDmod3b:     CMP16
8022                         NEXTOPCODE
8023 OpCEM0mod3:
8024 lblCEmod3a:     Absolute
8025 lblCEmod3b:     DEC16
8026                         NEXTOPCODE
8027 OpCFM0mod3:
8028 lblCFmod3a:     AbsoluteLong
8029 lblCFmod3b:     CMP16
8030                         NEXTOPCODE
8031 OpD0mod3:
8032 lblD0mod3:      OpD0
8033                         NEXTOPCODE
8034 OpD1M0mod3:
8035 lblD1mod3a:     DirectIndirectIndexed0
8036 lblD1mod3b:     CMP16
8037                         NEXTOPCODE
8038 OpD2M0mod3:
8039 lblD2mod3a:     DirectIndirect
8040 lblD2mod3b:     CMP16
8041                         NEXTOPCODE
8042 OpD3M0mod3:
8043 lblD3mod3a:     StackasmRelativeIndirectIndexed0
8044 lblD3mod3b:     CMP16
8045                         NEXTOPCODE
8046 OpD4mod3:
8047 lblD4mod3:      OpD4
8048                         NEXTOPCODE
8049 OpD5M0mod3:
8050 lblD5mod3a:     DirectIndexedX0
8051 lblD5mod3b:     CMP16
8052                         NEXTOPCODE
8053 OpD6M0mod3:
8054 lblD6mod3a:     DirectIndexedX0
8055 lblD6mod3b:     DEC16
8056                         NEXTOPCODE
8057 OpD7M0mod3:
8058 lblD7mod3a:     DirectIndirectIndexedLong0
8059 lblD7mod3b:     CMP16
8060                         NEXTOPCODE
8061 OpD8mod3:
8062 lblD8mod3:      OpD8
8063                         NEXTOPCODE
8064 OpD9M0mod3:
8065 lblD9mod3a:     AbsoluteIndexedY0
8066 lblD9mod3b:     CMP16
8067                         NEXTOPCODE
8068 OpDAX0mod3:
8069 lblDAmod3:      OpDAX0
8070                         NEXTOPCODE
8071 OpDBmod3:
8072 lblDBmod3:      OpDB
8073                         NEXTOPCODE
8074 OpDCmod3:
8075 lblDCmod3:      OpDC
8076                         NEXTOPCODE
8077 OpDDM0mod3:
8078 lblDDmod3a:     AbsoluteIndexedX0
8079 lblDDmod3b:     CMP16
8080                         NEXTOPCODE
8081 OpDEM0mod3:
8082 lblDEmod3a:     AbsoluteIndexedX0
8083 lblDEmod3b:     DEC16
8084                         NEXTOPCODE
8085 OpDFM0mod3:
8086 lblDFmod3a:     AbsoluteLongIndexedX0
8087 lblDFmod3b:     CMP16
8088                         NEXTOPCODE
8089 OpE0X0mod3:
8090 lblE0mod3:      OpE0X0
8091                         NEXTOPCODE
8092 OpE1M0mod3:
8093 lblE1mod3a:     DirectIndexedIndirect0
8094 lblE1mod3b:     SBC16
8095                         NEXTOPCODE
8096 OpE2mod3:
8097 lblE2mod3:      OpE2
8098                         NEXTOPCODE
8099 .pool
8100 OpE3M0mod3:
8101 lblE3mod3a:     StackasmRelative
8102 lblE3mod3b:     SBC16
8103                         NEXTOPCODE
8104 OpE4X0mod3:
8105 lblE4mod3a:     Direct
8106 lblE4mod3b:     CMX16
8107                         NEXTOPCODE
8108 OpE5M0mod3:
8109 lblE5mod3a:     Direct
8110 lblE5mod3b:     SBC16
8111                         NEXTOPCODE
8112 OpE6M0mod3:
8113 lblE6mod3a:     Direct
8114 lblE6mod3b:     INC16
8115                         NEXTOPCODE
8116 OpE7M0mod3:
8117 lblE7mod3a:     DirectIndirectLong
8118 lblE7mod3b:     SBC16
8119                         NEXTOPCODE
8120 OpE8X0mod3:
8121 lblE8mod3:      OpE8X0
8122                         NEXTOPCODE
8123 OpE9M0mod3:
8124 lblE9mod3a:     Immediate16
8125 lblE9mod3b:     SBC16
8126                         NEXTOPCODE
8127 OpEAmod3:
8128 lblEAmod3:      OpEA
8129                         NEXTOPCODE
8130 OpEBmod3:
8131 lblEBmod3:      OpEBM0
8132                         NEXTOPCODE
8133 OpECX0mod3:
8134 lblECmod3a:     Absolute
8135 lblECmod3b:     CMX16
8136                         NEXTOPCODE
8137 OpEDM0mod3:
8138 lblEDmod3a:     Absolute
8139 lblEDmod3b:     SBC16
8140                         NEXTOPCODE
8141 OpEEM0mod3:
8142 lblEEmod3a:     Absolute
8143 lblEEmod3b:     INC16
8144                         NEXTOPCODE
8145 OpEFM0mod3:
8146 lblEFmod3a:     AbsoluteLong
8147 lblEFmod3b:     SBC16
8148                         NEXTOPCODE
8149 OpF0mod3:
8150 lblF0mod3:      OpF0
8151                         NEXTOPCODE
8152 OpF1M0mod3:
8153 lblF1mod3a:     DirectIndirectIndexed0
8154 lblF1mod3b:     SBC16
8155                         NEXTOPCODE
8156 OpF2M0mod3:
8157 lblF2mod3a:     DirectIndirect
8158 lblF2mod3b:     SBC16
8159                         NEXTOPCODE
8160 OpF3M0mod3:
8161 lblF3mod3a:     StackasmRelativeIndirectIndexed0
8162 lblF3mod3b:     SBC16
8163                         NEXTOPCODE
8164 OpF4mod3:
8165 lblF4mod3:      OpF4
8166                         NEXTOPCODE
8167 OpF5M0mod3:
8168 lblF5mod3a:     DirectIndexedX0
8169 lblF5mod3b:     SBC16
8170                         NEXTOPCODE
8171 OpF6M0mod3:
8172 lblF6mod3a:     DirectIndexedX0
8173 lblF6mod3b:     INC16
8174                         NEXTOPCODE
8175 OpF7M0mod3:
8176 lblF7mod3a:     DirectIndirectIndexedLong0
8177 lblF7mod3b:     SBC16
8178                         NEXTOPCODE
8179 OpF8mod3:
8180 lblF8mod3:      OpF8
8181                         NEXTOPCODE
8182 OpF9M0mod3:
8183 lblF9mod3a:     AbsoluteIndexedY0
8184 lblF9mod3b:     SBC16
8185                         NEXTOPCODE
8186 OpFAX0mod3:
8187 lblFAmod3:      OpFAX0
8188                         NEXTOPCODE
8189 OpFBmod3:
8190 lblFBmod3:      OpFB
8191                         NEXTOPCODE
8192 OpFCmod3:
8193 lblFCmod3:      OpFCX0
8194                         NEXTOPCODE
8195 OpFDM0mod3:
8196 lblFDmod3a:     AbsoluteIndexedX0
8197 lblFDmod3b:     SBC16
8198                         NEXTOPCODE
8199 OpFEM0mod3:
8200 lblFEmod3a:     AbsoluteIndexedX0
8201 lblFEmod3b:     INC16
8202                         NEXTOPCODE
8203 OpFFM0mod3:
8204 lblFFmod3a:     AbsoluteLongIndexedX0
8205 lblFFmod3b:     SBC16
8206                         NEXTOPCODE
8207 .pool
8208
8209 jumptable4:             .long   Op00mod4
8210                         .long   Op01M0mod4
8211                         .long   Op02mod4
8212                         .long   Op03M0mod4
8213                         .long   Op04M0mod4
8214                         .long   Op05M0mod4
8215                         .long   Op06M0mod4
8216                         .long   Op07M0mod4
8217                         .long   Op08mod4
8218                         .long   Op09M0mod4
8219                         .long   Op0AM0mod4
8220                         .long   Op0Bmod4
8221                         .long   Op0CM0mod4
8222                         .long   Op0DM0mod4
8223                         .long   Op0EM0mod4
8224                         .long   Op0FM0mod4
8225                         .long   Op10mod4
8226                         .long   Op11M0mod4
8227                         .long   Op12M0mod4
8228                         .long   Op13M0mod4
8229                         .long   Op14M0mod4
8230                         .long   Op15M0mod4
8231                         .long   Op16M0mod4
8232                         .long   Op17M0mod4
8233                         .long   Op18mod4
8234                         .long   Op19M0mod4
8235                         .long   Op1AM0mod4
8236                         .long   Op1Bmod4
8237                         .long   Op1CM0mod4
8238                         .long   Op1DM0mod4
8239                         .long   Op1EM0mod4
8240                         .long   Op1FM0mod4
8241                         .long   Op20mod4
8242                         .long   Op21M0mod4
8243                         .long   Op22mod4
8244                         .long   Op23M0mod4
8245                         .long   Op24M0mod4
8246                         .long   Op25M0mod4
8247                         .long   Op26M0mod4
8248                         .long   Op27M0mod4
8249                         .long   Op28mod4
8250                         .long   Op29M0mod4
8251                         .long   Op2AM0mod4
8252                         .long   Op2Bmod4
8253                         .long   Op2CM0mod4
8254                         .long   Op2DM0mod4
8255                         .long   Op2EM0mod4
8256                         .long   Op2FM0mod4
8257                         .long   Op30mod4
8258                         .long   Op31M0mod4
8259                         .long   Op32M0mod4
8260                         .long   Op33M0mod4
8261                         .long   Op34M0mod4
8262                         .long   Op35M0mod4
8263                         .long   Op36M0mod4
8264                         .long   Op37M0mod4
8265                         .long   Op38mod4
8266                         .long   Op39M0mod4
8267                         .long   Op3AM0mod4
8268                         .long   Op3Bmod4
8269                         .long   Op3CM0mod4
8270                         .long   Op3DM0mod4
8271                         .long   Op3EM0mod4
8272                         .long   Op3FM0mod4
8273                         .long   Op40mod4
8274                         .long   Op41M0mod4
8275                         .long   Op42mod4
8276                         .long   Op43M0mod4
8277                         .long   Op44X1mod4
8278                         .long   Op45M0mod4
8279                         .long   Op46M0mod4
8280                         .long   Op47M0mod4
8281                         .long   Op48M0mod4
8282                         .long   Op49M0mod4
8283                         .long   Op4AM0mod4
8284                         .long   Op4Bmod4
8285                         .long   Op4Cmod4
8286                         .long   Op4DM0mod4
8287                         .long   Op4EM0mod4
8288                         .long   Op4FM0mod4
8289                         .long   Op50mod4
8290                         .long   Op51M0mod4
8291                         .long   Op52M0mod4
8292                         .long   Op53M0mod4
8293                         .long   Op54X1mod4
8294                         .long   Op55M0mod4
8295                         .long   Op56M0mod4
8296                         .long   Op57M0mod4
8297                         .long   Op58mod4
8298                         .long   Op59M0mod4
8299                         .long   Op5AX1mod4
8300                         .long   Op5Bmod4
8301                         .long   Op5Cmod4
8302                         .long   Op5DM0mod4
8303                         .long   Op5EM0mod4
8304                         .long   Op5FM0mod4
8305                         .long   Op60mod4
8306                         .long   Op61M0mod4
8307                         .long   Op62mod4
8308                         .long   Op63M0mod4
8309                         .long   Op64M0mod4
8310                         .long   Op65M0mod4
8311                         .long   Op66M0mod4
8312                         .long   Op67M0mod4
8313                         .long   Op68M0mod4
8314                         .long   Op69M0mod4
8315                         .long   Op6AM0mod4
8316                         .long   Op6Bmod4
8317                         .long   Op6Cmod4
8318                         .long   Op6DM0mod4
8319                         .long   Op6EM0mod4
8320                         .long   Op6FM0mod4
8321                         .long   Op70mod4
8322                         .long   Op71M0mod4
8323                         .long   Op72M0mod4
8324                         .long   Op73M0mod4
8325                         .long   Op74M0mod4
8326                         .long   Op75M0mod4
8327                         .long   Op76M0mod4
8328                         .long   Op77M0mod4
8329                         .long   Op78mod4
8330                         .long   Op79M0mod4
8331                         .long   Op7AX1mod4
8332                         .long   Op7Bmod4
8333                         .long   Op7Cmod4
8334                         .long   Op7DM0mod4
8335                         .long   Op7EM0mod4
8336                         .long   Op7FM0mod4
8337                         .long   Op80mod4
8338                         .long   Op81M0mod4
8339                         .long   Op82mod4
8340                         .long   Op83M0mod4
8341                         .long   Op84X1mod4
8342                         .long   Op85M0mod4
8343                         .long   Op86X1mod4
8344                         .long   Op87M0mod4
8345                         .long   Op88X1mod4
8346                         .long   Op89M0mod4
8347                         .long   Op8AM0mod4
8348                         .long   Op8Bmod4
8349                         .long   Op8CX1mod4
8350                         .long   Op8DM0mod4
8351                         .long   Op8EX1mod4
8352                         .long   Op8FM0mod4
8353                         .long   Op90mod4
8354                         .long   Op91M0mod4
8355                         .long   Op92M0mod4
8356                         .long   Op93M0mod4
8357                         .long   Op94X1mod4
8358                         .long   Op95M0mod4
8359                         .long   Op96X1mod4
8360                         .long   Op97M0mod4
8361                         .long   Op98M0mod4
8362                         .long   Op99M0mod4
8363                         .long   Op9Amod4
8364                         .long   Op9BX1mod4
8365                         .long   Op9CM0mod4
8366                         .long   Op9DM0mod4
8367                         .long   Op9EM0mod4
8368                         .long   Op9FM0mod4
8369                         .long   OpA0X1mod4
8370                         .long   OpA1M0mod4
8371                         .long   OpA2X1mod4
8372                         .long   OpA3M0mod4
8373                         .long   OpA4X1mod4
8374                         .long   OpA5M0mod4
8375                         .long   OpA6X1mod4
8376                         .long   OpA7M0mod4
8377                         .long   OpA8X1mod4
8378                         .long   OpA9M0mod4
8379                         .long   OpAAX1mod4
8380                         .long   OpABmod4
8381                         .long   OpACX1mod4
8382                         .long   OpADM0mod4
8383                         .long   OpAEX1mod4
8384                         .long   OpAFM0mod4
8385                         .long   OpB0mod4
8386                         .long   OpB1M0mod4
8387                         .long   OpB2M0mod4
8388                         .long   OpB3M0mod4
8389                         .long   OpB4X1mod4
8390                         .long   OpB5M0mod4
8391                         .long   OpB6X1mod4
8392                         .long   OpB7M0mod4
8393                         .long   OpB8mod4
8394                         .long   OpB9M0mod4
8395                         .long   OpBAX1mod4
8396                         .long   OpBBX1mod4
8397                         .long   OpBCX1mod4
8398                         .long   OpBDM0mod4
8399                         .long   OpBEX1mod4
8400                         .long   OpBFM0mod4
8401                         .long   OpC0X1mod4
8402                         .long   OpC1M0mod4
8403                         .long   OpC2mod4
8404                         .long   OpC3M0mod4
8405                         .long   OpC4X1mod4
8406                         .long   OpC5M0mod4
8407                         .long   OpC6M0mod4
8408                         .long   OpC7M0mod4
8409                         .long   OpC8X1mod4
8410                         .long   OpC9M0mod4
8411                         .long   OpCAX1mod4
8412                         .long   OpCBmod4
8413                         .long   OpCCX1mod4
8414                         .long   OpCDM0mod4
8415                         .long   OpCEM0mod4
8416                         .long   OpCFM0mod4
8417                         .long   OpD0mod4
8418                         .long   OpD1M0mod4
8419                         .long   OpD2M0mod4
8420                         .long   OpD3M0mod4
8421                         .long   OpD4mod4
8422                         .long   OpD5M0mod4
8423                         .long   OpD6M0mod4
8424                         .long   OpD7M0mod4
8425                         .long   OpD8mod4
8426                         .long   OpD9M0mod4
8427                         .long   OpDAX1mod4
8428                         .long   OpDBmod4
8429                         .long   OpDCmod4
8430                         .long   OpDDM0mod4
8431                         .long   OpDEM0mod4
8432                         .long   OpDFM0mod4
8433                         .long   OpE0X1mod4
8434                         .long   OpE1M0mod4
8435                         .long   OpE2mod4
8436                         .long   OpE3M0mod4
8437                         .long   OpE4X1mod4
8438                         .long   OpE5M0mod4
8439                         .long   OpE6M0mod4
8440                         .long   OpE7M0mod4
8441                         .long   OpE8X1mod4
8442                         .long   OpE9M0mod4
8443                         .long   OpEAmod4
8444                         .long   OpEBmod4
8445                         .long   OpECX1mod4
8446                         .long   OpEDM0mod4
8447                         .long   OpEEM0mod4
8448                         .long   OpEFM0mod4
8449                         .long   OpF0mod4
8450                         .long   OpF1M0mod4
8451                         .long   OpF2M0mod4
8452                         .long   OpF3M0mod4
8453                         .long   OpF4mod4
8454                         .long   OpF5M0mod4
8455                         .long   OpF6M0mod4
8456                         .long   OpF7M0mod4
8457                         .long   OpF8mod4
8458                         .long   OpF9M0mod4
8459                         .long   OpFAX1mod4
8460                         .long   OpFBmod4
8461                         .long   OpFCmod4
8462                         .long   OpFDM0mod4
8463                         .long   OpFEM0mod4
8464                         .long   OpFFM0mod4
8465 Op00mod4:
8466 lbl00mod4:      Op00
8467                         NEXTOPCODE
8468 Op01M0mod4:
8469 lbl01mod4a:     DirectIndexedIndirect1
8470 lbl01mod4b:     ORA16
8471                         NEXTOPCODE
8472 Op02mod4:
8473 lbl02mod4:      Op02
8474                         NEXTOPCODE
8475 Op03M0mod4:
8476 lbl03mod4a:     StackasmRelative
8477 lbl03mod4b:     ORA16
8478                         NEXTOPCODE
8479 Op04M0mod4:
8480 lbl04mod4a:     Direct
8481 lbl04mod4b:     TSB16
8482                         NEXTOPCODE
8483 Op05M0mod4:
8484 lbl05mod4a:     Direct
8485 lbl05mod4b:     ORA16
8486                         NEXTOPCODE
8487 Op06M0mod4:
8488 lbl06mod4a:     Direct
8489 lbl06mod4b:     ASL16
8490                         NEXTOPCODE
8491 Op07M0mod4:
8492 lbl07mod4a:     DirectIndirectLong
8493 lbl07mod4b:     ORA16
8494                         NEXTOPCODE
8495 Op08mod4:
8496 lbl08mod4:      Op08
8497                         NEXTOPCODE
8498 Op09M0mod4:
8499 lbl09mod4:      Op09M0
8500                         NEXTOPCODE
8501 Op0AM0mod4:
8502 lbl0Amod4a:     A_ASL16
8503                         NEXTOPCODE
8504 Op0Bmod4:
8505 lbl0Bmod4:      Op0B
8506                         NEXTOPCODE
8507 Op0CM0mod4:
8508 lbl0Cmod4a:     Absolute
8509 lbl0Cmod4b:     TSB16
8510                         NEXTOPCODE
8511 Op0DM0mod4:
8512 lbl0Dmod4a:     Absolute
8513 lbl0Dmod4b:     ORA16
8514                         NEXTOPCODE
8515 Op0EM0mod4:
8516 lbl0Emod4a:     Absolute
8517 lbl0Emod4b:     ASL16
8518                         NEXTOPCODE
8519 Op0FM0mod4:
8520 lbl0Fmod4a:     AbsoluteLong
8521 lbl0Fmod4b:     ORA16
8522                         NEXTOPCODE
8523 Op10mod4:
8524 lbl10mod4:      Op10
8525                         NEXTOPCODE
8526 Op11M0mod4:
8527 lbl11mod4a:     DirectIndirectIndexed1
8528 lbl11mod4b:     ORA16
8529                         NEXTOPCODE
8530 Op12M0mod4:
8531 lbl12mod4a:     DirectIndirect
8532 lbl12mod4b:     ORA16
8533                         NEXTOPCODE
8534 Op13M0mod4:
8535 lbl13mod4a:     StackasmRelativeIndirectIndexed1
8536 lbl13mod4b:     ORA16
8537                         NEXTOPCODE
8538 Op14M0mod4:
8539 lbl14mod4a:     Direct
8540 lbl14mod4b:     TRB16
8541                         NEXTOPCODE
8542 Op15M0mod4:
8543 lbl15mod4a:     DirectIndexedX1
8544 lbl15mod4b:     ORA16
8545                         NEXTOPCODE
8546 Op16M0mod4:
8547 lbl16mod4a:     DirectIndexedX1
8548 lbl16mod4b:     ASL16
8549                         NEXTOPCODE
8550 Op17M0mod4:
8551 lbl17mod4a:     DirectIndirectIndexedLong1
8552 lbl17mod4b:     ORA16
8553                         NEXTOPCODE
8554 Op18mod4:
8555 lbl18mod4:      Op18
8556                         NEXTOPCODE
8557 Op19M0mod4:
8558 lbl19mod4a:     AbsoluteIndexedY1
8559 lbl19mod4b:     ORA16
8560                         NEXTOPCODE
8561 Op1AM0mod4:
8562 lbl1Amod4a:     A_INC16
8563                         NEXTOPCODE
8564 Op1Bmod4:
8565 lbl1Bmod4:      Op1BM0
8566                         NEXTOPCODE
8567 Op1CM0mod4:
8568 lbl1Cmod4a:     Absolute
8569 lbl1Cmod4b:     TRB16
8570                         NEXTOPCODE
8571 Op1DM0mod4:
8572 lbl1Dmod4a:     AbsoluteIndexedX1
8573 lbl1Dmod4b:     ORA16
8574                         NEXTOPCODE
8575 Op1EM0mod4:
8576 lbl1Emod4a:     AbsoluteIndexedX1
8577 lbl1Emod4b:     ASL16
8578                         NEXTOPCODE
8579 Op1FM0mod4:
8580 lbl1Fmod4a:     AbsoluteLongIndexedX1
8581 lbl1Fmod4b:     ORA16
8582                         NEXTOPCODE
8583 Op20mod4:
8584 lbl20mod4:      Op20
8585                         NEXTOPCODE
8586 Op21M0mod4:
8587 lbl21mod4a:     DirectIndexedIndirect1
8588 lbl21mod4b:     AND16
8589                         NEXTOPCODE
8590 Op22mod4:
8591 lbl22mod4:      Op22
8592                         NEXTOPCODE
8593 Op23M0mod4:
8594 lbl23mod4a:     StackasmRelative
8595 lbl23mod4b:     AND16
8596                         NEXTOPCODE
8597 Op24M0mod4:
8598 lbl24mod4a:     Direct
8599 lbl24mod4b:     BIT16
8600                         NEXTOPCODE
8601 Op25M0mod4:
8602 lbl25mod4a:     Direct
8603 lbl25mod4b:     AND16
8604                         NEXTOPCODE
8605 Op26M0mod4:
8606 lbl26mod4a:     Direct
8607 lbl26mod4b:     ROL16
8608                         NEXTOPCODE
8609 Op27M0mod4:
8610 lbl27mod4a:     DirectIndirectLong
8611 lbl27mod4b:     AND16
8612                         NEXTOPCODE
8613 Op28mod4:
8614 lbl28mod4:      Op28X1M0
8615                         NEXTOPCODE
8616 .pool
8617 Op29M0mod4:
8618 lbl29mod4:      Op29M0
8619                         NEXTOPCODE
8620 Op2AM0mod4:
8621 lbl2Amod4a:     A_ROL16
8622                         NEXTOPCODE
8623 Op2Bmod4:
8624 lbl2Bmod4:      Op2B
8625                         NEXTOPCODE
8626 Op2CM0mod4:
8627 lbl2Cmod4a:     Absolute
8628 lbl2Cmod4b:     BIT16
8629                         NEXTOPCODE
8630 Op2DM0mod4:
8631 lbl2Dmod4a:     Absolute
8632 lbl2Dmod4b:     AND16
8633                         NEXTOPCODE
8634 Op2EM0mod4:
8635 lbl2Emod4a:     Absolute
8636 lbl2Emod4b:     ROL16
8637                         NEXTOPCODE
8638 Op2FM0mod4:
8639 lbl2Fmod4a:     AbsoluteLong
8640 lbl2Fmod4b:     AND16
8641                         NEXTOPCODE
8642 Op30mod4:
8643 lbl30mod4:      Op30
8644                         NEXTOPCODE
8645 Op31M0mod4:
8646 lbl31mod4a:     DirectIndirectIndexed1
8647 lbl31mod4b:     AND16
8648                         NEXTOPCODE
8649 Op32M0mod4:
8650 lbl32mod4a:     DirectIndirect
8651 lbl32mod4b:     AND16
8652                         NEXTOPCODE
8653 Op33M0mod4:
8654 lbl33mod4a:     StackasmRelativeIndirectIndexed1
8655 lbl33mod4b:     AND16
8656                         NEXTOPCODE
8657 Op34M0mod4:
8658 lbl34mod4a:     DirectIndexedX1
8659 lbl34mod4b:     BIT16
8660                         NEXTOPCODE
8661 Op35M0mod4:
8662 lbl35mod4a:     DirectIndexedX1
8663 lbl35mod4b:     AND16
8664                         NEXTOPCODE
8665 Op36M0mod4:
8666 lbl36mod4a:     DirectIndexedX1
8667 lbl36mod4b:     ROL16
8668                         NEXTOPCODE
8669 Op37M0mod4:
8670 lbl37mod4a:     DirectIndirectIndexedLong1
8671 lbl37mod4b:     AND16
8672                         NEXTOPCODE
8673 Op38mod4:
8674 lbl38mod4:      Op38
8675                         NEXTOPCODE
8676 Op39M0mod4:
8677 lbl39mod4a:     AbsoluteIndexedY1
8678 lbl39mod4b:     AND16
8679                         NEXTOPCODE
8680 Op3AM0mod4:
8681 lbl3Amod4a:     A_DEC16
8682                         NEXTOPCODE
8683 Op3Bmod4:
8684 lbl3Bmod4:      Op3BM0
8685                         NEXTOPCODE
8686 Op3CM0mod4:
8687 lbl3Cmod4a:     AbsoluteIndexedX1
8688 lbl3Cmod4b:     BIT16
8689                         NEXTOPCODE
8690 Op3DM0mod4:
8691 lbl3Dmod4a:     AbsoluteIndexedX1
8692 lbl3Dmod4b:     AND16
8693                         NEXTOPCODE
8694 Op3EM0mod4:
8695 lbl3Emod4a:     AbsoluteIndexedX1
8696 lbl3Emod4b:     ROL16
8697                         NEXTOPCODE
8698 Op3FM0mod4:
8699 lbl3Fmod4a:     AbsoluteLongIndexedX1
8700 lbl3Fmod4b:     AND16
8701                         NEXTOPCODE
8702 Op40mod4:
8703 lbl40mod4:      Op40X1M0
8704                         NEXTOPCODE
8705 .pool
8706 Op41M0mod4:
8707 lbl41mod4a:     DirectIndexedIndirect1
8708 lbl41mod4b:     EOR16
8709                         NEXTOPCODE
8710 Op42mod4:
8711 lbl42mod4:      Op42
8712                         NEXTOPCODE
8713 Op43M0mod4:
8714 lbl43mod4a:     StackasmRelative
8715 lbl43mod4b:     EOR16
8716                         NEXTOPCODE
8717 Op44X1mod4:
8718 lbl44mod4:      Op44X1M0
8719                         NEXTOPCODE
8720 Op45M0mod4:
8721 lbl45mod4a:     Direct
8722 lbl45mod4b:     EOR16
8723                         NEXTOPCODE
8724 Op46M0mod4:
8725 lbl46mod4a:     Direct
8726 lbl46mod4b:     LSR16
8727                         NEXTOPCODE
8728 Op47M0mod4:
8729 lbl47mod4a:     DirectIndirectLong
8730 lbl47mod4b:     EOR16
8731                         NEXTOPCODE
8732 Op48M0mod4:
8733 lbl48mod4:      Op48M0
8734                         NEXTOPCODE
8735 Op49M0mod4:
8736 lbl49mod4:      Op49M0
8737                         NEXTOPCODE
8738 Op4AM0mod4:
8739 lbl4Amod4a:     A_LSR16
8740                         NEXTOPCODE
8741 Op4Bmod4:
8742 lbl4Bmod4:      Op4B
8743                         NEXTOPCODE
8744 Op4Cmod4:
8745 lbl4Cmod4:      Op4C
8746                         NEXTOPCODE
8747 Op4DM0mod4:
8748 lbl4Dmod4a:     Absolute
8749 lbl4Dmod4b:     EOR16
8750                         NEXTOPCODE
8751 Op4EM0mod4:
8752 lbl4Emod4a:     Absolute
8753 lbl4Emod4b:     LSR16
8754                         NEXTOPCODE
8755 Op4FM0mod4:
8756 lbl4Fmod4a:     AbsoluteLong
8757 lbl4Fmod4b:     EOR16
8758                         NEXTOPCODE
8759 Op50mod4:
8760 lbl50mod4:      Op50
8761                         NEXTOPCODE
8762 Op51M0mod4:
8763 lbl51mod4a:     DirectIndirectIndexed1
8764 lbl51mod4b:     EOR16
8765                         NEXTOPCODE
8766 Op52M0mod4:
8767 lbl52mod4a:     DirectIndirect
8768 lbl52mod4b:     EOR16
8769                         NEXTOPCODE
8770 Op53M0mod4:
8771 lbl53mod4a:     StackasmRelativeIndirectIndexed1
8772 lbl53mod4b:     EOR16
8773                         NEXTOPCODE
8774 Op54X1mod4:
8775 lbl54mod4:      Op54X1M0
8776                         NEXTOPCODE
8777 Op55M0mod4:
8778 lbl55mod4a:     DirectIndexedX1
8779 lbl55mod4b:     EOR16
8780                         NEXTOPCODE
8781 Op56M0mod4:
8782 lbl56mod4a:     DirectIndexedX1
8783 lbl56mod4b:     LSR16
8784                         NEXTOPCODE
8785 Op57M0mod4:
8786 lbl57mod4a:     DirectIndirectIndexedLong1
8787 lbl57mod4b:     EOR16
8788                         NEXTOPCODE
8789 Op58mod4:
8790 lbl58mod4:      Op58
8791                         NEXTOPCODE
8792 Op59M0mod4:
8793 lbl59mod4a:     AbsoluteIndexedY1
8794 lbl59mod4b:     EOR16
8795                         NEXTOPCODE
8796 Op5AX1mod4:
8797 lbl5Amod4:      Op5AX1
8798                         NEXTOPCODE
8799 Op5Bmod4:
8800 lbl5Bmod4:      Op5BM0
8801                         NEXTOPCODE
8802 Op5Cmod4:
8803 lbl5Cmod4:      Op5C
8804                         NEXTOPCODE
8805 Op5DM0mod4:
8806 lbl5Dmod4a:     AbsoluteIndexedX1
8807 lbl5Dmod4b:     EOR16
8808                         NEXTOPCODE
8809 Op5EM0mod4:
8810 lbl5Emod4a:     AbsoluteIndexedX1
8811 lbl5Emod4b:     LSR16
8812                         NEXTOPCODE
8813 Op5FM0mod4:
8814 lbl5Fmod4a:     AbsoluteLongIndexedX1
8815 lbl5Fmod4b:     EOR16
8816                         NEXTOPCODE
8817 Op60mod4:
8818 lbl60mod4:      Op60
8819                         NEXTOPCODE
8820 Op61M0mod4:
8821 lbl61mod4a:     DirectIndexedIndirect1
8822 lbl61mod4b:     ADC16
8823                         NEXTOPCODE
8824 Op62mod4:
8825 lbl62mod4:      Op62
8826                         NEXTOPCODE
8827 Op63M0mod4:
8828 lbl63mod4a:     StackasmRelative
8829 lbl63mod4b:     ADC16
8830                         NEXTOPCODE
8831 .pool
8832 Op64M0mod4:
8833 lbl64mod4a:     Direct
8834 lbl64mod4b:     STZ16
8835                         NEXTOPCODE
8836 Op65M0mod4:
8837 lbl65mod4a:     Direct
8838 lbl65mod4b:     ADC16
8839                         NEXTOPCODE
8840 .pool
8841 Op66M0mod4:
8842 lbl66mod4a:     Direct
8843 lbl66mod4b:     ROR16
8844                         NEXTOPCODE
8845 Op67M0mod4:
8846 lbl67mod4a:     DirectIndirectLong
8847 lbl67mod4b:     ADC16
8848                         NEXTOPCODE
8849 .pool
8850 Op68M0mod4:
8851 lbl68mod4:      Op68M0
8852                         NEXTOPCODE
8853 Op69M0mod4:
8854 lbl69mod4a:     Immediate16
8855 lbl69mod4b:     ADC16
8856                         NEXTOPCODE
8857 .pool
8858 Op6AM0mod4:
8859 lbl6Amod4a:     A_ROR16
8860                         NEXTOPCODE
8861 Op6Bmod4:
8862 lbl6Bmod4:      Op6B
8863                         NEXTOPCODE
8864 Op6Cmod4:
8865 lbl6Cmod4:      Op6C
8866                         NEXTOPCODE
8867 Op6DM0mod4:
8868 lbl6Dmod4a:     Absolute
8869 lbl6Dmod4b:     ADC16
8870                         NEXTOPCODE
8871 Op6EM0mod4:
8872 lbl6Emod4a:     Absolute
8873 lbl6Emod4b:     ROR16
8874                         NEXTOPCODE
8875 Op6FM0mod4:
8876 lbl6Fmod4a:     AbsoluteLong
8877 lbl6Fmod4b:     ADC16
8878                         NEXTOPCODE
8879 Op70mod4:
8880 lbl70mod4:      Op70
8881                         NEXTOPCODE
8882 Op71M0mod4:
8883 lbl71mod4a:     DirectIndirectIndexed1
8884 lbl71mod4b:     ADC16
8885                         NEXTOPCODE
8886 Op72M0mod4:
8887 lbl72mod4a:     DirectIndirect
8888 lbl72mod4b:     ADC16
8889                         NEXTOPCODE
8890 Op73M0mod4:
8891 lbl73mod4a:     StackasmRelativeIndirectIndexed1
8892 lbl73mod4b:     ADC16
8893                         NEXTOPCODE
8894 .pool
8895 Op74M0mod4:
8896 lbl74mod4a:     DirectIndexedX1
8897 lbl74mod4b:     STZ16
8898                         NEXTOPCODE
8899 Op75M0mod4:
8900 lbl75mod4a:     DirectIndexedX1
8901 lbl75mod4b:     ADC16
8902                         NEXTOPCODE
8903 .pool
8904 Op76M0mod4:
8905 lbl76mod4a:     DirectIndexedX1
8906 lbl76mod4b:     ROR16
8907                         NEXTOPCODE
8908 Op77M0mod4:
8909 lbl77mod4a:     DirectIndirectIndexedLong1
8910 lbl77mod4b:     ADC16
8911                         NEXTOPCODE
8912 Op78mod4:
8913 lbl78mod4:      Op78
8914                         NEXTOPCODE
8915 Op79M0mod4:
8916 lbl79mod4a:     AbsoluteIndexedY1
8917 lbl79mod4b:     ADC16
8918                         NEXTOPCODE
8919 Op7AX1mod4:
8920 lbl7Amod4:      Op7AX1
8921                         NEXTOPCODE
8922 Op7Bmod4:
8923 lbl7Bmod4:      Op7BM0
8924                         NEXTOPCODE
8925 Op7Cmod4:
8926 lbl7Cmod4:      AbsoluteIndexedIndirectX1
8927                 Op7C
8928                         NEXTOPCODE
8929 Op7DM0mod4:
8930 lbl7Dmod4a:     AbsoluteIndexedX1
8931 lbl7Dmod4b:     ADC16
8932                         NEXTOPCODE
8933 Op7EM0mod4:
8934 lbl7Emod4a:     AbsoluteIndexedX1
8935 lbl7Emod4b:     ROR16
8936                         NEXTOPCODE
8937 Op7FM0mod4:
8938 lbl7Fmod4a:     AbsoluteLongIndexedX1
8939 lbl7Fmod4b:     ADC16
8940                         NEXTOPCODE
8941 .pool
8942 Op80mod4:
8943 lbl80mod4:      Op80
8944                         NEXTOPCODE
8945 Op81M0mod4:
8946 lbl81mod4a:     DirectIndexedIndirect1
8947 lbl81mod4b:     Op81M0
8948                         NEXTOPCODE
8949 Op82mod4:
8950 lbl82mod4:      Op82
8951                         NEXTOPCODE
8952 Op83M0mod4:
8953 lbl83mod4a:     StackasmRelative
8954 lbl83mod4b:     STA16
8955                         NEXTOPCODE
8956 Op84X1mod4:
8957 lbl84mod4a:     Direct
8958 lbl84mod4b:     STY8
8959                         NEXTOPCODE
8960 Op85M0mod4:
8961 lbl85mod4a:     Direct
8962 lbl85mod4b:     STA16
8963                         NEXTOPCODE
8964 Op86X1mod4:
8965 lbl86mod4a:     Direct
8966 lbl86mod4b:     STX8
8967                         NEXTOPCODE
8968 Op87M0mod4:
8969 lbl87mod4a:     DirectIndirectLong
8970 lbl87mod4b:     STA16
8971                         NEXTOPCODE
8972 Op88X1mod4:
8973 lbl88mod4:      Op88X1
8974                         NEXTOPCODE
8975 Op89M0mod4:
8976 lbl89mod4:      Op89M0
8977                         NEXTOPCODE
8978 Op8AM0mod4:
8979 lbl8Amod4:      Op8AM0X1
8980                         NEXTOPCODE
8981 Op8Bmod4:
8982 lbl8Bmod4:      Op8B
8983                         NEXTOPCODE
8984 Op8CX1mod4:
8985 lbl8Cmod4a:     Absolute
8986 lbl8Cmod4b:     STY8
8987                         NEXTOPCODE
8988 Op8DM0mod4:
8989 lbl8Dmod4a:     Absolute
8990 lbl8Dmod4b:     STA16
8991                         NEXTOPCODE
8992 Op8EX1mod4:
8993 lbl8Emod4a:     Absolute
8994 lbl8Emod4b:     STX8
8995                         NEXTOPCODE
8996 Op8FM0mod4:
8997 lbl8Fmod4a:     AbsoluteLong
8998 lbl8Fmod4b:     STA16
8999                         NEXTOPCODE
9000 Op90mod4:
9001 lbl90mod4:      Op90
9002                         NEXTOPCODE
9003 Op91M0mod4:
9004 lbl91mod4a:     DirectIndirectIndexed1
9005 lbl91mod4b:     STA16
9006                         NEXTOPCODE
9007 Op92M0mod4:
9008 lbl92mod4a:     DirectIndirect
9009 lbl92mod4b:     STA16
9010                         NEXTOPCODE
9011 Op93M0mod4:
9012 lbl93mod4a:     StackasmRelativeIndirectIndexed1
9013 lbl93mod4b:     STA16
9014                         NEXTOPCODE
9015 Op94X1mod4:
9016 lbl94mod4a:     DirectIndexedX1
9017 lbl94mod4b:     STY8
9018                         NEXTOPCODE
9019 Op95M0mod4:
9020 lbl95mod4a:     DirectIndexedX1
9021 lbl95mod4b:     STA16
9022                         NEXTOPCODE
9023 Op96X1mod4:
9024 lbl96mod4a:     DirectIndexedY1
9025 lbl96mod4b:     STX8
9026                         NEXTOPCODE
9027 Op97M0mod4:
9028 lbl97mod4a:     DirectIndirectIndexedLong1
9029 lbl97mod4b:     STA16
9030                         NEXTOPCODE
9031 Op98M0mod4:
9032 lbl98mod4:      Op98M0X1
9033                         NEXTOPCODE
9034 Op99M0mod4:
9035 lbl99mod4a:     AbsoluteIndexedY1
9036 lbl99mod4b:     STA16
9037                         NEXTOPCODE
9038 Op9Amod4:
9039 lbl9Amod4:      Op9AX1
9040                         NEXTOPCODE
9041 Op9BX1mod4:
9042 lbl9Bmod4:      Op9BX1
9043                         NEXTOPCODE
9044 Op9CM0mod4:
9045 lbl9Cmod4a:     Absolute
9046 lbl9Cmod4b:     STZ16
9047                         NEXTOPCODE
9048 Op9DM0mod4:
9049 lbl9Dmod4a:     AbsoluteIndexedX1
9050 lbl9Dmod4b:     STA16
9051                         NEXTOPCODE
9052 Op9EM0mod4:
9053 lbl9Emod4:      AbsoluteIndexedX1
9054                 STZ16
9055                         NEXTOPCODE
9056 Op9FM0mod4:
9057 lbl9Fmod4a:     AbsoluteLongIndexedX1
9058 lbl9Fmod4b:     STA16
9059                         NEXTOPCODE
9060 OpA0X1mod4:
9061 lblA0mod4:      OpA0X1
9062                         NEXTOPCODE
9063 OpA1M0mod4:
9064 lblA1mod4a:     DirectIndexedIndirect1
9065 lblA1mod4b:     LDA16
9066                         NEXTOPCODE
9067 OpA2X1mod4:
9068 lblA2mod4:      OpA2X1
9069                         NEXTOPCODE
9070 OpA3M0mod4:
9071 lblA3mod4a:     StackasmRelative
9072 lblA3mod4b:     LDA16
9073                         NEXTOPCODE
9074 OpA4X1mod4:
9075 lblA4mod4a:     Direct
9076 lblA4mod4b:     LDY8
9077                         NEXTOPCODE
9078 OpA5M0mod4:
9079 lblA5mod4a:     Direct
9080 lblA5mod4b:     LDA16
9081                         NEXTOPCODE
9082 OpA6X1mod4:
9083 lblA6mod4a:     Direct
9084 lblA6mod4b:     LDX8
9085                         NEXTOPCODE
9086 OpA7M0mod4:
9087 lblA7mod4a:     DirectIndirectLong
9088 lblA7mod4b:     LDA16
9089                         NEXTOPCODE
9090 OpA8X1mod4:
9091 lblA8mod4:      OpA8X1M0
9092                         NEXTOPCODE
9093 OpA9M0mod4:
9094 lblA9mod4:      OpA9M0
9095                         NEXTOPCODE
9096 OpAAX1mod4:
9097 lblAAmod4:      OpAAX1M0
9098                         NEXTOPCODE
9099 OpABmod4:
9100 lblABmod4:      OpAB
9101                         NEXTOPCODE
9102 OpACX1mod4:
9103 lblACmod4a:     Absolute
9104 lblACmod4b:     LDY8
9105                         NEXTOPCODE
9106 OpADM0mod4:
9107 lblADmod4a:     Absolute
9108 lblADmod4b:     LDA16
9109                         NEXTOPCODE
9110 OpAEX1mod4:
9111 lblAEmod4a:     Absolute
9112 lblAEmod4b:     LDX8
9113                         NEXTOPCODE
9114 OpAFM0mod4:
9115 lblAFmod4a:     AbsoluteLong
9116 lblAFmod4b:     LDA16
9117                         NEXTOPCODE
9118 OpB0mod4:
9119 lblB0mod4:      OpB0
9120                         NEXTOPCODE
9121 OpB1M0mod4:
9122 lblB1mod4a:     DirectIndirectIndexed1
9123 lblB1mod4b:     LDA16
9124                         NEXTOPCODE
9125 OpB2M0mod4:
9126 lblB2mod4a:     DirectIndirect
9127 lblB2mod4b:     LDA16
9128                         NEXTOPCODE
9129 OpB3M0mod4:
9130 lblB3mod4a:     StackasmRelativeIndirectIndexed1
9131 lblB3mod4b:     LDA16
9132                         NEXTOPCODE
9133 OpB4X1mod4:
9134 lblB4mod4a:     DirectIndexedX1
9135 lblB4mod4b:     LDY8
9136                         NEXTOPCODE
9137 OpB5M0mod4:
9138 lblB5mod4a:     DirectIndexedX1
9139 lblB5mod4b:     LDA16
9140                         NEXTOPCODE
9141 OpB6X1mod4:
9142 lblB6mod4a:     DirectIndexedY1
9143 lblB6mod4b:     LDX8
9144                         NEXTOPCODE
9145 OpB7M0mod4:
9146 lblB7mod4a:     DirectIndirectIndexedLong1
9147 lblB7mod4b:     LDA16
9148                         NEXTOPCODE
9149 OpB8mod4:
9150 lblB8mod4:      OpB8
9151                         NEXTOPCODE
9152 OpB9M0mod4:
9153 lblB9mod4a:     AbsoluteIndexedY1
9154 lblB9mod4b:     LDA16
9155                         NEXTOPCODE
9156 OpBAX1mod4:
9157 lblBAmod4:      OpBAX1
9158                         NEXTOPCODE
9159 OpBBX1mod4:
9160 lblBBmod4:      OpBBX1
9161                         NEXTOPCODE
9162 OpBCX1mod4:
9163 lblBCmod4a:     AbsoluteIndexedX1
9164 lblBCmod4b:     LDY8
9165                         NEXTOPCODE
9166 OpBDM0mod4:
9167 lblBDmod4a:     AbsoluteIndexedX1
9168 lblBDmod4b:     LDA16
9169                         NEXTOPCODE
9170 OpBEX1mod4:
9171 lblBEmod4a:     AbsoluteIndexedY1
9172 lblBEmod4b:     LDX8
9173                         NEXTOPCODE
9174 OpBFM0mod4:
9175 lblBFmod4a:     AbsoluteLongIndexedX1
9176 lblBFmod4b:     LDA16
9177                         NEXTOPCODE
9178 OpC0X1mod4:
9179 lblC0mod4:      OpC0X1
9180                         NEXTOPCODE
9181 OpC1M0mod4:
9182 lblC1mod4a:     DirectIndexedIndirect1
9183 lblC1mod4b:     CMP16
9184                         NEXTOPCODE
9185 OpC2mod4:
9186 lblC2mod4:      OpC2
9187                         NEXTOPCODE
9188 .pool
9189 OpC3M0mod4:
9190 lblC3mod4a:     StackasmRelative
9191 lblC3mod4b:     CMP16
9192                         NEXTOPCODE
9193 OpC4X1mod4:
9194 lblC4mod4a:     Direct
9195 lblC4mod4b:     CMY8
9196                         NEXTOPCODE
9197 OpC5M0mod4:
9198 lblC5mod4a:     Direct
9199 lblC5mod4b:     CMP16
9200                         NEXTOPCODE
9201 OpC6M0mod4:
9202 lblC6mod4a:     Direct
9203 lblC6mod4b:     DEC16
9204                         NEXTOPCODE
9205 OpC7M0mod4:
9206 lblC7mod4a:     DirectIndirectLong
9207 lblC7mod4b:     CMP16
9208                         NEXTOPCODE
9209 OpC8X1mod4:
9210 lblC8mod4:      OpC8X1
9211                         NEXTOPCODE
9212 OpC9M0mod4:
9213 lblC9mod4:      OpC9M0
9214                         NEXTOPCODE
9215 OpCAX1mod4:
9216 lblCAmod4:      OpCAX1
9217                         NEXTOPCODE
9218 OpCBmod4:
9219 lblCBmod4:      OpCB
9220                         NEXTOPCODE
9221 OpCCX1mod4:
9222 lblCCmod4a:     Absolute
9223 lblCCmod4b:     CMY8
9224                         NEXTOPCODE
9225 OpCDM0mod4:
9226 lblCDmod4a:     Absolute
9227 lblCDmod4b:     CMP16
9228                         NEXTOPCODE
9229 OpCEM0mod4:
9230 lblCEmod4a:     Absolute
9231 lblCEmod4b:     DEC16
9232                         NEXTOPCODE
9233 OpCFM0mod4:
9234 lblCFmod4a:     AbsoluteLong
9235 lblCFmod4b:     CMP16
9236                         NEXTOPCODE
9237 OpD0mod4:
9238 lblD0mod4:      OpD0
9239                         NEXTOPCODE
9240 OpD1M0mod4:
9241 lblD1mod4a:     DirectIndirectIndexed1
9242 lblD1mod4b:     CMP16
9243                         NEXTOPCODE
9244 OpD2M0mod4:
9245 lblD2mod4a:     DirectIndirect
9246 lblD2mod4b:     CMP16
9247                         NEXTOPCODE
9248 OpD3M0mod4:
9249 lblD3mod4a:     StackasmRelativeIndirectIndexed1
9250 lblD3mod4b:     CMP16
9251                         NEXTOPCODE
9252 OpD4mod4:
9253 lblD4mod4:      OpD4
9254                         NEXTOPCODE
9255 OpD5M0mod4:
9256 lblD5mod4a:     DirectIndexedX1
9257 lblD5mod4b:     CMP16
9258                         NEXTOPCODE
9259 OpD6M0mod4:
9260 lblD6mod4a:     DirectIndexedX1
9261 lblD6mod4b:     DEC16
9262                         NEXTOPCODE
9263 OpD7M0mod4:
9264 lblD7mod4a:     DirectIndirectIndexedLong1
9265 lblD7mod4b:     CMP16
9266                         NEXTOPCODE
9267 OpD8mod4:
9268 lblD8mod4:      OpD8
9269                         NEXTOPCODE
9270 OpD9M0mod4:
9271 lblD9mod4a:     AbsoluteIndexedY1
9272 lblD9mod4b:     CMP16
9273                         NEXTOPCODE
9274 OpDAX1mod4:
9275 lblDAmod4:      OpDAX1
9276                         NEXTOPCODE
9277 OpDBmod4:
9278 lblDBmod4:      OpDB
9279                         NEXTOPCODE
9280 OpDCmod4:
9281 lblDCmod4:      OpDC
9282                         NEXTOPCODE
9283 OpDDM0mod4:
9284 lblDDmod4a:     AbsoluteIndexedX1
9285 lblDDmod4b:     CMP16
9286                         NEXTOPCODE
9287 OpDEM0mod4:
9288 lblDEmod4a:     AbsoluteIndexedX1
9289 lblDEmod4b:     DEC16
9290                         NEXTOPCODE
9291 OpDFM0mod4:
9292 lblDFmod4a:     AbsoluteLongIndexedX1
9293 lblDFmod4b:     CMP16
9294                         NEXTOPCODE
9295 OpE0X1mod4:
9296 lblE0mod4:      OpE0X1
9297                         NEXTOPCODE
9298 OpE1M0mod4:
9299 lblE1mod4a:     DirectIndexedIndirect1
9300 lblE1mod4b:     SBC16
9301                         NEXTOPCODE
9302 OpE2mod4:
9303 lblE2mod4:      OpE2
9304                         NEXTOPCODE
9305 .pool
9306 OpE3M0mod4:
9307 lblE3mod4a:     StackasmRelative
9308 lblE3mod4b:     SBC16
9309                         NEXTOPCODE
9310 OpE4X1mod4:
9311 lblE4mod4a:     Direct
9312 lblE4mod4b:     CMX8
9313                         NEXTOPCODE
9314 OpE5M0mod4:
9315 lblE5mod4a:     Direct
9316 lblE5mod4b:     SBC16
9317                         NEXTOPCODE
9318 OpE6M0mod4:
9319 lblE6mod4a:     Direct
9320 lblE6mod4b:     INC16
9321                         NEXTOPCODE
9322 OpE7M0mod4:
9323 lblE7mod4a:     DirectIndirectLong
9324 lblE7mod4b:     SBC16
9325                         NEXTOPCODE
9326 OpE8X1mod4:
9327 lblE8mod4:      OpE8X1
9328                         NEXTOPCODE
9329 OpE9M0mod4:
9330 lblE9mod4a:     Immediate16
9331 lblE9mod4b:     SBC16
9332                         NEXTOPCODE
9333 OpEAmod4:
9334 lblEAmod4:      OpEA
9335                         NEXTOPCODE
9336 OpEBmod4:
9337 lblEBmod4:      OpEBM0
9338                         NEXTOPCODE
9339 OpECX1mod4:
9340 lblECmod4a:     Absolute
9341 lblECmod4b:     CMX8
9342                         NEXTOPCODE
9343 OpEDM0mod4:
9344 lblEDmod4a:     Absolute
9345 lblEDmod4b:     SBC16
9346                         NEXTOPCODE
9347 OpEEM0mod4:
9348 lblEEmod4a:     Absolute
9349 lblEEmod4b:     INC16
9350                         NEXTOPCODE
9351 OpEFM0mod4:
9352 lblEFmod4a:     AbsoluteLong
9353 lblEFmod4b:     SBC16
9354                         NEXTOPCODE
9355 OpF0mod4:
9356 lblF0mod4:      OpF0
9357                         NEXTOPCODE
9358 OpF1M0mod4:
9359 lblF1mod4a:     DirectIndirectIndexed1
9360 lblF1mod4b:     SBC16
9361                         NEXTOPCODE
9362 OpF2M0mod4:
9363 lblF2mod4a:     DirectIndirect
9364 lblF2mod4b:     SBC16
9365                         NEXTOPCODE
9366 OpF3M0mod4:
9367 lblF3mod4a:     StackasmRelativeIndirectIndexed1
9368 lblF3mod4b:     SBC16
9369                         NEXTOPCODE
9370 OpF4mod4:
9371 lblF4mod4:      OpF4
9372                         NEXTOPCODE
9373 OpF5M0mod4:
9374 lblF5mod4a:     DirectIndexedX1
9375 lblF5mod4b:     SBC16
9376                         NEXTOPCODE
9377 OpF6M0mod4:
9378 lblF6mod4a:     DirectIndexedX1
9379 lblF6mod4b:     INC16
9380                         NEXTOPCODE
9381 OpF7M0mod4:
9382 lblF7mod4a:     DirectIndirectIndexedLong1
9383 lblF7mod4b:     SBC16
9384                         NEXTOPCODE
9385 OpF8mod4:
9386 lblF8mod4:      OpF8
9387                         NEXTOPCODE
9388 OpF9M0mod4:
9389 lblF9mod4a:     AbsoluteIndexedY1
9390 lblF9mod4b:     SBC16
9391                         NEXTOPCODE
9392 OpFAX1mod4:
9393 lblFAmod4:      OpFAX1
9394                         NEXTOPCODE
9395 OpFBmod4:
9396 lblFBmod4:      OpFB
9397                         NEXTOPCODE
9398 OpFCmod4:
9399 lblFCmod4:      OpFCX1
9400                         NEXTOPCODE
9401 OpFDM0mod4:
9402 lblFDmod4a:     AbsoluteIndexedX1
9403 lblFDmod4b:     SBC16
9404                         NEXTOPCODE
9405 OpFEM0mod4:
9406 lblFEmod4a:     AbsoluteIndexedX1
9407 lblFEmod4b:     INC16
9408                         NEXTOPCODE
9409 OpFFM0mod4:
9410 lblFFmod4a:     AbsoluteLongIndexedX1
9411 lblFFmod4b:     SBC16
9412                         NEXTOPCODE
9413
9414
9415                         .pool
9416