2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
28 #include "host-utils.h"
30 #include "qemu-common.h"
36 /* #define DO_SINGLE_STEP */
37 #define ALPHA_DEBUG_DISAS
38 /* #define DO_TB_FLUSH */
41 #ifdef ALPHA_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
44 # define LOG_DISAS(...) do { } while (0)
47 typedef struct DisasContext DisasContext;
51 #if !defined (CONFIG_USER_ONLY)
57 /* global register indexes */
58 static TCGv_ptr cpu_env;
59 static TCGv cpu_ir[31];
60 static TCGv cpu_fir[31];
65 static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
67 #include "gen-icount.h"
69 static void alpha_translate_init(void)
73 static int done_init = 0;
78 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
81 for (i = 0; i < 31; i++) {
82 sprintf(p, "ir%d", i);
83 cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
84 offsetof(CPUState, ir[i]), p);
85 p += (i < 10) ? 4 : 5;
87 sprintf(p, "fir%d", i);
88 cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
89 offsetof(CPUState, fir[i]), p);
90 p += (i < 10) ? 5 : 6;
93 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
94 offsetof(CPUState, pc), "pc");
96 cpu_lock = tcg_global_mem_new_i64(TCG_AREG0,
97 offsetof(CPUState, lock), "lock");
99 /* register helpers */
106 static always_inline void gen_excp (DisasContext *ctx,
107 int exception, int error_code)
111 tcg_gen_movi_i64(cpu_pc, ctx->pc);
112 tmp1 = tcg_const_i32(exception);
113 tmp2 = tcg_const_i32(error_code);
114 gen_helper_excp(tmp1, tmp2);
115 tcg_temp_free_i32(tmp2);
116 tcg_temp_free_i32(tmp1);
119 static always_inline void gen_invalid (DisasContext *ctx)
121 gen_excp(ctx, EXCP_OPCDEC, 0);
124 static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
126 TCGv tmp = tcg_temp_new();
127 TCGv_i32 tmp32 = tcg_temp_new_i32();
128 tcg_gen_qemu_ld32u(tmp, t1, flags);
129 tcg_gen_trunc_i64_i32(tmp32, tmp);
130 gen_helper_memory_to_f(t0, tmp32);
131 tcg_temp_free_i32(tmp32);
135 static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
137 TCGv tmp = tcg_temp_new();
138 tcg_gen_qemu_ld64(tmp, t1, flags);
139 gen_helper_memory_to_g(t0, tmp);
143 static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
145 TCGv tmp = tcg_temp_new();
146 TCGv_i32 tmp32 = tcg_temp_new_i32();
147 tcg_gen_qemu_ld32u(tmp, t1, flags);
148 tcg_gen_trunc_i64_i32(tmp32, tmp);
149 gen_helper_memory_to_s(t0, tmp32);
150 tcg_temp_free_i32(tmp32);
154 static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
156 tcg_gen_mov_i64(cpu_lock, t1);
157 tcg_gen_qemu_ld32s(t0, t1, flags);
160 static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
162 tcg_gen_mov_i64(cpu_lock, t1);
163 tcg_gen_qemu_ld64(t0, t1, flags);
166 static always_inline void gen_load_mem (DisasContext *ctx,
167 void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
168 int ra, int rb, int32_t disp16,
173 if (unlikely(ra == 31))
176 addr = tcg_temp_new();
178 tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
180 tcg_gen_andi_i64(addr, addr, ~0x7);
184 tcg_gen_movi_i64(addr, disp16);
187 tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx);
189 tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);
193 static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
195 TCGv_i32 tmp32 = tcg_temp_new_i32();
196 TCGv tmp = tcg_temp_new();
197 gen_helper_f_to_memory(tmp32, t0);
198 tcg_gen_extu_i32_i64(tmp, tmp32);
199 tcg_gen_qemu_st32(tmp, t1, flags);
201 tcg_temp_free_i32(tmp32);
204 static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
206 TCGv tmp = tcg_temp_new();
207 gen_helper_g_to_memory(tmp, t0);
208 tcg_gen_qemu_st64(tmp, t1, flags);
212 static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
214 TCGv_i32 tmp32 = tcg_temp_new_i32();
215 TCGv tmp = tcg_temp_new();
216 gen_helper_s_to_memory(tmp32, t0);
217 tcg_gen_extu_i32_i64(tmp, tmp32);
218 tcg_gen_qemu_st32(tmp, t1, flags);
220 tcg_temp_free_i32(tmp32);
223 static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
227 l1 = gen_new_label();
228 l2 = gen_new_label();
229 tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
230 tcg_gen_qemu_st32(t0, t1, flags);
231 tcg_gen_movi_i64(t0, 1);
234 tcg_gen_movi_i64(t0, 0);
236 tcg_gen_movi_i64(cpu_lock, -1);
239 static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
243 l1 = gen_new_label();
244 l2 = gen_new_label();
245 tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
246 tcg_gen_qemu_st64(t0, t1, flags);
247 tcg_gen_movi_i64(t0, 1);
250 tcg_gen_movi_i64(t0, 0);
252 tcg_gen_movi_i64(cpu_lock, -1);
255 static always_inline void gen_store_mem (DisasContext *ctx,
256 void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
257 int ra, int rb, int32_t disp16,
258 int fp, int clear, int local)
262 addr = tcg_temp_local_new();
264 addr = tcg_temp_new();
266 tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
268 tcg_gen_andi_i64(addr, addr, ~0x7);
272 tcg_gen_movi_i64(addr, disp16);
276 tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx);
278 tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
282 zero = tcg_const_local_i64(0);
284 zero = tcg_const_i64(0);
285 tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
291 static always_inline void gen_bcond (DisasContext *ctx,
293 int ra, int32_t disp, int mask)
297 l1 = gen_new_label();
298 l2 = gen_new_label();
299 if (likely(ra != 31)) {
301 TCGv tmp = tcg_temp_new();
302 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
303 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
306 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
308 /* Very uncommon case - Do not bother to optimize. */
309 TCGv tmp = tcg_const_i64(0);
310 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
313 tcg_gen_movi_i64(cpu_pc, ctx->pc);
316 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
320 static always_inline void gen_fbcond (DisasContext *ctx, int opc,
321 int ra, int32_t disp16)
327 l1 = gen_new_label();
328 l2 = gen_new_label();
330 tmp = tcg_temp_new();
333 tmp = tcg_const_i64(0);
337 case 0x31: /* FBEQ */
338 gen_helper_cmpfeq(tmp, src);
340 case 0x32: /* FBLT */
341 gen_helper_cmpflt(tmp, src);
343 case 0x33: /* FBLE */
344 gen_helper_cmpfle(tmp, src);
346 case 0x35: /* FBNE */
347 gen_helper_cmpfne(tmp, src);
349 case 0x36: /* FBGE */
350 gen_helper_cmpfge(tmp, src);
352 case 0x37: /* FBGT */
353 gen_helper_cmpfgt(tmp, src);
358 tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1);
359 tcg_gen_movi_i64(cpu_pc, ctx->pc);
362 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
366 static always_inline void gen_cmov (TCGCond inv_cond,
367 int ra, int rb, int rc,
368 int islit, uint8_t lit, int mask)
372 if (unlikely(rc == 31))
375 l1 = gen_new_label();
379 TCGv tmp = tcg_temp_new();
380 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
381 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
384 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
386 /* Very uncommon case - Do not bother to optimize. */
387 TCGv tmp = tcg_const_i64(0);
388 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
393 tcg_gen_movi_i64(cpu_ir[rc], lit);
395 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
399 #define FARITH2(name) \
400 static always_inline void glue(gen_f, name)(int rb, int rc) \
402 if (unlikely(rc == 31)) \
406 gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \
408 TCGv tmp = tcg_const_i64(0); \
409 gen_helper_ ## name (cpu_fir[rc], tmp); \
410 tcg_temp_free(tmp); \
431 #define FARITH3(name) \
432 static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
434 if (unlikely(rc == 31)) \
439 gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \
441 TCGv tmp = tcg_const_i64(0); \
442 gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \
443 tcg_temp_free(tmp); \
446 TCGv tmp = tcg_const_i64(0); \
448 gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \
450 gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \
451 tcg_temp_free(tmp); \
482 #define FCMOV(name) \
483 static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
488 if (unlikely(rc == 31)) \
491 l1 = gen_new_label(); \
492 tmp = tcg_temp_new(); \
494 tmp = tcg_temp_new(); \
495 gen_helper_ ## name (tmp, cpu_fir[ra]); \
497 tmp = tcg_const_i64(0); \
498 gen_helper_ ## name (tmp, tmp); \
500 tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \
502 tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \
504 tcg_gen_movi_i64(cpu_fir[rc], 0); \
514 /* EXTWH, EXTWH, EXTLH, EXTQH */
515 static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
516 int ra, int rb, int rc,
517 int islit, uint8_t lit)
519 if (unlikely(rc == 31))
525 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
527 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
530 tmp1 = tcg_temp_new();
531 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
532 tcg_gen_shli_i64(tmp1, tmp1, 3);
533 tmp2 = tcg_const_i64(64);
534 tcg_gen_sub_i64(tmp1, tmp2, tmp1);
536 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
540 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
542 tcg_gen_movi_i64(cpu_ir[rc], 0);
545 /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
546 static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
547 int ra, int rb, int rc,
548 int islit, uint8_t lit)
550 if (unlikely(rc == 31))
555 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
557 TCGv tmp = tcg_temp_new();
558 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
559 tcg_gen_shli_i64(tmp, tmp, 3);
560 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
564 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
566 tcg_gen_movi_i64(cpu_ir[rc], 0);
569 /* Code to call arith3 helpers */
570 #define ARITH3(name) \
571 static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
572 int islit, uint8_t lit) \
574 if (unlikely(rc == 31)) \
579 TCGv tmp = tcg_const_i64(lit); \
580 gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \
581 tcg_temp_free(tmp); \
583 gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \
585 TCGv tmp1 = tcg_const_i64(0); \
587 TCGv tmp2 = tcg_const_i64(lit); \
588 gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \
589 tcg_temp_free(tmp2); \
591 gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \
592 tcg_temp_free(tmp1); \
620 static always_inline void gen_cmp(TCGCond cond,
621 int ra, int rb, int rc,
622 int islit, uint8_t lit)
627 if (unlikely(rc == 31))
630 l1 = gen_new_label();
631 l2 = gen_new_label();
634 tmp = tcg_temp_new();
635 tcg_gen_mov_i64(tmp, cpu_ir[ra]);
637 tmp = tcg_const_i64(0);
639 tcg_gen_brcondi_i64(cond, tmp, lit, l1);
641 tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
643 tcg_gen_movi_i64(cpu_ir[rc], 0);
646 tcg_gen_movi_i64(cpu_ir[rc], 1);
650 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
653 int32_t disp21, disp16, disp12;
655 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
659 /* Decode all instruction fields */
661 ra = (insn >> 21) & 0x1F;
662 rb = (insn >> 16) & 0x1F;
664 sbz = (insn >> 13) & 0x07;
665 islit = (insn >> 12) & 1;
666 if (rb == 31 && !islit) {
670 lit = (insn >> 13) & 0xFF;
671 palcode = insn & 0x03FFFFFF;
672 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
673 disp16 = (int16_t)(insn & 0x0000FFFF);
674 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
675 fn16 = insn & 0x0000FFFF;
676 fn11 = (insn >> 5) & 0x000007FF;
678 fn7 = (insn >> 5) & 0x0000007F;
679 fn2 = (insn >> 5) & 0x00000003;
681 LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
682 opc, ra, rb, rc, disp16);
686 if (palcode >= 0x80 && palcode < 0xC0) {
687 /* Unprivileged PAL call */
688 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
689 #if !defined (CONFIG_USER_ONLY)
690 } else if (palcode < 0x40) {
691 /* Privileged PAL code */
692 if (ctx->mem_idx & 1)
695 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
698 /* Invalid PAL call */
726 if (likely(ra != 31)) {
728 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
730 tcg_gen_movi_i64(cpu_ir[ra], disp16);
735 if (likely(ra != 31)) {
737 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
739 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
744 if (!(ctx->amask & AMASK_BWX))
746 gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
750 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
754 if (!(ctx->amask & AMASK_BWX))
756 gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
760 gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0);
764 gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0);
768 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0);
774 if (likely(rc != 31)) {
777 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
778 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
780 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
781 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
785 tcg_gen_movi_i64(cpu_ir[rc], lit);
787 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
793 if (likely(rc != 31)) {
795 TCGv tmp = tcg_temp_new();
796 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
798 tcg_gen_addi_i64(tmp, tmp, lit);
800 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
801 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
805 tcg_gen_movi_i64(cpu_ir[rc], lit);
807 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
813 if (likely(rc != 31)) {
816 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
818 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
819 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
822 tcg_gen_movi_i64(cpu_ir[rc], -lit);
824 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
825 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
831 if (likely(rc != 31)) {
833 TCGv tmp = tcg_temp_new();
834 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
836 tcg_gen_subi_i64(tmp, tmp, lit);
838 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
839 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
843 tcg_gen_movi_i64(cpu_ir[rc], -lit);
845 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
846 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
853 gen_cmpbge(ra, rb, rc, islit, lit);
857 if (likely(rc != 31)) {
859 TCGv tmp = tcg_temp_new();
860 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
862 tcg_gen_addi_i64(tmp, tmp, lit);
864 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
865 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
869 tcg_gen_movi_i64(cpu_ir[rc], lit);
871 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
877 if (likely(rc != 31)) {
879 TCGv tmp = tcg_temp_new();
880 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
882 tcg_gen_subi_i64(tmp, tmp, lit);
884 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
885 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
889 tcg_gen_movi_i64(cpu_ir[rc], -lit);
891 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
892 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
899 gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
903 if (likely(rc != 31)) {
906 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
908 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
911 tcg_gen_movi_i64(cpu_ir[rc], lit);
913 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
919 if (likely(rc != 31)) {
921 TCGv tmp = tcg_temp_new();
922 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
924 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
926 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
930 tcg_gen_movi_i64(cpu_ir[rc], lit);
932 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
938 if (likely(rc != 31)) {
941 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
943 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
946 tcg_gen_movi_i64(cpu_ir[rc], -lit);
948 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
954 if (likely(rc != 31)) {
956 TCGv tmp = tcg_temp_new();
957 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
959 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
961 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
965 tcg_gen_movi_i64(cpu_ir[rc], -lit);
967 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
973 gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
977 if (likely(rc != 31)) {
979 TCGv tmp = tcg_temp_new();
980 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
982 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
984 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
988 tcg_gen_movi_i64(cpu_ir[rc], lit);
990 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
996 if (likely(rc != 31)) {
998 TCGv tmp = tcg_temp_new();
999 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1001 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
1003 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1007 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1009 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1015 gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
1019 gen_addlv(ra, rb, rc, islit, lit);
1023 gen_sublv(ra, rb, rc, islit, lit);
1027 gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
1031 gen_addqv(ra, rb, rc, islit, lit);
1035 gen_subqv(ra, rb, rc, islit, lit);
1039 gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
1049 if (likely(rc != 31)) {
1051 tcg_gen_movi_i64(cpu_ir[rc], 0);
1053 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1055 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1060 if (likely(rc != 31)) {
1063 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1065 tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1067 tcg_gen_movi_i64(cpu_ir[rc], 0);
1072 gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
1076 gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
1080 if (likely(rc != 31)) {
1083 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1085 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1088 tcg_gen_movi_i64(cpu_ir[rc], lit);
1090 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1096 gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
1100 gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
1104 if (likely(rc != 31)) {
1107 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1109 tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1112 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1114 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1120 if (likely(rc != 31)) {
1123 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1125 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1128 tcg_gen_movi_i64(cpu_ir[rc], lit);
1130 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1136 gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
1140 gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
1144 if (likely(rc != 31)) {
1147 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1149 tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1152 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1154 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1160 if (likely(rc != 31)) {
1162 tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit));
1164 gen_helper_amask(cpu_ir[rc], cpu_ir[rb]);
1169 gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
1173 gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
1178 gen_helper_load_implver(cpu_ir[rc]);
1188 gen_mskbl(ra, rb, rc, islit, lit);
1192 gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit);
1196 gen_insbl(ra, rb, rc, islit, lit);
1200 gen_mskwl(ra, rb, rc, islit, lit);
1204 gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1208 gen_inswl(ra, rb, rc, islit, lit);
1212 gen_mskll(ra, rb, rc, islit, lit);
1216 gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
1220 gen_insll(ra, rb, rc, islit, lit);
1224 gen_zap(ra, rb, rc, islit, lit);
1228 gen_zapnot(ra, rb, rc, islit, lit);
1232 gen_mskql(ra, rb, rc, islit, lit);
1236 if (likely(rc != 31)) {
1239 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1241 TCGv shift = tcg_temp_new();
1242 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1243 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1244 tcg_temp_free(shift);
1247 tcg_gen_movi_i64(cpu_ir[rc], 0);
1252 gen_ext_l(NULL, ra, rb, rc, islit, lit);
1256 if (likely(rc != 31)) {
1259 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1261 TCGv shift = tcg_temp_new();
1262 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1263 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1264 tcg_temp_free(shift);
1267 tcg_gen_movi_i64(cpu_ir[rc], 0);
1272 gen_insql(ra, rb, rc, islit, lit);
1276 if (likely(rc != 31)) {
1279 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1281 TCGv shift = tcg_temp_new();
1282 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1283 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1284 tcg_temp_free(shift);
1287 tcg_gen_movi_i64(cpu_ir[rc], 0);
1292 gen_mskwh(ra, rb, rc, islit, lit);
1296 gen_inswh(ra, rb, rc, islit, lit);
1300 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1304 gen_msklh(ra, rb, rc, islit, lit);
1308 gen_inslh(ra, rb, rc, islit, lit);
1312 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1316 gen_mskqh(ra, rb, rc, islit, lit);
1320 gen_insqh(ra, rb, rc, islit, lit);
1324 gen_ext_h(NULL, ra, rb, rc, islit, lit);
1334 if (likely(rc != 31)) {
1336 tcg_gen_movi_i64(cpu_ir[rc], 0);
1339 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1341 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1342 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1348 if (likely(rc != 31)) {
1350 tcg_gen_movi_i64(cpu_ir[rc], 0);
1352 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1354 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1359 gen_umulh(ra, rb, rc, islit, lit);
1363 gen_mullv(ra, rb, rc, islit, lit);
1367 gen_mulqv(ra, rb, rc, islit, lit);
1374 switch (fpfn) { /* f11 & 0x3F */
1377 if (!(ctx->amask & AMASK_FIX))
1379 if (likely(rc != 31)) {
1381 TCGv_i32 tmp = tcg_temp_new_i32();
1382 tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
1383 gen_helper_memory_to_s(cpu_fir[rc], tmp);
1384 tcg_temp_free_i32(tmp);
1386 tcg_gen_movi_i64(cpu_fir[rc], 0);
1391 if (!(ctx->amask & AMASK_FIX))
1397 if (!(ctx->amask & AMASK_FIX))
1403 if (!(ctx->amask & AMASK_FIX))
1405 if (likely(rc != 31)) {
1407 TCGv_i32 tmp = tcg_temp_new_i32();
1408 tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
1409 gen_helper_memory_to_f(cpu_fir[rc], tmp);
1410 tcg_temp_free_i32(tmp);
1412 tcg_gen_movi_i64(cpu_fir[rc], 0);
1417 if (!(ctx->amask & AMASK_FIX))
1419 if (likely(rc != 31)) {
1421 tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
1423 tcg_gen_movi_i64(cpu_fir[rc], 0);
1428 if (!(ctx->amask & AMASK_FIX))
1434 if (!(ctx->amask & AMASK_FIX))
1443 /* VAX floating point */
1444 /* XXX: rounding mode and trap are ignored (!) */
1445 switch (fpfn) { /* f11 & 0x3F */
1448 gen_faddf(ra, rb, rc);
1452 gen_fsubf(ra, rb, rc);
1456 gen_fmulf(ra, rb, rc);
1460 gen_fdivf(ra, rb, rc);
1472 gen_faddg(ra, rb, rc);
1476 gen_fsubg(ra, rb, rc);
1480 gen_fmulg(ra, rb, rc);
1484 gen_fdivg(ra, rb, rc);
1488 gen_fcmpgeq(ra, rb, rc);
1492 gen_fcmpglt(ra, rb, rc);
1496 gen_fcmpgle(ra, rb, rc);
1527 /* IEEE floating-point */
1528 /* XXX: rounding mode and traps are ignored (!) */
1529 switch (fpfn) { /* f11 & 0x3F */
1532 gen_fadds(ra, rb, rc);
1536 gen_fsubs(ra, rb, rc);
1540 gen_fmuls(ra, rb, rc);
1544 gen_fdivs(ra, rb, rc);
1548 gen_faddt(ra, rb, rc);
1552 gen_fsubt(ra, rb, rc);
1556 gen_fmult(ra, rb, rc);
1560 gen_fdivt(ra, rb, rc);
1564 gen_fcmptun(ra, rb, rc);
1568 gen_fcmpteq(ra, rb, rc);
1572 gen_fcmptlt(ra, rb, rc);
1576 gen_fcmptle(ra, rb, rc);
1579 /* XXX: incorrect */
1580 if (fn11 == 0x2AC || fn11 == 0x6AC) {
1611 if (likely(rc != 31)) {
1614 tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
1617 gen_fcpys(ra, rb, rc);
1622 gen_fcpysn(ra, rb, rc);
1626 gen_fcpyse(ra, rb, rc);
1630 if (likely(ra != 31))
1631 gen_helper_store_fpcr(cpu_fir[ra]);
1633 TCGv tmp = tcg_const_i64(0);
1634 gen_helper_store_fpcr(tmp);
1640 if (likely(ra != 31))
1641 gen_helper_load_fpcr(cpu_fir[ra]);
1645 gen_fcmpfeq(ra, rb, rc);
1649 gen_fcmpfne(ra, rb, rc);
1653 gen_fcmpflt(ra, rb, rc);
1657 gen_fcmpfge(ra, rb, rc);
1661 gen_fcmpfle(ra, rb, rc);
1665 gen_fcmpfgt(ra, rb, rc);
1673 gen_fcvtqlv(rb, rc);
1677 gen_fcvtqlsv(rb, rc);
1684 switch ((uint16_t)disp16) {
1687 /* No-op. Just exit from the current tb */
1692 /* No-op. Just exit from the current tb */
1714 gen_helper_load_pcc(cpu_ir[ra]);
1719 gen_helper_rc(cpu_ir[ra]);
1723 /* XXX: TODO: evict tb cache at address rb */
1733 gen_helper_rs(cpu_ir[ra]);
1744 /* HW_MFPR (PALcode) */
1745 #if defined (CONFIG_USER_ONLY)
1751 TCGv tmp = tcg_const_i32(insn & 0xFF);
1752 gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]);
1759 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1761 tcg_gen_movi_i64(cpu_pc, 0);
1763 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1764 /* Those four jumps only differ by the branch prediction hint */
1782 /* HW_LD (PALcode) */
1783 #if defined (CONFIG_USER_ONLY)
1789 TCGv addr = tcg_temp_new();
1791 tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
1793 tcg_gen_movi_i64(addr, disp12);
1794 switch ((insn >> 12) & 0xF) {
1796 /* Longword physical access (hw_ldl/p) */
1797 gen_helper_ldl_raw(cpu_ir[ra], addr);
1800 /* Quadword physical access (hw_ldq/p) */
1801 gen_helper_ldq_raw(cpu_ir[ra], addr);
1804 /* Longword physical access with lock (hw_ldl_l/p) */
1805 gen_helper_ldl_l_raw(cpu_ir[ra], addr);
1808 /* Quadword physical access with lock (hw_ldq_l/p) */
1809 gen_helper_ldq_l_raw(cpu_ir[ra], addr);
1812 /* Longword virtual PTE fetch (hw_ldl/v) */
1813 tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
1816 /* Quadword virtual PTE fetch (hw_ldq/v) */
1817 tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
1820 /* Incpu_ir[ra]id */
1823 /* Incpu_ir[ra]id */
1826 /* Longword virtual access (hw_ldl) */
1827 gen_helper_st_virt_to_phys(addr, addr);
1828 gen_helper_ldl_raw(cpu_ir[ra], addr);
1831 /* Quadword virtual access (hw_ldq) */
1832 gen_helper_st_virt_to_phys(addr, addr);
1833 gen_helper_ldq_raw(cpu_ir[ra], addr);
1836 /* Longword virtual access with protection check (hw_ldl/w) */
1837 tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
1840 /* Quadword virtual access with protection check (hw_ldq/w) */
1841 tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
1844 /* Longword virtual access with alt access mode (hw_ldl/a)*/
1845 gen_helper_set_alt_mode();
1846 gen_helper_st_virt_to_phys(addr, addr);
1847 gen_helper_ldl_raw(cpu_ir[ra], addr);
1848 gen_helper_restore_mode();
1851 /* Quadword virtual access with alt access mode (hw_ldq/a) */
1852 gen_helper_set_alt_mode();
1853 gen_helper_st_virt_to_phys(addr, addr);
1854 gen_helper_ldq_raw(cpu_ir[ra], addr);
1855 gen_helper_restore_mode();
1858 /* Longword virtual access with alternate access mode and
1859 * protection checks (hw_ldl/wa)
1861 gen_helper_set_alt_mode();
1862 gen_helper_ldl_data(cpu_ir[ra], addr);
1863 gen_helper_restore_mode();
1866 /* Quadword virtual access with alternate access mode and
1867 * protection checks (hw_ldq/wa)
1869 gen_helper_set_alt_mode();
1870 gen_helper_ldq_data(cpu_ir[ra], addr);
1871 gen_helper_restore_mode();
1874 tcg_temp_free(addr);
1882 if (!(ctx->amask & AMASK_BWX))
1884 if (likely(rc != 31)) {
1886 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
1888 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
1893 if (!(ctx->amask & AMASK_BWX))
1895 if (likely(rc != 31)) {
1897 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
1899 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
1904 if (!(ctx->amask & AMASK_CIX))
1906 if (likely(rc != 31)) {
1908 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
1910 gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
1915 if (!(ctx->amask & AMASK_MVI))
1922 if (!(ctx->amask & AMASK_CIX))
1924 if (likely(rc != 31)) {
1926 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
1928 gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
1933 if (!(ctx->amask & AMASK_CIX))
1935 if (likely(rc != 31)) {
1937 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
1939 gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
1944 if (!(ctx->amask & AMASK_MVI))
1951 if (!(ctx->amask & AMASK_MVI))
1958 if (!(ctx->amask & AMASK_MVI))
1965 if (!(ctx->amask & AMASK_MVI))
1972 if (!(ctx->amask & AMASK_MVI))
1979 if (!(ctx->amask & AMASK_MVI))
1986 if (!(ctx->amask & AMASK_MVI))
1993 if (!(ctx->amask & AMASK_MVI))
2000 if (!(ctx->amask & AMASK_MVI))
2007 if (!(ctx->amask & AMASK_MVI))
2014 if (!(ctx->amask & AMASK_MVI))
2021 if (!(ctx->amask & AMASK_MVI))
2028 if (!(ctx->amask & AMASK_FIX))
2030 if (likely(rc != 31)) {
2032 tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
2034 tcg_gen_movi_i64(cpu_ir[rc], 0);
2039 if (!(ctx->amask & AMASK_FIX))
2042 TCGv_i32 tmp1 = tcg_temp_new_i32();
2044 gen_helper_s_to_memory(tmp1, cpu_fir[ra]);
2046 TCGv tmp2 = tcg_const_i64(0);
2047 gen_helper_s_to_memory(tmp1, tmp2);
2048 tcg_temp_free(tmp2);
2050 tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1);
2051 tcg_temp_free_i32(tmp1);
2059 /* HW_MTPR (PALcode) */
2060 #if defined (CONFIG_USER_ONLY)
2066 TCGv tmp1 = tcg_const_i32(insn & 0xFF);
2068 gen_helper_mtpr(tmp1, cpu_ir[ra]);
2070 TCGv tmp2 = tcg_const_i64(0);
2071 gen_helper_mtpr(tmp1, tmp2);
2072 tcg_temp_free(tmp2);
2074 tcg_temp_free(tmp1);
2080 /* HW_REI (PALcode) */
2081 #if defined (CONFIG_USER_ONLY)
2088 gen_helper_hw_rei();
2093 tmp = tcg_temp_new();
2094 tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
2096 tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
2097 gen_helper_hw_ret(tmp);
2104 /* HW_ST (PALcode) */
2105 #if defined (CONFIG_USER_ONLY)
2112 addr = tcg_temp_new();
2114 tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
2116 tcg_gen_movi_i64(addr, disp12);
2120 val = tcg_temp_new();
2121 tcg_gen_movi_i64(val, 0);
2123 switch ((insn >> 12) & 0xF) {
2125 /* Longword physical access */
2126 gen_helper_stl_raw(val, addr);
2129 /* Quadword physical access */
2130 gen_helper_stq_raw(val, addr);
2133 /* Longword physical access with lock */
2134 gen_helper_stl_c_raw(val, val, addr);
2137 /* Quadword physical access with lock */
2138 gen_helper_stq_c_raw(val, val, addr);
2141 /* Longword virtual access */
2142 gen_helper_st_virt_to_phys(addr, addr);
2143 gen_helper_stl_raw(val, addr);
2146 /* Quadword virtual access */
2147 gen_helper_st_virt_to_phys(addr, addr);
2148 gen_helper_stq_raw(val, addr);
2169 /* Longword virtual access with alternate access mode */
2170 gen_helper_set_alt_mode();
2171 gen_helper_st_virt_to_phys(addr, addr);
2172 gen_helper_stl_raw(val, addr);
2173 gen_helper_restore_mode();
2176 /* Quadword virtual access with alternate access mode */
2177 gen_helper_set_alt_mode();
2178 gen_helper_st_virt_to_phys(addr, addr);
2179 gen_helper_stl_raw(val, addr);
2180 gen_helper_restore_mode();
2191 tcg_temp_free(addr);
2197 gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
2201 gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
2205 gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
2209 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
2213 gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0);
2217 gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0);
2221 gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0);
2225 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0);
2229 gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
2233 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
2237 gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
2241 gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
2245 gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0);
2249 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0);
2253 gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1);
2257 gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1);
2262 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2263 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2266 case 0x31: /* FBEQ */
2267 case 0x32: /* FBLT */
2268 case 0x33: /* FBLE */
2269 gen_fbcond(ctx, opc, ra, disp16);
2275 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2276 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2279 case 0x35: /* FBNE */
2280 case 0x36: /* FBGE */
2281 case 0x37: /* FBGT */
2282 gen_fbcond(ctx, opc, ra, disp16);
2287 gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
2292 gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
2297 gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
2302 gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
2307 gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
2312 gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
2317 gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
2322 gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
2334 static always_inline void gen_intermediate_code_internal (CPUState *env,
2335 TranslationBlock *tb,
2338 #if defined ALPHA_DEBUG_DISAS
2339 static int insn_count;
2341 DisasContext ctx, *ctxp = &ctx;
2342 target_ulong pc_start;
2344 uint16_t *gen_opc_end;
2352 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2354 ctx.amask = env->amask;
2355 #if defined (CONFIG_USER_ONLY)
2358 ctx.mem_idx = ((env->ps >> 3) & 3);
2359 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2362 max_insns = tb->cflags & CF_COUNT_MASK;
2364 max_insns = CF_COUNT_MASK;
2367 for (ret = 0; ret == 0;) {
2368 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
2369 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
2370 if (bp->pc == ctx.pc) {
2371 gen_excp(&ctx, EXCP_DEBUG, 0);
2377 j = gen_opc_ptr - gen_opc_buf;
2381 gen_opc_instr_start[lj++] = 0;
2383 gen_opc_pc[lj] = ctx.pc;
2384 gen_opc_instr_start[lj] = 1;
2385 gen_opc_icount[lj] = num_insns;
2387 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2389 #if defined ALPHA_DEBUG_DISAS
2391 LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n",
2392 ctx.pc, ctx.mem_idx);
2394 insn = ldl_code(ctx.pc);
2395 #if defined ALPHA_DEBUG_DISAS
2397 LOG_DISAS("opcode %08x %d\n", insn, insn_count);
2401 ret = translate_one(ctxp, insn);
2404 /* if we reach a page boundary or are single stepping, stop
2407 if (env->singlestep_enabled) {
2408 gen_excp(&ctx, EXCP_DEBUG, 0);
2412 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
2415 if (gen_opc_ptr >= gen_opc_end)
2418 if (num_insns >= max_insns)
2425 if (ret != 1 && ret != 3) {
2426 tcg_gen_movi_i64(cpu_pc, ctx.pc);
2428 #if defined (DO_TB_FLUSH)
2429 gen_helper_tb_flush();
2431 if (tb->cflags & CF_LAST_IO)
2433 /* Generate the return instruction */
2435 gen_icount_end(tb, num_insns);
2436 *gen_opc_ptr = INDEX_op_end;
2438 j = gen_opc_ptr - gen_opc_buf;
2441 gen_opc_instr_start[lj++] = 0;
2443 tb->size = ctx.pc - pc_start;
2444 tb->icount = num_insns;
2446 #if defined ALPHA_DEBUG_DISAS
2447 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
2448 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2449 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2450 log_target_disas(pc_start, ctx.pc - pc_start, 1);
2456 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2458 gen_intermediate_code_internal(env, tb, 0);
2461 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2463 gen_intermediate_code_internal(env, tb, 1);
2466 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2471 env = qemu_mallocz(sizeof(CPUAlphaState));
2473 alpha_translate_init();
2475 /* XXX: should not be hardcoded */
2476 env->implver = IMPLVER_2106x;
2478 #if defined (CONFIG_USER_ONLY)
2482 /* Initialize IPR */
2483 hwpcb = env->ipr[IPR_PCBB];
2484 env->ipr[IPR_ASN] = 0;
2485 env->ipr[IPR_ASTEN] = 0;
2486 env->ipr[IPR_ASTSR] = 0;
2487 env->ipr[IPR_DATFX] = 0;
2489 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2490 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2491 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2492 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2493 env->ipr[IPR_FEN] = 0;
2494 env->ipr[IPR_IPL] = 31;
2495 env->ipr[IPR_MCES] = 0;
2496 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2497 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2498 env->ipr[IPR_SISR] = 0;
2499 env->ipr[IPR_VIRBND] = -1ULL;
2504 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2505 unsigned long searched_pc, int pc_pos, void *puc)
2507 env->pc = gen_opc_pc[pc_pos];