2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include "host-utils.h"
31 #include "qemu-common.h"
33 #define DO_SINGLE_STEP
35 #define ALPHA_DEBUG_DISAS
38 typedef struct DisasContext DisasContext;
42 #if !defined (CONFIG_USER_ONLY)
48 /* global register indexes */
50 static TCGv cpu_ir[31];
53 /* dyngen register indexes */
57 static char cpu_reg_names[10*4+21*5];
59 #include "gen-icount.h"
61 static void alpha_translate_init(void)
65 static int done_init = 0;
70 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
74 offsetof(CPUState, t0), "T0");
75 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
76 offsetof(CPUState, t1), "T1");
78 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
79 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
83 for (i = 0; i < 31; i++) {
84 sprintf(p, "ir%d", i);
85 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
86 offsetof(CPUState, ir[i]), p);
87 p += (i < 10) ? 4 : 5;
90 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
91 offsetof(CPUState, pc), "pc");
93 /* register helpers */
95 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
101 static always_inline void gen_op_nop (void)
103 #if defined(GENERATE_NOP)
108 #define GEN32(func, NAME) \
109 static GenOpFunc *NAME ## _table [32] = { \
110 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
111 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
112 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
113 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
114 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
115 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
116 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
117 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
119 static always_inline void func (int n) \
121 NAME ## _table[n](); \
125 /* Special hacks for fir31 */
126 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
127 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
128 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
129 #define gen_op_store_FT0_fir31 gen_op_nop
130 #define gen_op_store_FT1_fir31 gen_op_nop
131 #define gen_op_store_FT2_fir31 gen_op_nop
132 #define gen_op_cmov_fir31 gen_op_nop
133 GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
134 GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
135 GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
136 GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
137 GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
138 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
139 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
141 static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
145 gen_op_load_FT0_fir(firn);
148 gen_op_load_FT1_fir(firn);
151 gen_op_load_FT2_fir(firn);
156 static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
160 gen_op_store_FT0_fir(firn);
163 gen_op_store_FT1_fir(firn);
166 gen_op_store_FT2_fir(firn);
172 #if defined(CONFIG_USER_ONLY)
173 #define OP_LD_TABLE(width) \
174 static GenOpFunc *gen_op_ld##width[] = { \
175 &gen_op_ld##width##_raw, \
177 #define OP_ST_TABLE(width) \
178 static GenOpFunc *gen_op_st##width[] = { \
179 &gen_op_st##width##_raw, \
182 #define OP_LD_TABLE(width) \
183 static GenOpFunc *gen_op_ld##width[] = { \
184 &gen_op_ld##width##_kernel, \
185 &gen_op_ld##width##_executive, \
186 &gen_op_ld##width##_supervisor, \
187 &gen_op_ld##width##_user, \
189 #define OP_ST_TABLE(width) \
190 static GenOpFunc *gen_op_st##width[] = { \
191 &gen_op_st##width##_kernel, \
192 &gen_op_st##width##_executive, \
193 &gen_op_st##width##_supervisor, \
194 &gen_op_st##width##_user, \
198 #define GEN_LD(width) \
199 OP_LD_TABLE(width); \
200 static always_inline void gen_ld##width (DisasContext *ctx) \
202 (*gen_op_ld##width[ctx->mem_idx])(); \
205 #define GEN_ST(width) \
206 OP_ST_TABLE(width); \
207 static always_inline void gen_st##width (DisasContext *ctx) \
209 (*gen_op_st##width[ctx->mem_idx])(); \
227 #if 0 /* currently unused */
238 static always_inline void _gen_op_bcond (DisasContext *ctx)
240 #if 0 // Qemu does not know how to do this...
241 gen_op_bcond(ctx->pc);
243 gen_op_bcond(ctx->pc >> 32, ctx->pc);
247 static always_inline void gen_excp (DisasContext *ctx,
248 int exception, int error_code)
252 tcg_gen_movi_i64(cpu_pc, ctx->pc);
253 tmp1 = tcg_const_i32(exception);
254 tmp2 = tcg_const_i32(error_code);
255 tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);
260 static always_inline void gen_invalid (DisasContext *ctx)
262 gen_excp(ctx, EXCP_OPCDEC, 0);
265 static always_inline void gen_load_mem (DisasContext *ctx,
266 void (*gen_load_op)(DisasContext *ctx),
267 int ra, int rb, int32_t disp16,
270 if (ra == 31 && disp16 == 0) {
275 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
277 tcg_gen_movi_i64(cpu_T[0], disp16);
279 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
282 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
286 static always_inline void gen_store_mem (DisasContext *ctx,
287 void (*gen_store_op)(DisasContext *ctx),
288 int ra, int rb, int32_t disp16,
292 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
294 tcg_gen_movi_i64(cpu_T[0], disp16);
296 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
298 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
300 tcg_gen_movi_i64(cpu_T[1], 0);
301 (*gen_store_op)(ctx);
304 static always_inline void gen_load_fmem (DisasContext *ctx,
305 void (*gen_load_fop)(DisasContext *ctx),
306 int ra, int rb, int32_t disp16)
309 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
311 tcg_gen_movi_i64(cpu_T[0], disp16);
312 (*gen_load_fop)(ctx);
313 gen_store_fir(ctx, ra, 1);
316 static always_inline void gen_store_fmem (DisasContext *ctx,
317 void (*gen_store_fop)(DisasContext *ctx),
318 int ra, int rb, int32_t disp16)
321 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
323 tcg_gen_movi_i64(cpu_T[0], disp16);
324 gen_load_fir(ctx, ra, 1);
325 (*gen_store_fop)(ctx);
328 static always_inline void gen_bcond (DisasContext *ctx,
330 int ra, int32_t disp16, int mask)
334 l1 = gen_new_label();
335 l2 = gen_new_label();
336 if (likely(ra != 31)) {
338 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
339 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
340 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
343 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
345 /* Very uncommon case - Do not bother to optimize. */
346 TCGv tmp = tcg_const_i64(0);
347 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
350 tcg_gen_movi_i64(cpu_pc, ctx->pc);
353 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
357 static always_inline void gen_fbcond (DisasContext *ctx,
358 void (*gen_test_op)(void),
359 int ra, int32_t disp16)
361 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
362 gen_load_fir(ctx, ra, 0);
367 static always_inline void gen_cmov (DisasContext *ctx,
369 int ra, int rb, int rc,
370 int islit, uint8_t lit, int mask)
374 if (unlikely(rc == 31))
377 l1 = gen_new_label();
381 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
382 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
383 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
386 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
388 /* Very uncommon case - Do not bother to optimize. */
389 TCGv tmp = tcg_const_i64(0);
390 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
395 tcg_gen_movi_i64(cpu_ir[rc], lit);
397 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
401 static always_inline void gen_farith2 (DisasContext *ctx,
402 void (*gen_arith_fop)(void),
405 gen_load_fir(ctx, rb, 0);
407 gen_store_fir(ctx, rc, 0);
410 static always_inline void gen_farith3 (DisasContext *ctx,
411 void (*gen_arith_fop)(void),
412 int ra, int rb, int rc)
414 gen_load_fir(ctx, ra, 0);
415 gen_load_fir(ctx, rb, 1);
417 gen_store_fir(ctx, rc, 0);
420 static always_inline void gen_fcmov (DisasContext *ctx,
421 void (*gen_test_fop)(void),
422 int ra, int rb, int rc)
424 gen_load_fir(ctx, ra, 0);
425 gen_load_fir(ctx, rb, 1);
430 static always_inline void gen_fti (DisasContext *ctx,
431 void (*gen_move_fop)(void),
434 gen_load_fir(ctx, rc, 0);
437 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
440 static always_inline void gen_itf (DisasContext *ctx,
441 void (*gen_move_fop)(void),
445 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
447 tcg_gen_movi_i64(cpu_T[0], 0);
449 gen_store_fir(ctx, rc, 0);
452 /* EXTWH, EXTWH, EXTLH, EXTQH */
453 static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
454 int ra, int rb, int rc,
455 int islit, uint8_t lit)
457 if (unlikely(rc == 31))
463 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
465 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
468 tmp1 = tcg_temp_new(TCG_TYPE_I64);
469 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
470 tcg_gen_shli_i64(tmp1, tmp1, 3);
471 tmp2 = tcg_const_i64(64);
472 tcg_gen_sub_i64(tmp1, tmp2, tmp1);
474 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
478 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
480 tcg_gen_movi_i64(cpu_ir[rc], 0);
483 /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
484 static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
485 int ra, int rb, int rc,
486 int islit, uint8_t lit)
488 if (unlikely(rc == 31))
493 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
495 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
496 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
497 tcg_gen_shli_i64(tmp, tmp, 3);
498 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
502 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
504 tcg_gen_movi_i64(cpu_ir[rc], 0);
507 /* Code to call arith3 helpers */
508 static always_inline void gen_arith3_helper(void *helper,
509 int ra, int rb, int rc,
510 int islit, uint8_t lit)
512 if (unlikely(rc == 31))
517 TCGv tmp = tcg_const_i64(lit);
518 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);
521 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
523 TCGv tmp1 = tcg_const_i64(0);
525 TCGv tmp2 = tcg_const_i64(lit);
526 tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, tmp2);
529 tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, cpu_ir[rb]);
534 static always_inline void gen_cmp(TCGCond cond,
535 int ra, int rb, int rc,
536 int islit, uint8_t lit)
541 if (unlikely(rc == 31))
544 l1 = gen_new_label();
545 l2 = gen_new_label();
548 tmp = tcg_temp_new(TCG_TYPE_I64);
549 tcg_gen_mov_i64(tmp, cpu_ir[ra]);
551 tmp = tcg_const_i64(0);
553 tcg_gen_brcondi_i64(cond, tmp, lit, l1);
555 tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
557 tcg_gen_movi_i64(cpu_ir[rc], 0);
560 tcg_gen_movi_i64(cpu_ir[rc], 1);
564 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
567 int32_t disp21, disp16, disp12;
569 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
573 /* Decode all instruction fields */
575 ra = (insn >> 21) & 0x1F;
576 rb = (insn >> 16) & 0x1F;
578 sbz = (insn >> 13) & 0x07;
579 islit = (insn >> 12) & 1;
580 if (rb == 31 && !islit) {
584 lit = (insn >> 13) & 0xFF;
585 palcode = insn & 0x03FFFFFF;
586 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
587 disp16 = (int16_t)(insn & 0x0000FFFF);
588 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
589 fn16 = insn & 0x0000FFFF;
590 fn11 = (insn >> 5) & 0x000007FF;
592 fn7 = (insn >> 5) & 0x0000007F;
593 fn2 = (insn >> 5) & 0x00000003;
595 #if defined ALPHA_DEBUG_DISAS
596 if (logfile != NULL) {
597 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
598 opc, ra, rb, rc, disp16);
604 if (palcode >= 0x80 && palcode < 0xC0) {
605 /* Unprivileged PAL call */
606 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
607 #if !defined (CONFIG_USER_ONLY)
608 } else if (palcode < 0x40) {
609 /* Privileged PAL code */
610 if (ctx->mem_idx & 1)
613 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
616 /* Invalid PAL call */
644 if (likely(ra != 31)) {
646 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
648 tcg_gen_movi_i64(cpu_ir[ra], disp16);
653 if (likely(ra != 31)) {
655 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
657 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
662 if (!(ctx->amask & AMASK_BWX))
664 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
668 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
672 if (!(ctx->amask & AMASK_BWX))
674 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
678 if (!(ctx->amask & AMASK_BWX))
680 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
684 if (!(ctx->amask & AMASK_BWX))
686 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
690 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
696 if (likely(rc != 31)) {
699 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
700 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
702 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
703 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
707 tcg_gen_movi_i64(cpu_ir[rc], lit);
709 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
715 if (likely(rc != 31)) {
717 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
718 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
720 tcg_gen_addi_i64(tmp, tmp, lit);
722 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
723 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
727 tcg_gen_movi_i64(cpu_ir[rc], lit);
729 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
735 if (likely(rc != 31)) {
738 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
740 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
741 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
744 tcg_gen_movi_i64(cpu_ir[rc], -lit);
746 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
747 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
753 if (likely(rc != 31)) {
755 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
756 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
758 tcg_gen_subi_i64(tmp, tmp, lit);
760 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
761 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
765 tcg_gen_movi_i64(cpu_ir[rc], -lit);
767 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
768 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
775 gen_arith3_helper(helper_cmpbge, ra, rb, rc, islit, lit);
779 if (likely(rc != 31)) {
781 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
782 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
784 tcg_gen_addi_i64(tmp, tmp, lit);
786 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
787 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
791 tcg_gen_movi_i64(cpu_ir[rc], lit);
793 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
799 if (likely(rc != 31)) {
801 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
802 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
804 tcg_gen_subi_i64(tmp, tmp, lit);
806 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
807 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
811 tcg_gen_movi_i64(cpu_ir[rc], -lit);
813 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
814 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
821 gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
825 if (likely(rc != 31)) {
828 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
830 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
833 tcg_gen_movi_i64(cpu_ir[rc], lit);
835 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
841 if (likely(rc != 31)) {
843 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
844 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
846 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
848 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
852 tcg_gen_movi_i64(cpu_ir[rc], lit);
854 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
860 if (likely(rc != 31)) {
863 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
865 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
868 tcg_gen_movi_i64(cpu_ir[rc], -lit);
870 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
876 if (likely(rc != 31)) {
878 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
879 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
881 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
883 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
887 tcg_gen_movi_i64(cpu_ir[rc], -lit);
889 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
895 gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
899 if (likely(rc != 31)) {
901 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
902 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
904 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
906 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
910 tcg_gen_movi_i64(cpu_ir[rc], lit);
912 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
918 if (likely(rc != 31)) {
920 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
921 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
923 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
925 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
929 tcg_gen_movi_i64(cpu_ir[rc], -lit);
931 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
937 gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
941 gen_arith3_helper(helper_addlv, ra, rb, rc, islit, lit);
945 gen_arith3_helper(helper_sublv, ra, rb, rc, islit, lit);
949 gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
953 gen_arith3_helper(helper_addqv, ra, rb, rc, islit, lit);
957 gen_arith3_helper(helper_subqv, ra, rb, rc, islit, lit);
961 gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
971 if (likely(rc != 31)) {
973 tcg_gen_movi_i64(cpu_ir[rc], 0);
975 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
977 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
982 if (likely(rc != 31)) {
985 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
987 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
988 tcg_gen_not_i64(tmp, cpu_ir[rb]);
989 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
993 tcg_gen_movi_i64(cpu_ir[rc], 0);
998 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
1002 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
1006 if (likely(rc != 31)) {
1009 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1011 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1014 tcg_gen_movi_i64(cpu_ir[rc], lit);
1016 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1022 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
1026 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
1030 if (likely(rc != 31)) {
1033 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1035 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1036 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1037 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1042 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1044 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1050 if (likely(rc != 31)) {
1053 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1055 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1058 tcg_gen_movi_i64(cpu_ir[rc], lit);
1060 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1066 gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
1070 gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
1074 if (likely(rc != 31)) {
1077 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1079 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1080 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1081 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1086 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1088 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1094 if (likely(rc != 31)) {
1096 tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit));
1098 tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]);
1103 gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
1107 gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
1112 tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
1122 gen_arith3_helper(helper_mskbl, ra, rb, rc, islit, lit);
1126 gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit);
1130 gen_arith3_helper(helper_insbl, ra, rb, rc, islit, lit);
1134 gen_arith3_helper(helper_mskwl, ra, rb, rc, islit, lit);
1138 gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1142 gen_arith3_helper(helper_inswl, ra, rb, rc, islit, lit);
1146 gen_arith3_helper(helper_mskll, ra, rb, rc, islit, lit);
1150 gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
1154 gen_arith3_helper(helper_insll, ra, rb, rc, islit, lit);
1158 gen_arith3_helper(helper_zap, ra, rb, rc, islit, lit);
1162 gen_arith3_helper(helper_zapnot, ra, rb, rc, islit, lit);
1166 gen_arith3_helper(helper_mskql, ra, rb, rc, islit, lit);
1170 if (likely(rc != 31)) {
1173 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1175 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1176 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1177 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1178 tcg_temp_free(shift);
1181 tcg_gen_movi_i64(cpu_ir[rc], 0);
1186 gen_ext_l(NULL, ra, rb, rc, islit, lit);
1190 if (likely(rc != 31)) {
1193 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1195 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1196 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1197 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1198 tcg_temp_free(shift);
1201 tcg_gen_movi_i64(cpu_ir[rc], 0);
1206 gen_arith3_helper(helper_insql, ra, rb, rc, islit, lit);
1210 if (likely(rc != 31)) {
1213 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1215 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1216 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1217 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1218 tcg_temp_free(shift);
1221 tcg_gen_movi_i64(cpu_ir[rc], 0);
1226 gen_arith3_helper(helper_mskwh, ra, rb, rc, islit, lit);
1230 gen_arith3_helper(helper_inswh, ra, rb, rc, islit, lit);
1234 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1238 gen_arith3_helper(helper_msklh, ra, rb, rc, islit, lit);
1242 gen_arith3_helper(helper_inslh, ra, rb, rc, islit, lit);
1246 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1250 gen_arith3_helper(helper_mskqh, ra, rb, rc, islit, lit);
1254 gen_arith3_helper(helper_insqh, ra, rb, rc, islit, lit);
1258 gen_ext_h(NULL, ra, rb, rc, islit, lit);
1268 if (likely(rc != 31)) {
1270 tcg_gen_movi_i64(cpu_ir[rc], 0);
1273 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1275 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1276 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1282 if (likely(rc != 31)) {
1284 tcg_gen_movi_i64(cpu_ir[rc], 0);
1286 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1288 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1293 gen_arith3_helper(helper_umulh, ra, rb, rc, islit, lit);
1297 gen_arith3_helper(helper_mullv, ra, rb, rc, islit, lit);
1301 gen_arith3_helper(helper_mulqv, ra, rb, rc, islit, lit);
1308 switch (fpfn) { /* f11 & 0x3F */
1311 if (!(ctx->amask & AMASK_FIX))
1313 gen_itf(ctx, &gen_op_itofs, ra, rc);
1317 if (!(ctx->amask & AMASK_FIX))
1319 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1323 if (!(ctx->amask & AMASK_FIX))
1325 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1329 if (!(ctx->amask & AMASK_FIX))
1332 gen_itf(ctx, &gen_op_itoff, ra, rc);
1339 if (!(ctx->amask & AMASK_FIX))
1341 gen_itf(ctx, &gen_op_itoft, ra, rc);
1345 if (!(ctx->amask & AMASK_FIX))
1347 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1351 if (!(ctx->amask & AMASK_FIX))
1353 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1360 /* VAX floating point */
1361 /* XXX: rounding mode and trap are ignored (!) */
1362 switch (fpfn) { /* f11 & 0x3F */
1365 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1369 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1373 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1377 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1382 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1389 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1393 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1397 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1401 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1405 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1409 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1413 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1417 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1422 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1429 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1433 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1437 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1444 /* IEEE floating-point */
1445 /* XXX: rounding mode and traps are ignored (!) */
1446 switch (fpfn) { /* f11 & 0x3F */
1449 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1453 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1457 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1461 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1465 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1469 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1473 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1477 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1481 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1485 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1489 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1493 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1496 /* XXX: incorrect */
1497 if (fn11 == 0x2AC) {
1499 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1502 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1507 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1511 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1515 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1525 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1530 if (ra == 31 && rc == 31) {
1535 gen_load_fir(ctx, rb, 0);
1536 gen_store_fir(ctx, rc, 0);
1539 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1544 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1548 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1552 gen_load_fir(ctx, ra, 0);
1553 gen_op_store_fpcr();
1558 gen_store_fir(ctx, ra, 0);
1562 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1566 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1570 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1574 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1578 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1582 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1586 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1590 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1594 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1601 switch ((uint16_t)disp16) {
1604 /* No-op. Just exit from the current tb */
1609 /* No-op. Just exit from the current tb */
1631 tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
1636 tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]);
1640 /* XXX: TODO: evict tb cache at address rb */
1650 tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]);
1661 /* HW_MFPR (PALcode) */
1662 #if defined (CONFIG_USER_ONLY)
1667 gen_op_mfpr(insn & 0xFF);
1669 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1674 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1676 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1678 tcg_gen_movi_i64(cpu_pc, 0);
1679 /* Those four jumps only differ by the branch prediction hint */
1697 /* HW_LD (PALcode) */
1698 #if defined (CONFIG_USER_ONLY)
1704 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1706 tcg_gen_movi_i64(cpu_T[0], 0);
1707 tcg_gen_movi_i64(cpu_T[1], disp12);
1708 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1709 switch ((insn >> 12) & 0xF) {
1711 /* Longword physical access */
1715 /* Quadword physical access */
1719 /* Longword physical access with lock */
1723 /* Quadword physical access with lock */
1727 /* Longword virtual PTE fetch */
1728 gen_op_ldl_kernel();
1731 /* Quadword virtual PTE fetch */
1732 gen_op_ldq_kernel();
1741 /* Longword virtual access */
1742 gen_op_ld_phys_to_virt();
1746 /* Quadword virtual access */
1747 gen_op_ld_phys_to_virt();
1751 /* Longword virtual access with protection check */
1755 /* Quadword virtual access with protection check */
1759 /* Longword virtual access with altenate access mode */
1760 gen_op_set_alt_mode();
1761 gen_op_ld_phys_to_virt();
1763 gen_op_restore_mode();
1766 /* Quadword virtual access with altenate access mode */
1767 gen_op_set_alt_mode();
1768 gen_op_ld_phys_to_virt();
1770 gen_op_restore_mode();
1773 /* Longword virtual access with alternate access mode and
1776 gen_op_set_alt_mode();
1778 gen_op_restore_mode();
1781 /* Quadword virtual access with alternate access mode and
1784 gen_op_set_alt_mode();
1786 gen_op_restore_mode();
1790 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
1797 if (!(ctx->amask & AMASK_BWX))
1799 if (likely(rc != 31)) {
1801 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
1803 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
1808 if (!(ctx->amask & AMASK_BWX))
1810 if (likely(rc != 31)) {
1812 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
1814 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
1819 if (!(ctx->amask & AMASK_CIX))
1821 if (likely(rc != 31)) {
1823 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
1825 tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]);
1830 if (!(ctx->amask & AMASK_MVI))
1837 if (!(ctx->amask & AMASK_CIX))
1839 if (likely(rc != 31)) {
1841 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
1843 tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]);
1848 if (!(ctx->amask & AMASK_CIX))
1850 if (likely(rc != 31)) {
1852 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
1854 tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]);
1859 if (!(ctx->amask & AMASK_MVI))
1866 if (!(ctx->amask & AMASK_MVI))
1873 if (!(ctx->amask & AMASK_MVI))
1880 if (!(ctx->amask & AMASK_MVI))
1887 if (!(ctx->amask & AMASK_MVI))
1894 if (!(ctx->amask & AMASK_MVI))
1901 if (!(ctx->amask & AMASK_MVI))
1908 if (!(ctx->amask & AMASK_MVI))
1915 if (!(ctx->amask & AMASK_MVI))
1922 if (!(ctx->amask & AMASK_MVI))
1929 if (!(ctx->amask & AMASK_MVI))
1936 if (!(ctx->amask & AMASK_MVI))
1943 if (!(ctx->amask & AMASK_FIX))
1945 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1949 if (!(ctx->amask & AMASK_FIX))
1951 gen_fti(ctx, &gen_op_ftois, ra, rb);
1958 /* HW_MTPR (PALcode) */
1959 #if defined (CONFIG_USER_ONLY)
1965 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
1967 tcg_gen_movi_i64(cpu_T[0], 0);
1968 gen_op_mtpr(insn & 0xFF);
1973 /* HW_REI (PALcode) */
1974 #if defined (CONFIG_USER_ONLY)
1984 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1986 tcg_gen_movi_i64(cpu_T[0], 0);
1987 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
1988 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1995 /* HW_ST (PALcode) */
1996 #if defined (CONFIG_USER_ONLY)
2002 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
2004 tcg_gen_movi_i64(cpu_T[0], disp12);
2006 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
2008 tcg_gen_movi_i64(cpu_T[1], 0);
2009 switch ((insn >> 12) & 0xF) {
2011 /* Longword physical access */
2015 /* Quadword physical access */
2019 /* Longword physical access with lock */
2023 /* Quadword physical access with lock */
2027 /* Longword virtual access */
2028 gen_op_st_phys_to_virt();
2032 /* Quadword virtual access */
2033 gen_op_st_phys_to_virt();
2055 /* Longword virtual access with alternate access mode */
2056 gen_op_set_alt_mode();
2057 gen_op_st_phys_to_virt();
2059 gen_op_restore_mode();
2062 /* Quadword virtual access with alternate access mode */
2063 gen_op_set_alt_mode();
2064 gen_op_st_phys_to_virt();
2066 gen_op_restore_mode();
2081 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
2089 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
2096 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
2100 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
2105 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
2113 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
2120 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
2124 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
2128 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
2132 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
2136 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
2140 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
2144 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
2148 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
2152 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
2156 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
2161 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2162 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2167 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
2172 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
2177 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
2183 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2184 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2189 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
2194 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
2199 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
2204 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
2209 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
2214 gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
2219 gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
2224 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
2229 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
2234 gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
2239 gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
2251 static always_inline void gen_intermediate_code_internal (CPUState *env,
2252 TranslationBlock *tb,
2255 #if defined ALPHA_DEBUG_DISAS
2256 static int insn_count;
2258 DisasContext ctx, *ctxp = &ctx;
2259 target_ulong pc_start;
2261 uint16_t *gen_opc_end;
2268 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2270 ctx.amask = env->amask;
2271 #if defined (CONFIG_USER_ONLY)
2274 ctx.mem_idx = ((env->ps >> 3) & 3);
2275 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2278 max_insns = tb->cflags & CF_COUNT_MASK;
2280 max_insns = CF_COUNT_MASK;
2283 for (ret = 0; ret == 0;) {
2284 if (env->nb_breakpoints > 0) {
2285 for(j = 0; j < env->nb_breakpoints; j++) {
2286 if (env->breakpoints[j] == ctx.pc) {
2287 gen_excp(&ctx, EXCP_DEBUG, 0);
2293 j = gen_opc_ptr - gen_opc_buf;
2297 gen_opc_instr_start[lj++] = 0;
2298 gen_opc_pc[lj] = ctx.pc;
2299 gen_opc_instr_start[lj] = 1;
2300 gen_opc_icount[lj] = num_insns;
2303 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2305 #if defined ALPHA_DEBUG_DISAS
2307 if (logfile != NULL) {
2308 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2309 ctx.pc, ctx.mem_idx);
2312 insn = ldl_code(ctx.pc);
2313 #if defined ALPHA_DEBUG_DISAS
2315 if (logfile != NULL) {
2316 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2321 ret = translate_one(ctxp, insn);
2324 /* if we reach a page boundary or are single stepping, stop
2327 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2328 (env->singlestep_enabled) ||
2329 num_insns >= max_insns) {
2332 #if defined (DO_SINGLE_STEP)
2336 if (ret != 1 && ret != 3) {
2337 tcg_gen_movi_i64(cpu_pc, ctx.pc);
2339 #if defined (DO_TB_FLUSH)
2340 tcg_gen_helper_0_0(helper_tb_flush);
2342 if (tb->cflags & CF_LAST_IO)
2344 /* Generate the return instruction */
2346 gen_icount_end(tb, num_insns);
2347 *gen_opc_ptr = INDEX_op_end;
2349 j = gen_opc_ptr - gen_opc_buf;
2352 gen_opc_instr_start[lj++] = 0;
2354 tb->size = ctx.pc - pc_start;
2355 tb->icount = num_insns;
2357 #if defined ALPHA_DEBUG_DISAS
2358 if (loglevel & CPU_LOG_TB_CPU) {
2359 cpu_dump_state(env, logfile, fprintf, 0);
2361 if (loglevel & CPU_LOG_TB_IN_ASM) {
2362 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2363 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2364 fprintf(logfile, "\n");
2369 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2371 gen_intermediate_code_internal(env, tb, 0);
2374 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2376 gen_intermediate_code_internal(env, tb, 1);
2379 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2384 env = qemu_mallocz(sizeof(CPUAlphaState));
2388 alpha_translate_init();
2390 /* XXX: should not be hardcoded */
2391 env->implver = IMPLVER_2106x;
2393 #if defined (CONFIG_USER_ONLY)
2397 /* Initialize IPR */
2398 hwpcb = env->ipr[IPR_PCBB];
2399 env->ipr[IPR_ASN] = 0;
2400 env->ipr[IPR_ASTEN] = 0;
2401 env->ipr[IPR_ASTSR] = 0;
2402 env->ipr[IPR_DATFX] = 0;
2404 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2405 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2406 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2407 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2408 env->ipr[IPR_FEN] = 0;
2409 env->ipr[IPR_IPL] = 31;
2410 env->ipr[IPR_MCES] = 0;
2411 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2412 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2413 env->ipr[IPR_SISR] = 0;
2414 env->ipr[IPR_VIRBND] = -1ULL;
2419 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2420 unsigned long searched_pc, int pc_pos, void *puc)
2422 env->pc = gen_opc_pc[pc_pos];