2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include "qemu-common.h"
31 #define DO_SINGLE_STEP
33 #define ALPHA_DEBUG_DISAS
36 typedef struct DisasContext DisasContext;
40 #if !defined (CONFIG_USER_ONLY)
48 #include "gen-icount.h"
50 static void alpha_translate_init(void)
52 static int done_init = 0;
55 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
59 static always_inline void gen_op_nop (void)
61 #if defined(GENERATE_NOP)
66 #define GEN32(func, NAME) \
67 static GenOpFunc *NAME ## _table [32] = { \
68 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
69 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
70 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
71 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
72 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
73 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
74 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
75 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77 static always_inline void func (int n) \
79 NAME ## _table[n](); \
83 /* Special hacks for ir31 */
84 #define gen_op_load_T0_ir31 gen_op_reset_T0
85 #define gen_op_load_T1_ir31 gen_op_reset_T1
86 #define gen_op_load_T2_ir31 gen_op_reset_T2
87 #define gen_op_store_T0_ir31 gen_op_nop
88 #define gen_op_store_T1_ir31 gen_op_nop
89 #define gen_op_store_T2_ir31 gen_op_nop
90 #define gen_op_cmov_ir31 gen_op_nop
91 GEN32(gen_op_load_T0_ir, gen_op_load_T0_ir);
92 GEN32(gen_op_load_T1_ir, gen_op_load_T1_ir);
93 GEN32(gen_op_load_T2_ir, gen_op_load_T2_ir);
94 GEN32(gen_op_store_T0_ir, gen_op_store_T0_ir);
95 GEN32(gen_op_store_T1_ir, gen_op_store_T1_ir);
96 GEN32(gen_op_store_T2_ir, gen_op_store_T2_ir);
97 GEN32(gen_op_cmov_ir, gen_op_cmov_ir);
99 static always_inline void gen_load_ir (DisasContext *ctx, int irn, int Tn)
103 gen_op_load_T0_ir(irn);
106 gen_op_load_T1_ir(irn);
109 gen_op_load_T2_ir(irn);
114 static always_inline void gen_store_ir (DisasContext *ctx, int irn, int Tn)
118 gen_op_store_T0_ir(irn);
121 gen_op_store_T1_ir(irn);
124 gen_op_store_T2_ir(irn);
130 /* Special hacks for fir31 */
131 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
132 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
133 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
134 #define gen_op_store_FT0_fir31 gen_op_nop
135 #define gen_op_store_FT1_fir31 gen_op_nop
136 #define gen_op_store_FT2_fir31 gen_op_nop
137 #define gen_op_cmov_fir31 gen_op_nop
138 GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
139 GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
140 GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
141 GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
142 GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
143 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
144 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
146 static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
150 gen_op_load_FT0_fir(firn);
153 gen_op_load_FT1_fir(firn);
156 gen_op_load_FT2_fir(firn);
161 static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
165 gen_op_store_FT0_fir(firn);
168 gen_op_store_FT1_fir(firn);
171 gen_op_store_FT2_fir(firn);
177 #if defined(CONFIG_USER_ONLY)
178 #define OP_LD_TABLE(width) \
179 static GenOpFunc *gen_op_ld##width[] = { \
180 &gen_op_ld##width##_raw, \
182 #define OP_ST_TABLE(width) \
183 static GenOpFunc *gen_op_st##width[] = { \
184 &gen_op_st##width##_raw, \
187 #define OP_LD_TABLE(width) \
188 static GenOpFunc *gen_op_ld##width[] = { \
189 &gen_op_ld##width##_kernel, \
190 &gen_op_ld##width##_executive, \
191 &gen_op_ld##width##_supervisor, \
192 &gen_op_ld##width##_user, \
194 #define OP_ST_TABLE(width) \
195 static GenOpFunc *gen_op_st##width[] = { \
196 &gen_op_st##width##_kernel, \
197 &gen_op_st##width##_executive, \
198 &gen_op_st##width##_supervisor, \
199 &gen_op_st##width##_user, \
203 #define GEN_LD(width) \
204 OP_LD_TABLE(width); \
205 static always_inline void gen_ld##width (DisasContext *ctx) \
207 (*gen_op_ld##width[ctx->mem_idx])(); \
210 #define GEN_ST(width) \
211 OP_ST_TABLE(width); \
212 static always_inline void gen_st##width (DisasContext *ctx) \
214 (*gen_op_st##width[ctx->mem_idx])(); \
232 #if 0 /* currently unused */
243 #if defined(__i386__) || defined(__x86_64__)
244 static always_inline void gen_op_set_s16_T0 (int16_t imm)
246 gen_op_set_s32_T0((int32_t)imm);
249 static always_inline void gen_op_set_s16_T1 (int16_t imm)
251 gen_op_set_s32_T1((int32_t)imm);
254 static always_inline void gen_op_set_u16_T0 (uint16_t imm)
256 gen_op_set_s32_T0((uint32_t)imm);
259 static always_inline void gen_op_set_u16_T1 (uint16_t imm)
261 gen_op_set_s32_T1((uint32_t)imm);
265 static always_inline void gen_set_sT0 (DisasContext *ctx, int64_t imm)
277 gen_op_set_s16_T0(imm16);
280 gen_op_set_s32_T0(imm32);
283 #if 0 // Qemu does not know how to do this...
284 gen_op_set_64_T0(imm);
286 gen_op_set_64_T0(imm >> 32, imm);
291 static always_inline void gen_set_sT1 (DisasContext *ctx, int64_t imm)
303 gen_op_set_s16_T1(imm16);
306 gen_op_set_s32_T1(imm32);
309 #if 0 // Qemu does not know how to do this...
310 gen_op_set_64_T1(imm);
312 gen_op_set_64_T1(imm >> 32, imm);
317 static always_inline void gen_set_uT0 (DisasContext *ctx, uint64_t imm)
324 gen_op_set_u16_T0(imm);
326 gen_op_set_u32_T0(imm);
329 #if 0 // Qemu does not know how to do this...
330 gen_op_set_64_T0(imm);
332 gen_op_set_64_T0(imm >> 32, imm);
337 static always_inline void gen_set_uT1 (DisasContext *ctx, uint64_t imm)
344 gen_op_set_u16_T1(imm);
346 gen_op_set_u32_T1(imm);
349 #if 0 // Qemu does not know how to do this...
350 gen_op_set_64_T1(imm);
352 gen_op_set_64_T1(imm >> 32, imm);
357 static always_inline void gen_update_pc (DisasContext *ctx)
359 if (!(ctx->pc >> 32)) {
360 gen_op_update_pc32(ctx->pc);
362 #if 0 // Qemu does not know how to do this...
363 gen_op_update_pc(ctx->pc);
365 gen_op_update_pc(ctx->pc >> 32, ctx->pc);
370 static always_inline void _gen_op_bcond (DisasContext *ctx)
372 #if 0 // Qemu does not know how to do this...
373 gen_op_bcond(ctx->pc);
375 gen_op_bcond(ctx->pc >> 32, ctx->pc);
379 static always_inline void gen_excp (DisasContext *ctx,
380 int exception, int error_code)
383 gen_op_excp(exception, error_code);
386 static always_inline void gen_invalid (DisasContext *ctx)
388 gen_excp(ctx, EXCP_OPCDEC, 0);
391 static always_inline void gen_load_mem (DisasContext *ctx,
392 void (*gen_load_op)(DisasContext *ctx),
393 int ra, int rb, int32_t disp16,
396 if (ra == 31 && disp16 == 0) {
400 gen_load_ir(ctx, rb, 0);
402 gen_set_sT1(ctx, disp16);
408 gen_store_ir(ctx, ra, 1);
412 static always_inline void gen_store_mem (DisasContext *ctx,
413 void (*gen_store_op)(DisasContext *ctx),
414 int ra, int rb, int32_t disp16,
417 gen_load_ir(ctx, rb, 0);
419 gen_set_sT1(ctx, disp16);
424 gen_load_ir(ctx, ra, 1);
425 (*gen_store_op)(ctx);
428 static always_inline void gen_load_fmem (DisasContext *ctx,
429 void (*gen_load_fop)(DisasContext *ctx),
430 int ra, int rb, int32_t disp16)
432 gen_load_ir(ctx, rb, 0);
434 gen_set_sT1(ctx, disp16);
437 (*gen_load_fop)(ctx);
438 gen_store_fir(ctx, ra, 1);
441 static always_inline void gen_store_fmem (DisasContext *ctx,
442 void (*gen_store_fop)(DisasContext *ctx),
443 int ra, int rb, int32_t disp16)
445 gen_load_ir(ctx, rb, 0);
447 gen_set_sT1(ctx, disp16);
450 gen_load_fir(ctx, ra, 1);
451 (*gen_store_fop)(ctx);
454 static always_inline void gen_bcond (DisasContext *ctx,
455 void (*gen_test_op)(void),
456 int ra, int32_t disp16)
459 gen_set_uT0(ctx, ctx->pc);
460 gen_set_sT1(ctx, disp16 << 2);
463 gen_set_uT1(ctx, ctx->pc);
465 gen_load_ir(ctx, ra, 0);
470 static always_inline void gen_fbcond (DisasContext *ctx,
471 void (*gen_test_op)(void),
472 int ra, int32_t disp16)
475 gen_set_uT0(ctx, ctx->pc);
476 gen_set_sT1(ctx, disp16 << 2);
479 gen_set_uT1(ctx, ctx->pc);
481 gen_load_fir(ctx, ra, 0);
486 static always_inline void gen_arith2 (DisasContext *ctx,
487 void (*gen_arith_op)(void),
488 int rb, int rc, int islit, int8_t lit)
491 gen_set_sT0(ctx, lit);
493 gen_load_ir(ctx, rb, 0);
495 gen_store_ir(ctx, rc, 0);
498 static always_inline void gen_arith3 (DisasContext *ctx,
499 void (*gen_arith_op)(void),
500 int ra, int rb, int rc,
501 int islit, int8_t lit)
503 gen_load_ir(ctx, ra, 0);
505 gen_set_sT1(ctx, lit);
507 gen_load_ir(ctx, rb, 1);
509 gen_store_ir(ctx, rc, 0);
512 static always_inline void gen_cmov (DisasContext *ctx,
513 void (*gen_test_op)(void),
514 int ra, int rb, int rc,
515 int islit, int8_t lit)
517 gen_load_ir(ctx, ra, 1);
519 gen_set_sT0(ctx, lit);
521 gen_load_ir(ctx, rb, 0);
526 static always_inline void gen_farith2 (DisasContext *ctx,
527 void (*gen_arith_fop)(void),
530 gen_load_fir(ctx, rb, 0);
532 gen_store_fir(ctx, rc, 0);
535 static always_inline void gen_farith3 (DisasContext *ctx,
536 void (*gen_arith_fop)(void),
537 int ra, int rb, int rc)
539 gen_load_fir(ctx, ra, 0);
540 gen_load_fir(ctx, rb, 1);
542 gen_store_fir(ctx, rc, 0);
545 static always_inline void gen_fcmov (DisasContext *ctx,
546 void (*gen_test_fop)(void),
547 int ra, int rb, int rc)
549 gen_load_fir(ctx, ra, 0);
550 gen_load_fir(ctx, rb, 1);
555 static always_inline void gen_fti (DisasContext *ctx,
556 void (*gen_move_fop)(void),
559 gen_load_fir(ctx, rc, 0);
561 gen_store_ir(ctx, ra, 0);
564 static always_inline void gen_itf (DisasContext *ctx,
565 void (*gen_move_fop)(void),
568 gen_load_ir(ctx, ra, 0);
570 gen_store_fir(ctx, rc, 0);
573 static always_inline void gen_s4addl (void)
579 static always_inline void gen_s4subl (void)
585 static always_inline void gen_s8addl (void)
591 static always_inline void gen_s8subl (void)
597 static always_inline void gen_s4addq (void)
603 static always_inline void gen_s4subq (void)
609 static always_inline void gen_s8addq (void)
615 static always_inline void gen_s8subq (void)
621 static always_inline void gen_amask (void)
627 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
630 int32_t disp21, disp16, disp12;
632 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
636 /* Decode all instruction fields */
638 ra = (insn >> 21) & 0x1F;
639 rb = (insn >> 16) & 0x1F;
641 sbz = (insn >> 13) & 0x07;
642 islit = (insn >> 12) & 1;
643 lit = (insn >> 13) & 0xFF;
644 palcode = insn & 0x03FFFFFF;
645 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
646 disp16 = (int16_t)(insn & 0x0000FFFF);
647 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
648 fn16 = insn & 0x0000FFFF;
649 fn11 = (insn >> 5) & 0x000007FF;
651 fn7 = (insn >> 5) & 0x0000007F;
652 fn2 = (insn >> 5) & 0x00000003;
654 #if defined ALPHA_DEBUG_DISAS
655 if (logfile != NULL) {
656 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
657 opc, ra, rb, rc, disp16);
663 if (palcode >= 0x80 && palcode < 0xC0) {
664 /* Unprivileged PAL call */
665 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
666 #if !defined (CONFIG_USER_ONLY)
667 } else if (palcode < 0x40) {
668 /* Privileged PAL code */
669 if (ctx->mem_idx & 1)
672 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
675 /* Invalid PAL call */
703 gen_load_ir(ctx, rb, 0);
704 gen_set_sT1(ctx, disp16);
706 gen_store_ir(ctx, ra, 0);
710 gen_load_ir(ctx, rb, 0);
711 gen_set_sT1(ctx, disp16 << 16);
713 gen_store_ir(ctx, ra, 0);
717 if (!(ctx->amask & AMASK_BWX))
719 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
723 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
727 if (!(ctx->amask & AMASK_BWX))
729 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
733 if (!(ctx->amask & AMASK_BWX))
735 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
739 if (!(ctx->amask & AMASK_BWX))
741 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
745 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
751 gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit);
755 gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit);
759 gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit);
763 gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit);
767 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
771 gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit);
775 gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit);
779 gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
783 gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit);
787 gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit);
791 gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit);
795 gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit);
799 gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
803 gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit);
807 gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit);
811 gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
815 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
819 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
823 gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
827 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
831 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
835 gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
845 gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit);
849 gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit);
853 gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit);
857 gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit);
861 if (ra == rb || ra == 31 || rb == 31) {
862 if (ra == 31 && rc == 31) {
867 gen_load_ir(ctx, rb, 0);
868 gen_store_ir(ctx, rc, 0);
871 gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit);
876 gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit);
880 gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit);
884 gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit);
888 gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit);
892 gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit);
896 gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit);
900 gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit);
904 gen_arith2(ctx, &gen_amask, rb, rc, islit, lit);
908 gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit);
912 gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit);
916 gen_op_load_implver();
917 gen_store_ir(ctx, rc, 0);
927 gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit);
931 gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit);
935 gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit);
939 gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit);
943 gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit);
947 gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit);
951 gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit);
955 gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit);
959 gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit);
963 gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit);
967 gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit);
971 gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit);
975 gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit);
979 gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit);
983 gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit);
987 gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit);
991 gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit);
995 gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit);
999 gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit);
1003 gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit);
1007 gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit);
1011 gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit);
1015 gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit);
1019 gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit);
1023 gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit);
1027 gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit);
1037 gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit);
1041 gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit);
1045 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
1049 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
1053 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
1060 switch (fpfn) { /* f11 & 0x3F */
1063 if (!(ctx->amask & AMASK_FIX))
1065 gen_itf(ctx, &gen_op_itofs, ra, rc);
1069 if (!(ctx->amask & AMASK_FIX))
1071 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1075 if (!(ctx->amask & AMASK_FIX))
1077 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1081 if (!(ctx->amask & AMASK_FIX))
1084 gen_itf(ctx, &gen_op_itoff, ra, rc);
1091 if (!(ctx->amask & AMASK_FIX))
1093 gen_itf(ctx, &gen_op_itoft, ra, rc);
1097 if (!(ctx->amask & AMASK_FIX))
1099 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1103 if (!(ctx->amask & AMASK_FIX))
1105 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1112 /* VAX floating point */
1113 /* XXX: rounding mode and trap are ignored (!) */
1114 switch (fpfn) { /* f11 & 0x3F */
1117 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1121 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1125 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1129 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1134 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1141 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1145 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1149 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1153 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1157 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1161 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1165 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1169 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1174 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1181 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1185 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1189 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1196 /* IEEE floating-point */
1197 /* XXX: rounding mode and traps are ignored (!) */
1198 switch (fpfn) { /* f11 & 0x3F */
1201 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1205 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1209 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1213 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1217 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1221 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1225 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1229 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1233 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1237 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1241 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1245 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1248 /* XXX: incorrect */
1249 if (fn11 == 0x2AC) {
1251 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1254 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1259 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1263 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1267 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1277 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1282 if (ra == 31 && rc == 31) {
1287 gen_load_fir(ctx, rb, 0);
1288 gen_store_fir(ctx, rc, 0);
1291 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1296 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1300 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1304 gen_load_fir(ctx, ra, 0);
1305 gen_op_store_fpcr();
1310 gen_store_fir(ctx, ra, 0);
1314 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1318 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1322 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1326 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1330 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1334 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1338 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1342 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1346 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1353 switch ((uint16_t)disp16) {
1356 /* No-op. Just exit from the current tb */
1361 /* No-op. Just exit from the current tb */
1383 gen_store_ir(ctx, ra, 0);
1388 gen_store_ir(ctx, ra, 0);
1393 /* XXX: TODO: evict tb cache at address rb */
1403 gen_store_ir(ctx, ra, 0);
1415 /* HW_MFPR (PALcode) */
1416 #if defined (CONFIG_USER_ONLY)
1421 gen_op_mfpr(insn & 0xFF);
1422 gen_store_ir(ctx, ra, 0);
1426 gen_load_ir(ctx, rb, 0);
1428 gen_set_uT1(ctx, ctx->pc);
1429 gen_store_ir(ctx, ra, 1);
1432 /* Those four jumps only differ by the branch prediction hint */
1450 /* HW_LD (PALcode) */
1451 #if defined (CONFIG_USER_ONLY)
1456 gen_load_ir(ctx, rb, 0);
1457 gen_set_sT1(ctx, disp12);
1459 switch ((insn >> 12) & 0xF) {
1461 /* Longword physical access */
1465 /* Quadword physical access */
1469 /* Longword physical access with lock */
1473 /* Quadword physical access with lock */
1477 /* Longword virtual PTE fetch */
1478 gen_op_ldl_kernel();
1481 /* Quadword virtual PTE fetch */
1482 gen_op_ldq_kernel();
1491 /* Longword virtual access */
1492 gen_op_ld_phys_to_virt();
1496 /* Quadword virtual access */
1497 gen_op_ld_phys_to_virt();
1501 /* Longword virtual access with protection check */
1505 /* Quadword virtual access with protection check */
1509 /* Longword virtual access with altenate access mode */
1510 gen_op_set_alt_mode();
1511 gen_op_ld_phys_to_virt();
1513 gen_op_restore_mode();
1516 /* Quadword virtual access with altenate access mode */
1517 gen_op_set_alt_mode();
1518 gen_op_ld_phys_to_virt();
1520 gen_op_restore_mode();
1523 /* Longword virtual access with alternate access mode and
1526 gen_op_set_alt_mode();
1528 gen_op_restore_mode();
1531 /* Quadword virtual access with alternate access mode and
1534 gen_op_set_alt_mode();
1536 gen_op_restore_mode();
1539 gen_store_ir(ctx, ra, 1);
1546 if (!(ctx->amask & AMASK_BWX))
1548 gen_arith2(ctx, &gen_op_sextb, rb, rc, islit, lit);
1552 if (!(ctx->amask & AMASK_BWX))
1554 gen_arith2(ctx, &gen_op_sextw, rb, rc, islit, lit);
1558 if (!(ctx->amask & AMASK_CIX))
1560 gen_arith2(ctx, &gen_op_ctpop, rb, rc, 0, 0);
1564 if (!(ctx->amask & AMASK_MVI))
1571 if (!(ctx->amask & AMASK_CIX))
1573 gen_arith2(ctx, &gen_op_ctlz, rb, rc, 0, 0);
1577 if (!(ctx->amask & AMASK_CIX))
1579 gen_arith2(ctx, &gen_op_cttz, rb, rc, 0, 0);
1583 if (!(ctx->amask & AMASK_MVI))
1590 if (!(ctx->amask & AMASK_MVI))
1597 if (!(ctx->amask & AMASK_MVI))
1604 if (!(ctx->amask & AMASK_MVI))
1611 if (!(ctx->amask & AMASK_MVI))
1618 if (!(ctx->amask & AMASK_MVI))
1625 if (!(ctx->amask & AMASK_MVI))
1632 if (!(ctx->amask & AMASK_MVI))
1639 if (!(ctx->amask & AMASK_MVI))
1646 if (!(ctx->amask & AMASK_MVI))
1653 if (!(ctx->amask & AMASK_MVI))
1660 if (!(ctx->amask & AMASK_MVI))
1667 if (!(ctx->amask & AMASK_FIX))
1669 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1673 if (!(ctx->amask & AMASK_FIX))
1675 gen_fti(ctx, &gen_op_ftois, ra, rb);
1682 /* HW_MTPR (PALcode) */
1683 #if defined (CONFIG_USER_ONLY)
1688 gen_load_ir(ctx, ra, 0);
1689 gen_op_mtpr(insn & 0xFF);
1694 /* HW_REI (PALcode) */
1695 #if defined (CONFIG_USER_ONLY)
1704 gen_load_ir(ctx, rb, 0);
1705 gen_set_uT1(ctx, (((int64_t)insn << 51) >> 51));
1713 /* HW_ST (PALcode) */
1714 #if defined (CONFIG_USER_ONLY)
1719 gen_load_ir(ctx, rb, 0);
1720 gen_set_sT1(ctx, disp12);
1722 gen_load_ir(ctx, ra, 1);
1723 switch ((insn >> 12) & 0xF) {
1725 /* Longword physical access */
1729 /* Quadword physical access */
1733 /* Longword physical access with lock */
1737 /* Quadword physical access with lock */
1741 /* Longword virtual access */
1742 gen_op_st_phys_to_virt();
1746 /* Quadword virtual access */
1747 gen_op_st_phys_to_virt();
1769 /* Longword virtual access with alternate access mode */
1770 gen_op_set_alt_mode();
1771 gen_op_st_phys_to_virt();
1773 gen_op_restore_mode();
1776 /* Quadword virtual access with alternate access mode */
1777 gen_op_set_alt_mode();
1778 gen_op_st_phys_to_virt();
1780 gen_op_restore_mode();
1795 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
1803 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
1810 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
1814 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
1819 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
1827 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
1834 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
1838 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
1842 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
1846 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
1850 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
1854 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
1858 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
1862 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
1866 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
1870 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
1874 gen_set_uT0(ctx, ctx->pc);
1875 gen_store_ir(ctx, ra, 0);
1877 gen_set_sT1(ctx, disp21 << 2);
1885 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
1890 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
1895 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
1900 gen_set_uT0(ctx, ctx->pc);
1901 gen_store_ir(ctx, ra, 0);
1903 gen_set_sT1(ctx, disp21 << 2);
1911 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
1916 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
1921 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
1926 gen_bcond(ctx, &gen_op_cmplbc, ra, disp16);
1931 gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16);
1936 gen_bcond(ctx, &gen_op_cmpltz, ra, disp16);
1941 gen_bcond(ctx, &gen_op_cmplez, ra, disp16);
1946 gen_bcond(ctx, &gen_op_cmplbs, ra, disp16);
1951 gen_bcond(ctx, &gen_op_cmpnez, ra, disp16);
1956 gen_bcond(ctx, &gen_op_cmpgez, ra, disp16);
1961 gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16);
1973 static always_inline void gen_intermediate_code_internal (CPUState *env,
1974 TranslationBlock *tb,
1977 #if defined ALPHA_DEBUG_DISAS
1978 static int insn_count;
1980 DisasContext ctx, *ctxp = &ctx;
1981 target_ulong pc_start;
1983 uint16_t *gen_opc_end;
1990 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1992 ctx.amask = env->amask;
1993 #if defined (CONFIG_USER_ONLY)
1996 ctx.mem_idx = ((env->ps >> 3) & 3);
1997 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2000 max_insns = tb->cflags & CF_COUNT_MASK;
2002 max_insns = CF_COUNT_MASK;
2005 for (ret = 0; ret == 0;) {
2006 if (env->nb_breakpoints > 0) {
2007 for(j = 0; j < env->nb_breakpoints; j++) {
2008 if (env->breakpoints[j] == ctx.pc) {
2009 gen_excp(&ctx, EXCP_DEBUG, 0);
2015 j = gen_opc_ptr - gen_opc_buf;
2019 gen_opc_instr_start[lj++] = 0;
2020 gen_opc_pc[lj] = ctx.pc;
2021 gen_opc_instr_start[lj] = 1;
2022 gen_opc_icount[lj] = num_insns;
2025 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2027 #if defined ALPHA_DEBUG_DISAS
2029 if (logfile != NULL) {
2030 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2031 ctx.pc, ctx.mem_idx);
2034 insn = ldl_code(ctx.pc);
2035 #if defined ALPHA_DEBUG_DISAS
2037 if (logfile != NULL) {
2038 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2043 ret = translate_one(ctxp, insn);
2046 /* if we reach a page boundary or are single stepping, stop
2049 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2050 (env->singlestep_enabled) ||
2051 num_insns >= max_insns) {
2054 #if defined (DO_SINGLE_STEP)
2058 if (ret != 1 && ret != 3) {
2059 gen_update_pc(&ctx);
2061 #if defined (DO_TB_FLUSH)
2064 if (tb->cflags & CF_LAST_IO)
2066 /* Generate the return instruction */
2068 gen_icount_end(tb, num_insns);
2069 *gen_opc_ptr = INDEX_op_end;
2071 j = gen_opc_ptr - gen_opc_buf;
2074 gen_opc_instr_start[lj++] = 0;
2076 tb->size = ctx.pc - pc_start;
2077 tb->icount = num_insns;
2079 #if defined ALPHA_DEBUG_DISAS
2080 if (loglevel & CPU_LOG_TB_CPU) {
2081 cpu_dump_state(env, logfile, fprintf, 0);
2083 if (loglevel & CPU_LOG_TB_IN_ASM) {
2084 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2085 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2086 fprintf(logfile, "\n");
2091 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2093 gen_intermediate_code_internal(env, tb, 0);
2096 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2098 gen_intermediate_code_internal(env, tb, 1);
2101 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2106 env = qemu_mallocz(sizeof(CPUAlphaState));
2110 alpha_translate_init();
2112 /* XXX: should not be hardcoded */
2113 env->implver = IMPLVER_2106x;
2115 #if defined (CONFIG_USER_ONLY)
2119 /* Initialize IPR */
2120 hwpcb = env->ipr[IPR_PCBB];
2121 env->ipr[IPR_ASN] = 0;
2122 env->ipr[IPR_ASTEN] = 0;
2123 env->ipr[IPR_ASTSR] = 0;
2124 env->ipr[IPR_DATFX] = 0;
2126 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2127 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2128 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2129 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2130 env->ipr[IPR_FEN] = 0;
2131 env->ipr[IPR_IPL] = 31;
2132 env->ipr[IPR_MCES] = 0;
2133 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2134 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2135 env->ipr[IPR_SISR] = 0;
2136 env->ipr[IPR_VIRBND] = -1ULL;
2141 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2142 unsigned long searched_pc, int pc_pos, void *puc)
2144 env->pc = gen_opc_pc[pc_pos];