2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include "qemu-common.h"
31 #define DO_SINGLE_STEP
33 #define ALPHA_DEBUG_DISAS
36 typedef struct DisasContext DisasContext;
40 #if !defined (CONFIG_USER_ONLY)
46 static always_inline void gen_op_nop (void)
48 #if defined(GENERATE_NOP)
53 #define GEN32(func, NAME) \
54 static GenOpFunc *NAME ## _table [32] = { \
55 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
56 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
57 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
58 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
59 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
60 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
61 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
62 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
64 static always_inline void func (int n) \
66 NAME ## _table[n](); \
70 /* Special hacks for ir31 */
71 #define gen_op_load_T0_ir31 gen_op_reset_T0
72 #define gen_op_load_T1_ir31 gen_op_reset_T1
73 #define gen_op_load_T2_ir31 gen_op_reset_T2
74 #define gen_op_store_T0_ir31 gen_op_nop
75 #define gen_op_store_T1_ir31 gen_op_nop
76 #define gen_op_store_T2_ir31 gen_op_nop
77 #define gen_op_cmov_ir31 gen_op_nop
78 GEN32(gen_op_load_T0_ir, gen_op_load_T0_ir);
79 GEN32(gen_op_load_T1_ir, gen_op_load_T1_ir);
80 GEN32(gen_op_load_T2_ir, gen_op_load_T2_ir);
81 GEN32(gen_op_store_T0_ir, gen_op_store_T0_ir);
82 GEN32(gen_op_store_T1_ir, gen_op_store_T1_ir);
83 GEN32(gen_op_store_T2_ir, gen_op_store_T2_ir);
84 GEN32(gen_op_cmov_ir, gen_op_cmov_ir);
86 static always_inline void gen_load_ir (DisasContext *ctx, int irn, int Tn)
90 gen_op_load_T0_ir(irn);
93 gen_op_load_T1_ir(irn);
96 gen_op_load_T2_ir(irn);
101 static always_inline void gen_store_ir (DisasContext *ctx, int irn, int Tn)
105 gen_op_store_T0_ir(irn);
108 gen_op_store_T1_ir(irn);
111 gen_op_store_T2_ir(irn);
117 /* Special hacks for fir31 */
118 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
119 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
120 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
121 #define gen_op_store_FT0_fir31 gen_op_nop
122 #define gen_op_store_FT1_fir31 gen_op_nop
123 #define gen_op_store_FT2_fir31 gen_op_nop
124 #define gen_op_cmov_fir31 gen_op_nop
125 GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
126 GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
127 GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
128 GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
129 GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
130 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
131 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
133 static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
137 gen_op_load_FT0_fir(firn);
140 gen_op_load_FT1_fir(firn);
143 gen_op_load_FT2_fir(firn);
148 static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
152 gen_op_store_FT0_fir(firn);
155 gen_op_store_FT1_fir(firn);
158 gen_op_store_FT2_fir(firn);
164 #if defined(CONFIG_USER_ONLY)
165 #define OP_LD_TABLE(width) \
166 static GenOpFunc *gen_op_ld##width[] = { \
167 &gen_op_ld##width##_raw, \
169 #define OP_ST_TABLE(width) \
170 static GenOpFunc *gen_op_st##width[] = { \
171 &gen_op_st##width##_raw, \
174 #define OP_LD_TABLE(width) \
175 static GenOpFunc *gen_op_ld##width[] = { \
176 &gen_op_ld##width##_kernel, \
177 &gen_op_ld##width##_executive, \
178 &gen_op_ld##width##_supervisor, \
179 &gen_op_ld##width##_user, \
181 #define OP_ST_TABLE(width) \
182 static GenOpFunc *gen_op_st##width[] = { \
183 &gen_op_st##width##_kernel, \
184 &gen_op_st##width##_executive, \
185 &gen_op_st##width##_supervisor, \
186 &gen_op_st##width##_user, \
190 #define GEN_LD(width) \
191 OP_LD_TABLE(width); \
192 static always_inline void gen_ld##width (DisasContext *ctx) \
194 (*gen_op_ld##width[ctx->mem_idx])(); \
197 #define GEN_ST(width) \
198 OP_ST_TABLE(width); \
199 static always_inline void gen_st##width (DisasContext *ctx) \
201 (*gen_op_st##width[ctx->mem_idx])(); \
219 #if 0 /* currently unused */
230 #if defined(__i386__) || defined(__x86_64__)
231 static always_inline void gen_op_set_s16_T0 (int16_t imm)
233 gen_op_set_s32_T0((int32_t)imm);
236 static always_inline void gen_op_set_s16_T1 (int16_t imm)
238 gen_op_set_s32_T1((int32_t)imm);
241 static always_inline void gen_op_set_u16_T0 (uint16_t imm)
243 gen_op_set_s32_T0((uint32_t)imm);
246 static always_inline void gen_op_set_u16_T1 (uint16_t imm)
248 gen_op_set_s32_T1((uint32_t)imm);
252 static always_inline void gen_set_sT0 (DisasContext *ctx, int64_t imm)
264 gen_op_set_s16_T0(imm16);
267 gen_op_set_s32_T0(imm32);
270 #if 0 // Qemu does not know how to do this...
271 gen_op_set_64_T0(imm);
273 gen_op_set_64_T0(imm >> 32, imm);
278 static always_inline void gen_set_sT1 (DisasContext *ctx, int64_t imm)
290 gen_op_set_s16_T1(imm16);
293 gen_op_set_s32_T1(imm32);
296 #if 0 // Qemu does not know how to do this...
297 gen_op_set_64_T1(imm);
299 gen_op_set_64_T1(imm >> 32, imm);
304 static always_inline void gen_set_uT0 (DisasContext *ctx, uint64_t imm)
311 gen_op_set_u16_T0(imm);
313 gen_op_set_u32_T0(imm);
316 #if 0 // Qemu does not know how to do this...
317 gen_op_set_64_T0(imm);
319 gen_op_set_64_T0(imm >> 32, imm);
324 static always_inline void gen_set_uT1 (DisasContext *ctx, uint64_t imm)
331 gen_op_set_u16_T1(imm);
333 gen_op_set_u32_T1(imm);
336 #if 0 // Qemu does not know how to do this...
337 gen_op_set_64_T1(imm);
339 gen_op_set_64_T1(imm >> 32, imm);
344 static always_inline void gen_update_pc (DisasContext *ctx)
346 if (!(ctx->pc >> 32)) {
347 gen_op_update_pc32(ctx->pc);
349 #if 0 // Qemu does not know how to do this...
350 gen_op_update_pc(ctx->pc);
352 gen_op_update_pc(ctx->pc >> 32, ctx->pc);
357 static always_inline void _gen_op_bcond (DisasContext *ctx)
359 #if 0 // Qemu does not know how to do this...
360 gen_op_bcond(ctx->pc);
362 gen_op_bcond(ctx->pc >> 32, ctx->pc);
366 static always_inline void gen_excp (DisasContext *ctx,
367 int exception, int error_code)
370 gen_op_excp(exception, error_code);
373 static always_inline void gen_invalid (DisasContext *ctx)
375 gen_excp(ctx, EXCP_OPCDEC, 0);
378 static always_inline void gen_load_mem (DisasContext *ctx,
379 void (*gen_load_op)(DisasContext *ctx),
380 int ra, int rb, int32_t disp16,
383 if (ra == 31 && disp16 == 0) {
387 gen_load_ir(ctx, rb, 0);
389 gen_set_sT1(ctx, disp16);
395 gen_store_ir(ctx, ra, 1);
399 static always_inline void gen_store_mem (DisasContext *ctx,
400 void (*gen_store_op)(DisasContext *ctx),
401 int ra, int rb, int32_t disp16,
404 gen_load_ir(ctx, rb, 0);
406 gen_set_sT1(ctx, disp16);
411 gen_load_ir(ctx, ra, 1);
412 (*gen_store_op)(ctx);
415 static always_inline void gen_load_fmem (DisasContext *ctx,
416 void (*gen_load_fop)(DisasContext *ctx),
417 int ra, int rb, int32_t disp16)
419 gen_load_ir(ctx, rb, 0);
421 gen_set_sT1(ctx, disp16);
424 (*gen_load_fop)(ctx);
425 gen_store_fir(ctx, ra, 1);
428 static always_inline void gen_store_fmem (DisasContext *ctx,
429 void (*gen_store_fop)(DisasContext *ctx),
430 int ra, int rb, int32_t disp16)
432 gen_load_ir(ctx, rb, 0);
434 gen_set_sT1(ctx, disp16);
437 gen_load_fir(ctx, ra, 1);
438 (*gen_store_fop)(ctx);
441 static always_inline void gen_bcond (DisasContext *ctx,
442 void (*gen_test_op)(void),
443 int ra, int32_t disp16)
446 gen_set_uT0(ctx, ctx->pc);
447 gen_set_sT1(ctx, disp16 << 2);
450 gen_set_uT1(ctx, ctx->pc);
452 gen_load_ir(ctx, ra, 0);
457 static always_inline void gen_fbcond (DisasContext *ctx,
458 void (*gen_test_op)(void),
459 int ra, int32_t disp16)
462 gen_set_uT0(ctx, ctx->pc);
463 gen_set_sT1(ctx, disp16 << 2);
466 gen_set_uT1(ctx, ctx->pc);
468 gen_load_fir(ctx, ra, 0);
473 static always_inline void gen_arith2 (DisasContext *ctx,
474 void (*gen_arith_op)(void),
475 int rb, int rc, int islit, int8_t lit)
478 gen_set_sT0(ctx, lit);
480 gen_load_ir(ctx, rb, 0);
482 gen_store_ir(ctx, rc, 0);
485 static always_inline void gen_arith3 (DisasContext *ctx,
486 void (*gen_arith_op)(void),
487 int ra, int rb, int rc,
488 int islit, int8_t lit)
490 gen_load_ir(ctx, ra, 0);
492 gen_set_sT1(ctx, lit);
494 gen_load_ir(ctx, rb, 1);
496 gen_store_ir(ctx, rc, 0);
499 static always_inline void gen_cmov (DisasContext *ctx,
500 void (*gen_test_op)(void),
501 int ra, int rb, int rc,
502 int islit, int8_t lit)
504 gen_load_ir(ctx, ra, 1);
506 gen_set_sT0(ctx, lit);
508 gen_load_ir(ctx, rb, 0);
513 static always_inline void gen_farith2 (DisasContext *ctx,
514 void (*gen_arith_fop)(void),
517 gen_load_fir(ctx, rb, 0);
519 gen_store_fir(ctx, rc, 0);
522 static always_inline void gen_farith3 (DisasContext *ctx,
523 void (*gen_arith_fop)(void),
524 int ra, int rb, int rc)
526 gen_load_fir(ctx, ra, 0);
527 gen_load_fir(ctx, rb, 1);
529 gen_store_fir(ctx, rc, 0);
532 static always_inline void gen_fcmov (DisasContext *ctx,
533 void (*gen_test_fop)(void),
534 int ra, int rb, int rc)
536 gen_load_fir(ctx, ra, 0);
537 gen_load_fir(ctx, rb, 1);
542 static always_inline void gen_fti (DisasContext *ctx,
543 void (*gen_move_fop)(void),
546 gen_load_fir(ctx, rc, 0);
548 gen_store_ir(ctx, ra, 0);
551 static always_inline void gen_itf (DisasContext *ctx,
552 void (*gen_move_fop)(void),
555 gen_load_ir(ctx, ra, 0);
557 gen_store_fir(ctx, rc, 0);
560 static always_inline void gen_s4addl (void)
566 static always_inline void gen_s4subl (void)
572 static always_inline void gen_s8addl (void)
578 static always_inline void gen_s8subl (void)
584 static always_inline void gen_s4addq (void)
590 static always_inline void gen_s4subq (void)
596 static always_inline void gen_s8addq (void)
602 static always_inline void gen_s8subq (void)
608 static always_inline void gen_amask (void)
614 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
617 int32_t disp21, disp16, disp12;
619 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
623 /* Decode all instruction fields */
625 ra = (insn >> 21) & 0x1F;
626 rb = (insn >> 16) & 0x1F;
628 sbz = (insn >> 13) & 0x07;
629 islit = (insn >> 12) & 1;
630 lit = (insn >> 13) & 0xFF;
631 palcode = insn & 0x03FFFFFF;
632 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
633 disp16 = (int16_t)(insn & 0x0000FFFF);
634 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
635 fn16 = insn & 0x0000FFFF;
636 fn11 = (insn >> 5) & 0x000007FF;
638 fn7 = (insn >> 5) & 0x0000007F;
639 fn2 = (insn >> 5) & 0x00000003;
641 #if defined ALPHA_DEBUG_DISAS
642 if (logfile != NULL) {
643 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
644 opc, ra, rb, rc, disp16);
650 if (palcode >= 0x80 && palcode < 0xC0) {
651 /* Unprivileged PAL call */
652 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
653 #if !defined (CONFIG_USER_ONLY)
654 } else if (palcode < 0x40) {
655 /* Privileged PAL code */
656 if (ctx->mem_idx & 1)
659 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
662 /* Invalid PAL call */
690 gen_load_ir(ctx, rb, 0);
691 gen_set_sT1(ctx, disp16);
693 gen_store_ir(ctx, ra, 0);
697 gen_load_ir(ctx, rb, 0);
698 gen_set_sT1(ctx, disp16 << 16);
700 gen_store_ir(ctx, ra, 0);
704 if (!(ctx->amask & AMASK_BWX))
706 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
710 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
714 if (!(ctx->amask & AMASK_BWX))
716 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
720 if (!(ctx->amask & AMASK_BWX))
722 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
726 if (!(ctx->amask & AMASK_BWX))
728 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
732 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
738 gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit);
742 gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit);
746 gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit);
750 gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit);
754 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
758 gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit);
762 gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit);
766 gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
770 gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit);
774 gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit);
778 gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit);
782 gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit);
786 gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
790 gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit);
794 gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit);
798 gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
802 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
806 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
810 gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
814 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
818 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
822 gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
832 gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit);
836 gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit);
840 gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit);
844 gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit);
848 if (ra == rb || ra == 31 || rb == 31) {
849 if (ra == 31 && rc == 31) {
854 gen_load_ir(ctx, rb, 0);
855 gen_store_ir(ctx, rc, 0);
858 gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit);
863 gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit);
867 gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit);
871 gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit);
875 gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit);
879 gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit);
883 gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit);
887 gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit);
891 gen_arith2(ctx, &gen_amask, rb, rc, islit, lit);
895 gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit);
899 gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit);
903 gen_op_load_implver();
904 gen_store_ir(ctx, rc, 0);
914 gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit);
918 gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit);
922 gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit);
926 gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit);
930 gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit);
934 gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit);
938 gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit);
942 gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit);
946 gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit);
950 gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit);
954 gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit);
958 gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit);
962 gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit);
966 gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit);
970 gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit);
974 gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit);
978 gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit);
982 gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit);
986 gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit);
990 gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit);
994 gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit);
998 gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit);
1002 gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit);
1006 gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit);
1010 gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit);
1014 gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit);
1024 gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit);
1028 gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit);
1032 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
1036 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
1040 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
1047 switch (fpfn) { /* f11 & 0x3F */
1050 if (!(ctx->amask & AMASK_FIX))
1052 gen_itf(ctx, &gen_op_itofs, ra, rc);
1056 if (!(ctx->amask & AMASK_FIX))
1058 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1062 if (!(ctx->amask & AMASK_FIX))
1064 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1068 if (!(ctx->amask & AMASK_FIX))
1071 gen_itf(ctx, &gen_op_itoff, ra, rc);
1078 if (!(ctx->amask & AMASK_FIX))
1080 gen_itf(ctx, &gen_op_itoft, ra, rc);
1084 if (!(ctx->amask & AMASK_FIX))
1086 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1090 if (!(ctx->amask & AMASK_FIX))
1092 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1099 /* VAX floating point */
1100 /* XXX: rounding mode and trap are ignored (!) */
1101 switch (fpfn) { /* f11 & 0x3F */
1104 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1108 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1112 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1116 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1121 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1128 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1132 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1136 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1140 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1144 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1148 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1152 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1156 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1161 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1168 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1172 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1176 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1183 /* IEEE floating-point */
1184 /* XXX: rounding mode and traps are ignored (!) */
1185 switch (fpfn) { /* f11 & 0x3F */
1188 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1192 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1196 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1200 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1204 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1208 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1212 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1216 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1220 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1224 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1228 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1232 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1235 /* XXX: incorrect */
1236 if (fn11 == 0x2AC) {
1238 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1241 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1246 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1250 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1254 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1264 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1269 if (ra == 31 && rc == 31) {
1274 gen_load_fir(ctx, rb, 0);
1275 gen_store_fir(ctx, rc, 0);
1278 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1283 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1287 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1291 gen_load_fir(ctx, ra, 0);
1292 gen_op_store_fpcr();
1297 gen_store_fir(ctx, ra, 0);
1301 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1305 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1309 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1313 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1317 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1321 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1325 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1329 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1333 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1340 switch ((uint16_t)disp16) {
1343 /* No-op. Just exit from the current tb */
1348 /* No-op. Just exit from the current tb */
1370 gen_store_ir(ctx, ra, 0);
1375 gen_store_ir(ctx, ra, 0);
1380 /* XXX: TODO: evict tb cache at address rb */
1390 gen_store_ir(ctx, ra, 0);
1402 /* HW_MFPR (PALcode) */
1403 #if defined (CONFIG_USER_ONLY)
1408 gen_op_mfpr(insn & 0xFF);
1409 gen_store_ir(ctx, ra, 0);
1413 gen_load_ir(ctx, rb, 0);
1415 gen_set_uT1(ctx, ctx->pc);
1416 gen_store_ir(ctx, ra, 1);
1419 /* Those four jumps only differ by the branch prediction hint */
1437 /* HW_LD (PALcode) */
1438 #if defined (CONFIG_USER_ONLY)
1443 gen_load_ir(ctx, rb, 0);
1444 gen_set_sT1(ctx, disp12);
1446 switch ((insn >> 12) & 0xF) {
1448 /* Longword physical access */
1452 /* Quadword physical access */
1456 /* Longword physical access with lock */
1460 /* Quadword physical access with lock */
1464 /* Longword virtual PTE fetch */
1465 gen_op_ldl_kernel();
1468 /* Quadword virtual PTE fetch */
1469 gen_op_ldq_kernel();
1478 /* Longword virtual access */
1479 gen_op_ld_phys_to_virt();
1483 /* Quadword virtual access */
1484 gen_op_ld_phys_to_virt();
1488 /* Longword virtual access with protection check */
1492 /* Quadword virtual access with protection check */
1496 /* Longword virtual access with altenate access mode */
1497 gen_op_set_alt_mode();
1498 gen_op_ld_phys_to_virt();
1500 gen_op_restore_mode();
1503 /* Quadword virtual access with altenate access mode */
1504 gen_op_set_alt_mode();
1505 gen_op_ld_phys_to_virt();
1507 gen_op_restore_mode();
1510 /* Longword virtual access with alternate access mode and
1513 gen_op_set_alt_mode();
1515 gen_op_restore_mode();
1518 /* Quadword virtual access with alternate access mode and
1521 gen_op_set_alt_mode();
1523 gen_op_restore_mode();
1526 gen_store_ir(ctx, ra, 1);
1533 if (!(ctx->amask & AMASK_BWX))
1535 gen_arith2(ctx, &gen_op_sextb, rb, rc, islit, lit);
1539 if (!(ctx->amask & AMASK_BWX))
1541 gen_arith2(ctx, &gen_op_sextw, rb, rc, islit, lit);
1545 if (!(ctx->amask & AMASK_CIX))
1547 gen_arith2(ctx, &gen_op_ctpop, rb, rc, 0, 0);
1551 if (!(ctx->amask & AMASK_MVI))
1558 if (!(ctx->amask & AMASK_CIX))
1560 gen_arith2(ctx, &gen_op_ctlz, rb, rc, 0, 0);
1564 if (!(ctx->amask & AMASK_CIX))
1566 gen_arith2(ctx, &gen_op_cttz, rb, rc, 0, 0);
1570 if (!(ctx->amask & AMASK_MVI))
1577 if (!(ctx->amask & AMASK_MVI))
1584 if (!(ctx->amask & AMASK_MVI))
1591 if (!(ctx->amask & AMASK_MVI))
1598 if (!(ctx->amask & AMASK_MVI))
1605 if (!(ctx->amask & AMASK_MVI))
1612 if (!(ctx->amask & AMASK_MVI))
1619 if (!(ctx->amask & AMASK_MVI))
1626 if (!(ctx->amask & AMASK_MVI))
1633 if (!(ctx->amask & AMASK_MVI))
1640 if (!(ctx->amask & AMASK_MVI))
1647 if (!(ctx->amask & AMASK_MVI))
1654 if (!(ctx->amask & AMASK_FIX))
1656 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1660 if (!(ctx->amask & AMASK_FIX))
1662 gen_fti(ctx, &gen_op_ftois, ra, rb);
1669 /* HW_MTPR (PALcode) */
1670 #if defined (CONFIG_USER_ONLY)
1675 gen_load_ir(ctx, ra, 0);
1676 gen_op_mtpr(insn & 0xFF);
1681 /* HW_REI (PALcode) */
1682 #if defined (CONFIG_USER_ONLY)
1691 gen_load_ir(ctx, rb, 0);
1692 gen_set_uT1(ctx, (((int64_t)insn << 51) >> 51));
1700 /* HW_ST (PALcode) */
1701 #if defined (CONFIG_USER_ONLY)
1706 gen_load_ir(ctx, rb, 0);
1707 gen_set_sT1(ctx, disp12);
1709 gen_load_ir(ctx, ra, 1);
1710 switch ((insn >> 12) & 0xF) {
1712 /* Longword physical access */
1716 /* Quadword physical access */
1720 /* Longword physical access with lock */
1724 /* Quadword physical access with lock */
1728 /* Longword virtual access */
1729 gen_op_st_phys_to_virt();
1733 /* Quadword virtual access */
1734 gen_op_st_phys_to_virt();
1756 /* Longword virtual access with alternate access mode */
1757 gen_op_set_alt_mode();
1758 gen_op_st_phys_to_virt();
1760 gen_op_restore_mode();
1763 /* Quadword virtual access with alternate access mode */
1764 gen_op_set_alt_mode();
1765 gen_op_st_phys_to_virt();
1767 gen_op_restore_mode();
1782 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
1790 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
1797 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
1801 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
1806 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
1814 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
1821 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
1825 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
1829 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
1833 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
1837 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
1841 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
1845 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
1849 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
1853 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
1857 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
1861 gen_set_uT0(ctx, ctx->pc);
1862 gen_store_ir(ctx, ra, 0);
1864 gen_set_sT1(ctx, disp21 << 2);
1872 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
1877 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
1882 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
1887 gen_set_uT0(ctx, ctx->pc);
1888 gen_store_ir(ctx, ra, 0);
1890 gen_set_sT1(ctx, disp21 << 2);
1898 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
1903 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
1908 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
1913 gen_bcond(ctx, &gen_op_cmplbc, ra, disp16);
1918 gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16);
1923 gen_bcond(ctx, &gen_op_cmpltz, ra, disp16);
1928 gen_bcond(ctx, &gen_op_cmplez, ra, disp16);
1933 gen_bcond(ctx, &gen_op_cmplbs, ra, disp16);
1938 gen_bcond(ctx, &gen_op_cmpnez, ra, disp16);
1943 gen_bcond(ctx, &gen_op_cmpgez, ra, disp16);
1948 gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16);
1960 static always_inline int gen_intermediate_code_internal (CPUState *env,
1961 TranslationBlock *tb,
1964 #if defined ALPHA_DEBUG_DISAS
1965 static int insn_count;
1967 DisasContext ctx, *ctxp = &ctx;
1968 target_ulong pc_start;
1970 uint16_t *gen_opc_end;
1975 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1977 ctx.amask = env->amask;
1978 #if defined (CONFIG_USER_ONLY)
1981 ctx.mem_idx = ((env->ps >> 3) & 3);
1982 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
1984 for (ret = 0; ret == 0;) {
1985 if (env->nb_breakpoints > 0) {
1986 for(j = 0; j < env->nb_breakpoints; j++) {
1987 if (env->breakpoints[j] == ctx.pc) {
1988 gen_excp(&ctx, EXCP_DEBUG, 0);
1994 j = gen_opc_ptr - gen_opc_buf;
1998 gen_opc_instr_start[lj++] = 0;
1999 gen_opc_pc[lj] = ctx.pc;
2000 gen_opc_instr_start[lj] = 1;
2003 #if defined ALPHA_DEBUG_DISAS
2005 if (logfile != NULL) {
2006 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2007 ctx.pc, ctx.mem_idx);
2010 insn = ldl_code(ctx.pc);
2011 #if defined ALPHA_DEBUG_DISAS
2013 if (logfile != NULL) {
2014 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2018 ret = translate_one(ctxp, insn);
2021 /* if we reach a page boundary or are single stepping, stop
2024 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2025 (env->singlestep_enabled)) {
2028 #if defined (DO_SINGLE_STEP)
2032 if (ret != 1 && ret != 3) {
2033 gen_update_pc(&ctx);
2035 #if defined (DO_TB_FLUSH)
2038 /* Generate the return instruction */
2040 *gen_opc_ptr = INDEX_op_end;
2042 j = gen_opc_ptr - gen_opc_buf;
2045 gen_opc_instr_start[lj++] = 0;
2047 tb->size = ctx.pc - pc_start;
2049 #if defined ALPHA_DEBUG_DISAS
2050 if (loglevel & CPU_LOG_TB_CPU) {
2051 cpu_dump_state(env, logfile, fprintf, 0);
2053 if (loglevel & CPU_LOG_TB_IN_ASM) {
2054 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2055 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2056 fprintf(logfile, "\n");
2063 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2065 return gen_intermediate_code_internal(env, tb, 0);
2068 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2070 return gen_intermediate_code_internal(env, tb, 1);
2073 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2078 env = qemu_mallocz(sizeof(CPUAlphaState));
2083 /* XXX: should not be hardcoded */
2084 env->implver = IMPLVER_2106x;
2086 #if defined (CONFIG_USER_ONLY)
2090 /* Initialize IPR */
2091 hwpcb = env->ipr[IPR_PCBB];
2092 env->ipr[IPR_ASN] = 0;
2093 env->ipr[IPR_ASTEN] = 0;
2094 env->ipr[IPR_ASTSR] = 0;
2095 env->ipr[IPR_DATFX] = 0;
2097 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2098 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2099 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2100 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2101 env->ipr[IPR_FEN] = 0;
2102 env->ipr[IPR_IPL] = 31;
2103 env->ipr[IPR_MCES] = 0;
2104 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2105 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2106 env->ipr[IPR_SISR] = 0;
2107 env->ipr[IPR_VIRBND] = -1ULL;
2112 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2113 unsigned long searched_pc, int pc_pos, void *puc)
2115 env->pc = gen_opc_pc[pc_pos];