9 #include "qemu-common.h"
11 static uint32_t cortexa8_cp15_c0_c1[8] =
12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14 static uint32_t cortexa8_cp15_c0_c2[8] =
15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17 static uint32_t mpcore_cp15_c0_c1[8] =
18 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
20 static uint32_t mpcore_cp15_c0_c2[8] =
21 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
23 static uint32_t arm1136_cp15_c0_c1[8] =
24 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
26 static uint32_t arm1136_cp15_c0_c2[8] =
27 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
29 static uint32_t cpu_arm_find_by_name(const char *name);
31 static inline void set_feature(CPUARMState *env, int feature)
33 env->features |= 1u << feature;
36 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
38 env->cp15.c0_cpuid = id;
40 case ARM_CPUID_ARM926:
41 set_feature(env, ARM_FEATURE_VFP);
42 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
43 env->cp15.c0_cachetype = 0x1dd20d2;
44 env->cp15.c1_sys = 0x00090078;
46 case ARM_CPUID_ARM946:
47 set_feature(env, ARM_FEATURE_MPU);
48 env->cp15.c0_cachetype = 0x0f004006;
49 env->cp15.c1_sys = 0x00000078;
51 case ARM_CPUID_ARM1026:
52 set_feature(env, ARM_FEATURE_VFP);
53 set_feature(env, ARM_FEATURE_AUXCR);
54 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
55 env->cp15.c0_cachetype = 0x1dd20d2;
56 env->cp15.c1_sys = 0x00090078;
58 case ARM_CPUID_ARM1136_R2:
59 case ARM_CPUID_ARM1136:
60 set_feature(env, ARM_FEATURE_V6);
61 set_feature(env, ARM_FEATURE_VFP);
62 set_feature(env, ARM_FEATURE_AUXCR);
63 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
64 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
65 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
66 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
67 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
68 env->cp15.c0_cachetype = 0x1dd20d2;
70 case ARM_CPUID_ARM11MPCORE:
71 set_feature(env, ARM_FEATURE_V6);
72 set_feature(env, ARM_FEATURE_V6K);
73 set_feature(env, ARM_FEATURE_VFP);
74 set_feature(env, ARM_FEATURE_AUXCR);
75 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
76 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
77 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
78 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
79 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
80 env->cp15.c0_cachetype = 0x1dd20d2;
82 case ARM_CPUID_CORTEXA8:
83 set_feature(env, ARM_FEATURE_V6);
84 set_feature(env, ARM_FEATURE_V6K);
85 set_feature(env, ARM_FEATURE_V7);
86 set_feature(env, ARM_FEATURE_AUXCR);
87 set_feature(env, ARM_FEATURE_THUMB2);
88 set_feature(env, ARM_FEATURE_VFP);
89 set_feature(env, ARM_FEATURE_VFP3);
90 set_feature(env, ARM_FEATURE_NEON);
91 set_feature(env, ARM_FEATURE_THUMB2EE);
92 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
93 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
94 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
95 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
96 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
97 env->cp15.c0_cachetype = 0x82048004;
98 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
99 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
100 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
101 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
103 case ARM_CPUID_CORTEXM3:
104 set_feature(env, ARM_FEATURE_V6);
105 set_feature(env, ARM_FEATURE_THUMB2);
106 set_feature(env, ARM_FEATURE_V7);
107 set_feature(env, ARM_FEATURE_M);
108 set_feature(env, ARM_FEATURE_DIV);
110 case ARM_CPUID_ANY: /* For userspace emulation. */
111 set_feature(env, ARM_FEATURE_V6);
112 set_feature(env, ARM_FEATURE_V6K);
113 set_feature(env, ARM_FEATURE_V7);
114 set_feature(env, ARM_FEATURE_THUMB2);
115 set_feature(env, ARM_FEATURE_VFP);
116 set_feature(env, ARM_FEATURE_VFP3);
117 set_feature(env, ARM_FEATURE_NEON);
118 set_feature(env, ARM_FEATURE_THUMB2EE);
119 set_feature(env, ARM_FEATURE_DIV);
121 case ARM_CPUID_TI915T:
122 case ARM_CPUID_TI925T:
123 set_feature(env, ARM_FEATURE_OMAPCP);
124 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
125 env->cp15.c0_cachetype = 0x5109149;
126 env->cp15.c1_sys = 0x00000070;
127 env->cp15.c15_i_max = 0x000;
128 env->cp15.c15_i_min = 0xff0;
130 case ARM_CPUID_PXA250:
131 case ARM_CPUID_PXA255:
132 case ARM_CPUID_PXA260:
133 case ARM_CPUID_PXA261:
134 case ARM_CPUID_PXA262:
135 set_feature(env, ARM_FEATURE_XSCALE);
136 /* JTAG_ID is ((id << 28) | 0x09265013) */
137 env->cp15.c0_cachetype = 0xd172172;
138 env->cp15.c1_sys = 0x00000078;
140 case ARM_CPUID_PXA270_A0:
141 case ARM_CPUID_PXA270_A1:
142 case ARM_CPUID_PXA270_B0:
143 case ARM_CPUID_PXA270_B1:
144 case ARM_CPUID_PXA270_C0:
145 case ARM_CPUID_PXA270_C5:
146 set_feature(env, ARM_FEATURE_XSCALE);
147 /* JTAG_ID is ((id << 28) | 0x09265013) */
148 set_feature(env, ARM_FEATURE_IWMMXT);
149 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
150 env->cp15.c0_cachetype = 0xd172172;
151 env->cp15.c1_sys = 0x00000078;
154 cpu_abort(env, "Bad CPU ID: %x\n", id);
159 void cpu_reset(CPUARMState *env)
163 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
164 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
165 log_cpu_state(env, 0);
168 id = env->cp15.c0_cpuid;
169 memset(env, 0, offsetof(CPUARMState, breakpoints));
171 cpu_reset_model_id(env, id);
172 #if defined (CONFIG_USER_ONLY)
173 env->uncached_cpsr = ARM_CPU_MODE_USR;
174 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
176 /* SVC mode with interrupts disabled. */
177 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
178 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
181 env->uncached_cpsr &= ~CPSR_I;
182 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
183 env->cp15.c2_base_mask = 0xffffc000u;
189 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
193 /* VFP data registers are always little-endian. */
194 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
196 stfq_le_p(buf, env->vfp.regs[reg]);
199 if (arm_feature(env, ARM_FEATURE_NEON)) {
200 /* Aliases for Q regs. */
203 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
204 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
208 switch (reg - nregs) {
209 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
210 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
211 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
216 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
220 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
222 env->vfp.regs[reg] = ldfq_le_p(buf);
225 if (arm_feature(env, ARM_FEATURE_NEON)) {
228 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
229 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
233 switch (reg - nregs) {
234 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
235 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
236 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;
241 CPUARMState *cpu_arm_init(const char *cpu_model)
245 static int inited = 0;
247 id = cpu_arm_find_by_name(cpu_model);
250 env = qemu_mallocz(sizeof(CPUARMState));
254 arm_translate_init();
257 env->cpu_model_str = cpu_model;
258 env->cp15.c0_cpuid = id;
260 if (arm_feature(env, ARM_FEATURE_NEON)) {
261 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
262 51, "arm-neon.xml", 0);
263 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
264 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
265 35, "arm-vfp3.xml", 0);
266 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
267 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
268 19, "arm-vfp.xml", 0);
278 static const struct arm_cpu_t arm_cpu_names[] = {
279 { ARM_CPUID_ARM926, "arm926"},
280 { ARM_CPUID_ARM946, "arm946"},
281 { ARM_CPUID_ARM1026, "arm1026"},
282 { ARM_CPUID_ARM1136, "arm1136"},
283 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
284 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
285 { ARM_CPUID_CORTEXM3, "cortex-m3"},
286 { ARM_CPUID_CORTEXA8, "cortex-a8"},
287 { ARM_CPUID_TI925T, "ti925t" },
288 { ARM_CPUID_PXA250, "pxa250" },
289 { ARM_CPUID_PXA255, "pxa255" },
290 { ARM_CPUID_PXA260, "pxa260" },
291 { ARM_CPUID_PXA261, "pxa261" },
292 { ARM_CPUID_PXA262, "pxa262" },
293 { ARM_CPUID_PXA270, "pxa270" },
294 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
295 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
296 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
297 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
298 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
299 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
300 { ARM_CPUID_ANY, "any"},
304 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
308 (*cpu_fprintf)(f, "Available CPUs:\n");
309 for (i = 0; arm_cpu_names[i].name; i++) {
310 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
314 /* return 0 if not found */
315 static uint32_t cpu_arm_find_by_name(const char *name)
321 for (i = 0; arm_cpu_names[i].name; i++) {
322 if (strcmp(name, arm_cpu_names[i].name) == 0) {
323 id = arm_cpu_names[i].id;
330 void cpu_arm_close(CPUARMState *env)
335 uint32_t cpsr_read(CPUARMState *env)
339 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
340 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
341 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
342 | ((env->condexec_bits & 0xfc) << 8)
346 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
348 if (mask & CPSR_NZCV) {
349 env->ZF = (~val) & CPSR_Z;
351 env->CF = (val >> 29) & 1;
352 env->VF = (val << 3) & 0x80000000;
355 env->QF = ((val & CPSR_Q) != 0);
357 env->thumb = ((val & CPSR_T) != 0);
358 if (mask & CPSR_IT_0_1) {
359 env->condexec_bits &= ~3;
360 env->condexec_bits |= (val >> 25) & 3;
362 if (mask & CPSR_IT_2_7) {
363 env->condexec_bits &= 3;
364 env->condexec_bits |= (val >> 8) & 0xfc;
366 if (mask & CPSR_GE) {
367 env->GE = (val >> 16) & 0xf;
370 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
371 switch_mode(env, val & CPSR_M);
373 mask &= ~CACHED_CPSR_BITS;
374 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
377 /* Sign/zero extend */
378 uint32_t HELPER(sxtb16)(uint32_t x)
381 res = (uint16_t)(int8_t)x;
382 res |= (uint32_t)(int8_t)(x >> 16) << 16;
386 uint32_t HELPER(uxtb16)(uint32_t x)
389 res = (uint16_t)(uint8_t)x;
390 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
394 uint32_t HELPER(clz)(uint32_t x)
397 for (count = 32; x; count--)
402 int32_t HELPER(sdiv)(int32_t num, int32_t den)
409 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
416 uint32_t HELPER(rbit)(uint32_t x)
418 x = ((x & 0xff000000) >> 24)
419 | ((x & 0x00ff0000) >> 8)
420 | ((x & 0x0000ff00) << 8)
421 | ((x & 0x000000ff) << 24);
422 x = ((x & 0xf0f0f0f0) >> 4)
423 | ((x & 0x0f0f0f0f) << 4);
424 x = ((x & 0x88888888) >> 3)
425 | ((x & 0x44444444) >> 1)
426 | ((x & 0x22222222) << 1)
427 | ((x & 0x11111111) << 3);
431 uint32_t HELPER(abs)(uint32_t x)
433 return ((int32_t)x < 0) ? -x : x;
436 #if defined(CONFIG_USER_ONLY)
438 void do_interrupt (CPUState *env)
440 env->exception_index = -1;
443 /* Structure used to record exclusive memory locations. */
444 typedef struct mmon_state {
445 struct mmon_state *next;
446 CPUARMState *cpu_env;
450 /* Chain of current locks. */
451 static mmon_state* mmon_head = NULL;
453 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
454 int mmu_idx, int is_softmmu)
457 env->exception_index = EXCP_PREFETCH_ABORT;
458 env->cp15.c6_insn = address;
460 env->exception_index = EXCP_DATA_ABORT;
461 env->cp15.c6_data = address;
466 static void allocate_mmon_state(CPUState *env)
468 env->mmon_entry = malloc(sizeof (mmon_state));
469 memset (env->mmon_entry, 0, sizeof (mmon_state));
470 env->mmon_entry->cpu_env = env;
471 mmon_head = env->mmon_entry;
474 /* Flush any monitor locks for the specified address. */
475 static void flush_mmon(uint32_t addr)
479 for (mon = mmon_head; mon; mon = mon->next)
481 if (mon->addr != addr)
489 /* Mark an address for exclusive access. */
490 void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
492 if (!env->mmon_entry)
493 allocate_mmon_state(env);
494 /* Clear any previous locks. */
496 env->mmon_entry->addr = addr;
499 /* Test if an exclusive address is still exclusive. Returns zero
500 if the address is still exclusive. */
501 uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
505 if (!env->mmon_entry)
507 if (env->mmon_entry->addr == addr)
515 void HELPER(clrex)(CPUState *env)
517 if (!(env->mmon_entry && env->mmon_entry->addr))
519 flush_mmon(env->mmon_entry->addr);
522 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
527 /* These should probably raise undefined insn exceptions. */
528 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
530 int op1 = (insn >> 8) & 0xf;
531 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
535 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
537 int op1 = (insn >> 8) & 0xf;
538 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
542 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
544 cpu_abort(env, "cp15 insn %08x\n", insn);
547 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
549 cpu_abort(env, "cp15 insn %08x\n", insn);
553 /* These should probably raise undefined insn exceptions. */
554 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
556 cpu_abort(env, "v7m_mrs %d\n", reg);
559 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
561 cpu_abort(env, "v7m_mrs %d\n", reg);
565 void switch_mode(CPUState *env, int mode)
567 if (mode != ARM_CPU_MODE_USR)
568 cpu_abort(env, "Tried to switch out of user mode\n");
571 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
573 cpu_abort(env, "banked r13 write\n");
576 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
578 cpu_abort(env, "banked r13 read\n");
584 extern int semihosting_enabled;
586 /* Map CPU modes onto saved register banks. */
587 static inline int bank_number (int mode)
590 case ARM_CPU_MODE_USR:
591 case ARM_CPU_MODE_SYS:
593 case ARM_CPU_MODE_SVC:
595 case ARM_CPU_MODE_ABT:
597 case ARM_CPU_MODE_UND:
599 case ARM_CPU_MODE_IRQ:
601 case ARM_CPU_MODE_FIQ:
604 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
608 void switch_mode(CPUState *env, int mode)
613 old_mode = env->uncached_cpsr & CPSR_M;
614 if (mode == old_mode)
617 if (old_mode == ARM_CPU_MODE_FIQ) {
618 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
619 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
620 } else if (mode == ARM_CPU_MODE_FIQ) {
621 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
622 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
625 i = bank_number(old_mode);
626 env->banked_r13[i] = env->regs[13];
627 env->banked_r14[i] = env->regs[14];
628 env->banked_spsr[i] = env->spsr;
630 i = bank_number(mode);
631 env->regs[13] = env->banked_r13[i];
632 env->regs[14] = env->banked_r14[i];
633 env->spsr = env->banked_spsr[i];
636 static void v7m_push(CPUARMState *env, uint32_t val)
639 stl_phys(env->regs[13], val);
642 static uint32_t v7m_pop(CPUARMState *env)
645 val = ldl_phys(env->regs[13]);
650 /* Switch to V7M main or process stack pointer. */
651 static void switch_v7m_sp(CPUARMState *env, int process)
654 if (env->v7m.current_sp != process) {
655 tmp = env->v7m.other_sp;
656 env->v7m.other_sp = env->regs[13];
658 env->v7m.current_sp = process;
662 static void do_v7m_exception_exit(CPUARMState *env)
667 type = env->regs[15];
668 if (env->v7m.exception != 0)
669 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
671 /* Switch to the target stack. */
672 switch_v7m_sp(env, (type & 4) != 0);
674 env->regs[0] = v7m_pop(env);
675 env->regs[1] = v7m_pop(env);
676 env->regs[2] = v7m_pop(env);
677 env->regs[3] = v7m_pop(env);
678 env->regs[12] = v7m_pop(env);
679 env->regs[14] = v7m_pop(env);
680 env->regs[15] = v7m_pop(env);
682 xpsr_write(env, xpsr, 0xfffffdff);
683 /* Undo stack alignment. */
686 /* ??? The exception return type specifies Thread/Handler mode. However
687 this is also implied by the xPSR value. Not sure what to do
688 if there is a mismatch. */
689 /* ??? Likewise for mismatches between the CONTROL register and the stack
693 static void do_interrupt_v7m(CPUARMState *env)
695 uint32_t xpsr = xpsr_read(env);
700 if (env->v7m.current_sp)
702 if (env->v7m.exception == 0)
705 /* For exceptions we just mark as pending on the NVIC, and let that
707 /* TODO: Need to escalate if the current priority is higher than the
708 one we're raising. */
709 switch (env->exception_index) {
711 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
715 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
717 case EXCP_PREFETCH_ABORT:
718 case EXCP_DATA_ABORT:
719 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
722 if (semihosting_enabled) {
724 nr = lduw_code(env->regs[15]) & 0xff;
727 env->regs[0] = do_arm_semihosting(env);
731 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
734 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
736 case EXCP_EXCEPTION_EXIT:
737 do_v7m_exception_exit(env);
740 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
741 return; /* Never happens. Keep compiler happy. */
744 /* Align stack pointer. */
745 /* ??? Should only do this if Configuration Control Register
746 STACKALIGN bit is set. */
747 if (env->regs[13] & 4) {
751 /* Switch to the handler mode. */
753 v7m_push(env, env->regs[15]);
754 v7m_push(env, env->regs[14]);
755 v7m_push(env, env->regs[12]);
756 v7m_push(env, env->regs[3]);
757 v7m_push(env, env->regs[2]);
758 v7m_push(env, env->regs[1]);
759 v7m_push(env, env->regs[0]);
760 switch_v7m_sp(env, 0);
761 env->uncached_cpsr &= ~CPSR_IT;
763 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
764 env->regs[15] = addr & 0xfffffffe;
765 env->thumb = addr & 1;
768 /* Handle a CPU exception. */
769 void do_interrupt(CPUARMState *env)
777 do_interrupt_v7m(env);
780 /* TODO: Vectored interrupt controller. */
781 switch (env->exception_index) {
783 new_mode = ARM_CPU_MODE_UND;
792 if (semihosting_enabled) {
793 /* Check for semihosting interrupt. */
795 mask = lduw_code(env->regs[15] - 2) & 0xff;
797 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
799 /* Only intercept calls from privileged modes, to provide some
800 semblance of security. */
801 if (((mask == 0x123456 && !env->thumb)
802 || (mask == 0xab && env->thumb))
803 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
804 env->regs[0] = do_arm_semihosting(env);
808 new_mode = ARM_CPU_MODE_SVC;
811 /* The PC already points to the next instruction. */
815 /* See if this is a semihosting syscall. */
816 if (env->thumb && semihosting_enabled) {
817 mask = lduw_code(env->regs[15]) & 0xff;
819 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
821 env->regs[0] = do_arm_semihosting(env);
825 /* Fall through to prefetch abort. */
826 case EXCP_PREFETCH_ABORT:
827 new_mode = ARM_CPU_MODE_ABT;
829 mask = CPSR_A | CPSR_I;
832 case EXCP_DATA_ABORT:
833 new_mode = ARM_CPU_MODE_ABT;
835 mask = CPSR_A | CPSR_I;
839 new_mode = ARM_CPU_MODE_IRQ;
841 /* Disable IRQ and imprecise data aborts. */
842 mask = CPSR_A | CPSR_I;
846 new_mode = ARM_CPU_MODE_FIQ;
848 /* Disable FIQ, IRQ and imprecise data aborts. */
849 mask = CPSR_A | CPSR_I | CPSR_F;
853 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
854 return; /* Never happens. Keep compiler happy. */
857 if (env->cp15.c1_sys & (1 << 13)) {
860 switch_mode (env, new_mode);
861 env->spsr = cpsr_read(env);
863 env->condexec_bits = 0;
864 /* Switch to the new mode, and switch to Arm mode. */
865 /* ??? Thumb interrupt handlers not implemented. */
866 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
867 env->uncached_cpsr |= mask;
869 env->regs[14] = env->regs[15] + offset;
870 env->regs[15] = addr;
871 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
874 /* Check section/page access permissions.
875 Returns the page protection flags, or zero if the access is not
877 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
883 return PAGE_READ | PAGE_WRITE;
885 if (access_type == 1)
892 if (access_type == 1)
894 switch ((env->cp15.c1_sys >> 8) & 3) {
896 return is_user ? 0 : PAGE_READ;
903 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
908 return PAGE_READ | PAGE_WRITE;
910 return PAGE_READ | PAGE_WRITE;
911 case 4: /* Reserved. */
914 return is_user ? 0 : prot_ro;
918 if (!arm_feature (env, ARM_FEATURE_V7))
926 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
930 if (address & env->cp15.c2_mask)
931 table = env->cp15.c2_base1 & 0xffffc000;
933 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
935 table |= (address >> 18) & 0x3ffc;
939 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
940 int is_user, uint32_t *phys_ptr, int *prot)
950 /* Pagetable walk. */
951 /* Lookup l1 descriptor. */
952 table = get_level1_table_address(env, address);
953 desc = ldl_phys(table);
955 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
957 /* Section translation fault. */
961 if (domain == 0 || domain == 2) {
963 code = 9; /* Section domain fault. */
965 code = 11; /* Page domain fault. */
970 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
971 ap = (desc >> 10) & 3;
974 /* Lookup l2 entry. */
976 /* Coarse pagetable. */
977 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
979 /* Fine pagetable. */
980 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
982 desc = ldl_phys(table);
984 case 0: /* Page translation fault. */
987 case 1: /* 64k page. */
988 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
989 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
991 case 2: /* 4k page. */
992 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
993 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
995 case 3: /* 1k page. */
997 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
998 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1000 /* Page translation fault. */
1005 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1007 ap = (desc >> 4) & 3;
1010 /* Never happens, but compiler isn't smart enough to tell. */
1015 *prot = check_ap(env, ap, domain, access_type, is_user);
1017 /* Access permission fault. */
1020 *phys_ptr = phys_addr;
1023 return code | (domain << 4);
1026 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1027 int is_user, uint32_t *phys_ptr, int *prot)
1038 /* Pagetable walk. */
1039 /* Lookup l1 descriptor. */
1040 table = get_level1_table_address(env, address);
1041 desc = ldl_phys(table);
1044 /* Section translation fault. */
1048 } else if (type == 2 && (desc & (1 << 18))) {
1052 /* Section or page. */
1053 domain = (desc >> 4) & 0x1e;
1055 domain = (env->cp15.c3 >> domain) & 3;
1056 if (domain == 0 || domain == 2) {
1058 code = 9; /* Section domain fault. */
1060 code = 11; /* Page domain fault. */
1064 if (desc & (1 << 18)) {
1066 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
1069 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1071 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1072 xn = desc & (1 << 4);
1075 /* Lookup l2 entry. */
1076 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1077 desc = ldl_phys(table);
1078 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1080 case 0: /* Page translation fault. */
1083 case 1: /* 64k page. */
1084 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1085 xn = desc & (1 << 15);
1087 case 2: case 3: /* 4k page. */
1088 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1092 /* Never happens, but compiler isn't smart enough to tell. */
1097 if (xn && access_type == 2)
1100 /* The simplified model uses AP[0] as an access control bit. */
1101 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1102 /* Access flag fault. */
1103 code = (code == 15) ? 6 : 3;
1106 *prot = check_ap(env, ap, domain, access_type, is_user);
1108 /* Access permission fault. */
1111 *phys_ptr = phys_addr;
1114 return code | (domain << 4);
1117 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1118 int is_user, uint32_t *phys_ptr, int *prot)
1124 *phys_ptr = address;
1125 for (n = 7; n >= 0; n--) {
1126 base = env->cp15.c6_region[n];
1127 if ((base & 1) == 0)
1129 mask = 1 << ((base >> 1) & 0x1f);
1130 /* Keep this shift separate from the above to avoid an
1131 (undefined) << 32. */
1132 mask = (mask << 1) - 1;
1133 if (((base ^ address) & ~mask) == 0)
1139 if (access_type == 2) {
1140 mask = env->cp15.c5_insn;
1142 mask = env->cp15.c5_data;
1144 mask = (mask >> (n * 4)) & 0xf;
1151 *prot = PAGE_READ | PAGE_WRITE;
1156 *prot |= PAGE_WRITE;
1159 *prot = PAGE_READ | PAGE_WRITE;
1170 /* Bad permission. */
1176 static inline int get_phys_addr(CPUState *env, uint32_t address,
1177 int access_type, int is_user,
1178 uint32_t *phys_ptr, int *prot)
1180 /* Fast Context Switch Extension. */
1181 if (address < 0x02000000)
1182 address += env->cp15.c13_fcse;
1184 if ((env->cp15.c1_sys & 1) == 0) {
1185 /* MMU/MPU disabled. */
1186 *phys_ptr = address;
1187 *prot = PAGE_READ | PAGE_WRITE;
1189 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1190 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1192 } else if (env->cp15.c1_sys & (1 << 23)) {
1193 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1196 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1201 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1202 int access_type, int mmu_idx, int is_softmmu)
1208 is_user = mmu_idx == MMU_USER_IDX;
1209 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1211 /* Map a single [sub]page. */
1212 phys_addr &= ~(uint32_t)0x3ff;
1213 address &= ~(uint32_t)0x3ff;
1214 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
1218 if (access_type == 2) {
1219 env->cp15.c5_insn = ret;
1220 env->cp15.c6_insn = address;
1221 env->exception_index = EXCP_PREFETCH_ABORT;
1223 env->cp15.c5_data = ret;
1224 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1225 env->cp15.c5_data |= (1 << 11);
1226 env->cp15.c6_data = address;
1227 env->exception_index = EXCP_DATA_ABORT;
1232 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1238 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1246 /* Not really implemented. Need to figure out a sane way of doing this.
1247 Maybe add generic watchpoint support and use that. */
1249 void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
1251 env->mmon_addr = addr;
1254 uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
1256 return (env->mmon_addr != addr);
1259 void HELPER(clrex)(CPUState *env)
1261 env->mmon_addr = -1;
1264 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1266 int cp_num = (insn >> 8) & 0xf;
1267 int cp_info = (insn >> 5) & 7;
1268 int src = (insn >> 16) & 0xf;
1269 int operand = insn & 0xf;
1271 if (env->cp[cp_num].cp_write)
1272 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1273 cp_info, src, operand, val);
1276 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1278 int cp_num = (insn >> 8) & 0xf;
1279 int cp_info = (insn >> 5) & 7;
1280 int dest = (insn >> 16) & 0xf;
1281 int operand = insn & 0xf;
1283 if (env->cp[cp_num].cp_read)
1284 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1285 cp_info, dest, operand);
1289 /* Return basic MPU access permission bits. */
1290 static uint32_t simple_mpu_ap_bits(uint32_t val)
1297 for (i = 0; i < 16; i += 2) {
1298 ret |= (val >> i) & mask;
1304 /* Pad basic MPU access permission bits to extended format. */
1305 static uint32_t extended_mpu_ap_bits(uint32_t val)
1312 for (i = 0; i < 16; i += 2) {
1313 ret |= (val & mask) << i;
1319 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1325 op1 = (insn >> 21) & 7;
1326 op2 = (insn >> 5) & 7;
1328 switch ((insn >> 16) & 0xf) {
1331 if (arm_feature(env, ARM_FEATURE_XSCALE))
1333 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1335 if (arm_feature(env, ARM_FEATURE_V7)
1336 && op1 == 2 && crm == 0 && op2 == 0) {
1337 env->cp15.c0_cssel = val & 0xf;
1341 case 1: /* System configuration. */
1342 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1346 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1347 env->cp15.c1_sys = val;
1348 /* ??? Lots of these bits are not implemented. */
1349 /* This may enable/disable the MMU, so do a TLB flush. */
1352 case 1: /* Auxiliary cotrol register. */
1353 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1354 env->cp15.c1_xscaleauxcr = val;
1357 /* Not implemented. */
1360 if (arm_feature(env, ARM_FEATURE_XSCALE))
1362 if (env->cp15.c1_coproc != val) {
1363 env->cp15.c1_coproc = val;
1364 /* ??? Is this safe when called from within a TB? */
1372 case 2: /* MMU Page table control / MPU cache control. */
1373 if (arm_feature(env, ARM_FEATURE_MPU)) {
1376 env->cp15.c2_data = val;
1379 env->cp15.c2_insn = val;
1387 env->cp15.c2_base0 = val;
1390 env->cp15.c2_base1 = val;
1394 env->cp15.c2_control = val;
1395 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1396 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1403 case 3: /* MMU Domain access control / MPU write buffer control. */
1405 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1407 case 4: /* Reserved. */
1409 case 5: /* MMU Fault status / MPU access permission. */
1410 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1414 if (arm_feature(env, ARM_FEATURE_MPU))
1415 val = extended_mpu_ap_bits(val);
1416 env->cp15.c5_data = val;
1419 if (arm_feature(env, ARM_FEATURE_MPU))
1420 val = extended_mpu_ap_bits(val);
1421 env->cp15.c5_insn = val;
1424 if (!arm_feature(env, ARM_FEATURE_MPU))
1426 env->cp15.c5_data = val;
1429 if (!arm_feature(env, ARM_FEATURE_MPU))
1431 env->cp15.c5_insn = val;
1437 case 6: /* MMU Fault address / MPU base/size. */
1438 if (arm_feature(env, ARM_FEATURE_MPU)) {
1441 env->cp15.c6_region[crm] = val;
1443 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1447 env->cp15.c6_data = val;
1449 case 1: /* ??? This is WFAR on armv6 */
1451 env->cp15.c6_insn = val;
1458 case 7: /* Cache control. */
1459 env->cp15.c15_i_max = 0x000;
1460 env->cp15.c15_i_min = 0xff0;
1461 /* No cache, so nothing to do. */
1462 /* ??? MPCore has VA to PA translation functions. */
1464 case 8: /* MMU TLB control. */
1466 case 0: /* Invalidate all. */
1469 case 1: /* Invalidate single TLB entry. */
1471 /* ??? This is wrong for large pages and sections. */
1472 /* As an ugly hack to make linux work we always flush a 4K
1475 tlb_flush_page(env, val);
1476 tlb_flush_page(env, val + 0x400);
1477 tlb_flush_page(env, val + 0x800);
1478 tlb_flush_page(env, val + 0xc00);
1483 case 2: /* Invalidate on ASID. */
1484 tlb_flush(env, val == 0);
1486 case 3: /* Invalidate single entry on MVA. */
1487 /* ??? This is like case 1, but ignores ASID. */
1495 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1498 case 0: /* Cache lockdown. */
1500 case 0: /* L1 cache. */
1503 env->cp15.c9_data = val;
1506 env->cp15.c9_insn = val;
1512 case 1: /* L2 cache. */
1513 /* Ignore writes to L2 lockdown/auxiliary registers. */
1519 case 1: /* TCM memory region registers. */
1520 /* Not implemented. */
1526 case 10: /* MMU TLB lockdown. */
1527 /* ??? TLB lockdown not implemented. */
1529 case 12: /* Reserved. */
1531 case 13: /* Process ID. */
1534 /* Unlike real hardware the qemu TLB uses virtual addresses,
1535 not modified virtual addresses, so this causes a TLB flush.
1537 if (env->cp15.c13_fcse != val)
1539 env->cp15.c13_fcse = val;
1542 /* This changes the ASID, so do a TLB flush. */
1543 if (env->cp15.c13_context != val
1544 && !arm_feature(env, ARM_FEATURE_MPU))
1546 env->cp15.c13_context = val;
1549 env->cp15.c13_tls1 = val;
1552 env->cp15.c13_tls2 = val;
1555 env->cp15.c13_tls3 = val;
1561 case 14: /* Reserved. */
1563 case 15: /* Implementation specific. */
1564 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1565 if (op2 == 0 && crm == 1) {
1566 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1567 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1569 env->cp15.c15_cpar = val & 0x3fff;
1575 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1579 case 1: /* Set TI925T configuration. */
1580 env->cp15.c15_ticonfig = val & 0xe7;
1581 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1582 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1584 case 2: /* Set I_max. */
1585 env->cp15.c15_i_max = val;
1587 case 3: /* Set I_min. */
1588 env->cp15.c15_i_min = val;
1590 case 4: /* Set thread-ID. */
1591 env->cp15.c15_threadid = val & 0xffff;
1593 case 8: /* Wait-for-interrupt (deprecated). */
1594 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1604 /* ??? For debugging only. Should raise illegal instruction exception. */
1605 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1606 (insn >> 16) & 0xf, crm, op1, op2);
1609 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1615 op1 = (insn >> 21) & 7;
1616 op2 = (insn >> 5) & 7;
1618 switch ((insn >> 16) & 0xf) {
1619 case 0: /* ID codes. */
1625 case 0: /* Device ID. */
1626 return env->cp15.c0_cpuid;
1627 case 1: /* Cache Type. */
1628 return env->cp15.c0_cachetype;
1629 case 2: /* TCM status. */
1631 case 3: /* TLB type register. */
1632 return 0; /* No lockable TLB entries. */
1633 case 5: /* CPU ID */
1634 return env->cpu_index;
1639 if (!arm_feature(env, ARM_FEATURE_V6))
1641 return env->cp15.c0_c1[op2];
1643 if (!arm_feature(env, ARM_FEATURE_V6))
1645 return env->cp15.c0_c2[op2];
1646 case 3: case 4: case 5: case 6: case 7:
1652 /* These registers aren't documented on arm11 cores. However
1653 Linux looks at them anyway. */
1654 if (!arm_feature(env, ARM_FEATURE_V6))
1658 if (!arm_feature(env, ARM_FEATURE_V7))
1663 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1665 return env->cp15.c0_clid;
1671 if (op2 != 0 || crm != 0)
1673 return env->cp15.c0_cssel;
1677 case 1: /* System configuration. */
1678 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1681 case 0: /* Control register. */
1682 return env->cp15.c1_sys;
1683 case 1: /* Auxiliary control register. */
1684 if (arm_feature(env, ARM_FEATURE_XSCALE))
1685 return env->cp15.c1_xscaleauxcr;
1686 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1688 switch (ARM_CPUID(env)) {
1689 case ARM_CPUID_ARM1026:
1691 case ARM_CPUID_ARM1136:
1692 case ARM_CPUID_ARM1136_R2:
1694 case ARM_CPUID_ARM11MPCORE:
1696 case ARM_CPUID_CORTEXA8:
1701 case 2: /* Coprocessor access register. */
1702 if (arm_feature(env, ARM_FEATURE_XSCALE))
1704 return env->cp15.c1_coproc;
1708 case 2: /* MMU Page table control / MPU cache control. */
1709 if (arm_feature(env, ARM_FEATURE_MPU)) {
1712 return env->cp15.c2_data;
1715 return env->cp15.c2_insn;
1723 return env->cp15.c2_base0;
1725 return env->cp15.c2_base1;
1727 return env->cp15.c2_control;
1732 case 3: /* MMU Domain access control / MPU write buffer control. */
1733 return env->cp15.c3;
1734 case 4: /* Reserved. */
1736 case 5: /* MMU Fault status / MPU access permission. */
1737 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1741 if (arm_feature(env, ARM_FEATURE_MPU))
1742 return simple_mpu_ap_bits(env->cp15.c5_data);
1743 return env->cp15.c5_data;
1745 if (arm_feature(env, ARM_FEATURE_MPU))
1746 return simple_mpu_ap_bits(env->cp15.c5_data);
1747 return env->cp15.c5_insn;
1749 if (!arm_feature(env, ARM_FEATURE_MPU))
1751 return env->cp15.c5_data;
1753 if (!arm_feature(env, ARM_FEATURE_MPU))
1755 return env->cp15.c5_insn;
1759 case 6: /* MMU Fault address. */
1760 if (arm_feature(env, ARM_FEATURE_MPU)) {
1763 return env->cp15.c6_region[crm];
1765 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1769 return env->cp15.c6_data;
1771 if (arm_feature(env, ARM_FEATURE_V6)) {
1772 /* Watchpoint Fault Adrress. */
1773 return 0; /* Not implemented. */
1775 /* Instruction Fault Adrress. */
1776 /* Arm9 doesn't have an IFAR, but implementing it anyway
1777 shouldn't do any harm. */
1778 return env->cp15.c6_insn;
1781 if (arm_feature(env, ARM_FEATURE_V6)) {
1782 /* Instruction Fault Adrress. */
1783 return env->cp15.c6_insn;
1791 case 7: /* Cache control. */
1792 /* FIXME: Should only clear Z flag if destination is r15. */
1795 case 8: /* MMU TLB control. */
1797 case 9: /* Cache lockdown. */
1799 case 0: /* L1 cache. */
1800 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1804 return env->cp15.c9_data;
1806 return env->cp15.c9_insn;
1810 case 1: /* L2 cache */
1813 /* L2 Lockdown and Auxiliary control. */
1818 case 10: /* MMU TLB lockdown. */
1819 /* ??? TLB lockdown not implemented. */
1821 case 11: /* TCM DMA control. */
1822 case 12: /* Reserved. */
1824 case 13: /* Process ID. */
1827 return env->cp15.c13_fcse;
1829 return env->cp15.c13_context;
1831 return env->cp15.c13_tls1;
1833 return env->cp15.c13_tls2;
1835 return env->cp15.c13_tls3;
1839 case 14: /* Reserved. */
1841 case 15: /* Implementation specific. */
1842 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1843 if (op2 == 0 && crm == 1)
1844 return env->cp15.c15_cpar;
1848 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1852 case 1: /* Read TI925T configuration. */
1853 return env->cp15.c15_ticonfig;
1854 case 2: /* Read I_max. */
1855 return env->cp15.c15_i_max;
1856 case 3: /* Read I_min. */
1857 return env->cp15.c15_i_min;
1858 case 4: /* Read thread-ID. */
1859 return env->cp15.c15_threadid;
1860 case 8: /* TI925T_status */
1863 /* TODO: Peripheral port remap register:
1864 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1865 * controller base address at $rn & ~0xfff and map size of
1866 * 0x200 << ($rn & 0xfff), when MMU is off. */
1872 /* ??? For debugging only. Should raise illegal instruction exception. */
1873 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1874 (insn >> 16) & 0xf, crm, op1, op2);
1878 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1880 env->banked_r13[bank_number(mode)] = val;
1883 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
1885 return env->banked_r13[bank_number(mode)];
1888 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
1892 return xpsr_read(env) & 0xf8000000;
1894 return xpsr_read(env) & 0xf80001ff;
1896 return xpsr_read(env) & 0xff00fc00;
1898 return xpsr_read(env) & 0xff00fdff;
1900 return xpsr_read(env) & 0x000001ff;
1902 return xpsr_read(env) & 0x0700fc00;
1904 return xpsr_read(env) & 0x0700edff;
1906 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1908 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1909 case 16: /* PRIMASK */
1910 return (env->uncached_cpsr & CPSR_I) != 0;
1911 case 17: /* FAULTMASK */
1912 return (env->uncached_cpsr & CPSR_F) != 0;
1913 case 18: /* BASEPRI */
1914 case 19: /* BASEPRI_MAX */
1915 return env->v7m.basepri;
1916 case 20: /* CONTROL */
1917 return env->v7m.control;
1919 /* ??? For debugging only. */
1920 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1925 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
1929 xpsr_write(env, val, 0xf8000000);
1932 xpsr_write(env, val, 0xf8000000);
1935 xpsr_write(env, val, 0xfe00fc00);
1938 xpsr_write(env, val, 0xfe00fc00);
1941 /* IPSR bits are readonly. */
1944 xpsr_write(env, val, 0x0600fc00);
1947 xpsr_write(env, val, 0x0600fc00);
1950 if (env->v7m.current_sp)
1951 env->v7m.other_sp = val;
1953 env->regs[13] = val;
1956 if (env->v7m.current_sp)
1957 env->regs[13] = val;
1959 env->v7m.other_sp = val;
1961 case 16: /* PRIMASK */
1963 env->uncached_cpsr |= CPSR_I;
1965 env->uncached_cpsr &= ~CPSR_I;
1967 case 17: /* FAULTMASK */
1969 env->uncached_cpsr |= CPSR_F;
1971 env->uncached_cpsr &= ~CPSR_F;
1973 case 18: /* BASEPRI */
1974 env->v7m.basepri = val & 0xff;
1976 case 19: /* BASEPRI_MAX */
1978 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1979 env->v7m.basepri = val;
1981 case 20: /* CONTROL */
1982 env->v7m.control = val & 3;
1983 switch_v7m_sp(env, (val & 2) != 0);
1986 /* ??? For debugging only. */
1987 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1992 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1993 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1996 if (cpnum < 0 || cpnum > 14) {
1997 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2001 env->cp[cpnum].cp_read = cp_read;
2002 env->cp[cpnum].cp_write = cp_write;
2003 env->cp[cpnum].opaque = opaque;
2008 /* Note that signed overflow is undefined in C. The following routines are
2009 careful to use unsigned types where modulo arithmetic is required.
2010 Failure to do so _will_ break on newer gcc. */
2012 /* Signed saturating arithmetic. */
2014 /* Perform 16-bit signed saturating addition. */
2015 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2020 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2029 /* Perform 8-bit signed saturating addition. */
2030 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2035 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2044 /* Perform 16-bit signed saturating subtraction. */
2045 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2050 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2059 /* Perform 8-bit signed saturating subtraction. */
2060 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2065 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2074 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2075 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2076 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2077 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2080 #include "op_addsub.h"
2082 /* Unsigned saturating arithmetic. */
2083 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2092 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2100 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2109 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2117 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2118 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2119 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2120 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2123 #include "op_addsub.h"
2125 /* Signed modulo arithmetic. */
2126 #define SARITH16(a, b, n, op) do { \
2128 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2129 RESULT(sum, n, 16); \
2131 ge |= 3 << (n * 2); \
2134 #define SARITH8(a, b, n, op) do { \
2136 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2137 RESULT(sum, n, 8); \
2143 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2144 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2145 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2146 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2150 #include "op_addsub.h"
2152 /* Unsigned modulo arithmetic. */
2153 #define ADD16(a, b, n) do { \
2155 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2156 RESULT(sum, n, 16); \
2157 if ((sum >> 16) == 1) \
2158 ge |= 3 << (n * 2); \
2161 #define ADD8(a, b, n) do { \
2163 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2164 RESULT(sum, n, 8); \
2165 if ((sum >> 8) == 1) \
2169 #define SUB16(a, b, n) do { \
2171 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2172 RESULT(sum, n, 16); \
2173 if ((sum >> 16) == 0) \
2174 ge |= 3 << (n * 2); \
2177 #define SUB8(a, b, n) do { \
2179 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2180 RESULT(sum, n, 8); \
2181 if ((sum >> 8) == 0) \
2188 #include "op_addsub.h"
2190 /* Halved signed arithmetic. */
2191 #define ADD16(a, b, n) \
2192 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2193 #define SUB16(a, b, n) \
2194 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2195 #define ADD8(a, b, n) \
2196 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2197 #define SUB8(a, b, n) \
2198 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2201 #include "op_addsub.h"
2203 /* Halved unsigned arithmetic. */
2204 #define ADD16(a, b, n) \
2205 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2206 #define SUB16(a, b, n) \
2207 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2208 #define ADD8(a, b, n) \
2209 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2210 #define SUB8(a, b, n) \
2211 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2214 #include "op_addsub.h"
2216 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2224 /* Unsigned sum of absolute byte differences. */
2225 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2228 sum = do_usad(a, b);
2229 sum += do_usad(a >> 8, b >> 8);
2230 sum += do_usad(a >> 16, b >>16);
2231 sum += do_usad(a >> 24, b >> 24);
2235 /* For ARMv6 SEL instruction. */
2236 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2249 return (a & mask) | (b & ~mask);
2252 uint32_t HELPER(logicq_cc)(uint64_t val)
2254 return (val >> 32) | (val != 0);
2257 /* VFP support. We follow the convention used for VFP instrunctions:
2258 Single precition routines have a "s" suffix, double precision a
2261 /* Convert host exception flags to vfp form. */
2262 static inline int vfp_exceptbits_from_host(int host_bits)
2264 int target_bits = 0;
2266 if (host_bits & float_flag_invalid)
2268 if (host_bits & float_flag_divbyzero)
2270 if (host_bits & float_flag_overflow)
2272 if (host_bits & float_flag_underflow)
2274 if (host_bits & float_flag_inexact)
2275 target_bits |= 0x10;
2279 uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2284 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2285 | (env->vfp.vec_len << 16)
2286 | (env->vfp.vec_stride << 20);
2287 i = get_float_exception_flags(&env->vfp.fp_status);
2288 fpscr |= vfp_exceptbits_from_host(i);
2292 /* Convert vfp exception flags to target form. */
2293 static inline int vfp_exceptbits_to_host(int target_bits)
2297 if (target_bits & 1)
2298 host_bits |= float_flag_invalid;
2299 if (target_bits & 2)
2300 host_bits |= float_flag_divbyzero;
2301 if (target_bits & 4)
2302 host_bits |= float_flag_overflow;
2303 if (target_bits & 8)
2304 host_bits |= float_flag_underflow;
2305 if (target_bits & 0x10)
2306 host_bits |= float_flag_inexact;
2310 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2315 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2316 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2317 env->vfp.vec_len = (val >> 16) & 7;
2318 env->vfp.vec_stride = (val >> 20) & 3;
2321 if (changed & (3 << 22)) {
2322 i = (val >> 22) & 3;
2325 i = float_round_nearest_even;
2331 i = float_round_down;
2334 i = float_round_to_zero;
2337 set_float_rounding_mode(i, &env->vfp.fp_status);
2339 if (changed & (1 << 24))
2340 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2341 if (changed & (1 << 25))
2342 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2344 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2345 set_float_exception_flags(i, &env->vfp.fp_status);
2348 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2350 #define VFP_BINOP(name) \
2351 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2353 return float32_ ## name (a, b, &env->vfp.fp_status); \
2355 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2357 return float64_ ## name (a, b, &env->vfp.fp_status); \
2365 float32 VFP_HELPER(neg, s)(float32 a)
2367 return float32_chs(a);
2370 float64 VFP_HELPER(neg, d)(float64 a)
2372 return float64_chs(a);
2375 float32 VFP_HELPER(abs, s)(float32 a)
2377 return float32_abs(a);
2380 float64 VFP_HELPER(abs, d)(float64 a)
2382 return float64_abs(a);
2385 float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2387 return float32_sqrt(a, &env->vfp.fp_status);
2390 float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2392 return float64_sqrt(a, &env->vfp.fp_status);
2395 /* XXX: check quiet/signaling case */
2396 #define DO_VFP_cmp(p, type) \
2397 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2400 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2401 case 0: flags = 0x6; break; \
2402 case -1: flags = 0x8; break; \
2403 case 1: flags = 0x2; break; \
2404 default: case 2: flags = 0x3; break; \
2406 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2407 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2409 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2412 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2413 case 0: flags = 0x6; break; \
2414 case -1: flags = 0x8; break; \
2415 case 1: flags = 0x2; break; \
2416 default: case 2: flags = 0x3; break; \
2418 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2419 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2421 DO_VFP_cmp(s, float32)
2422 DO_VFP_cmp(d, float64)
2425 /* Helper routines to perform bitwise copies between float and int. */
2426 static inline float32 vfp_itos(uint32_t i)
2437 static inline uint32_t vfp_stoi(float32 s)
2448 static inline float64 vfp_itod(uint64_t i)
2459 static inline uint64_t vfp_dtoi(float64 d)
2470 /* Integer to float conversion. */
2471 float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2473 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2476 float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2478 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2481 float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2483 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2486 float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2488 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2491 /* Float to integer conversion. */
2492 float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2494 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2497 float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2499 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2502 float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2504 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2507 float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2509 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2512 float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2514 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2517 float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2519 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2522 float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2524 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2527 float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2529 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2532 /* floating point conversion */
2533 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2535 return float32_to_float64(x, &env->vfp.fp_status);
2538 float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2540 return float64_to_float32(x, &env->vfp.fp_status);
2543 /* VFP3 fixed point conversion. */
2544 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2545 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2548 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2549 &env->vfp.fp_status); \
2550 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2552 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2555 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2556 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2557 &env->vfp.fp_status)); \
2560 VFP_CONV_FIX(sh, d, float64, int16, )
2561 VFP_CONV_FIX(sl, d, float64, int32, )
2562 VFP_CONV_FIX(uh, d, float64, uint16, u)
2563 VFP_CONV_FIX(ul, d, float64, uint32, u)
2564 VFP_CONV_FIX(sh, s, float32, int16, )
2565 VFP_CONV_FIX(sl, s, float32, int32, )
2566 VFP_CONV_FIX(uh, s, float32, uint16, u)
2567 VFP_CONV_FIX(ul, s, float32, uint32, u)
2570 float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2572 float_status *s = &env->vfp.fp_status;
2573 float32 two = int32_to_float32(2, s);
2574 return float32_sub(two, float32_mul(a, b, s), s);
2577 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2579 float_status *s = &env->vfp.fp_status;
2580 float32 three = int32_to_float32(3, s);
2581 return float32_sub(three, float32_mul(a, b, s), s);
2586 /* TODO: The architecture specifies the value that the estimate functions
2587 should return. We return the exact reciprocal/root instead. */
2588 float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2590 float_status *s = &env->vfp.fp_status;
2591 float32 one = int32_to_float32(1, s);
2592 return float32_div(one, a, s);
2595 float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2597 float_status *s = &env->vfp.fp_status;
2598 float32 one = int32_to_float32(1, s);
2599 return float32_div(one, float32_sqrt(a, s), s);
2602 uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2604 float_status *s = &env->vfp.fp_status;
2606 tmp = int32_to_float32(a, s);
2607 tmp = float32_scalbn(tmp, -32, s);
2608 tmp = helper_recpe_f32(tmp, env);
2609 tmp = float32_scalbn(tmp, 31, s);
2610 return float32_to_int32(tmp, s);
2613 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2615 float_status *s = &env->vfp.fp_status;
2617 tmp = int32_to_float32(a, s);
2618 tmp = float32_scalbn(tmp, -32, s);
2619 tmp = helper_rsqrte_f32(tmp, env);
2620 tmp = float32_scalbn(tmp, 31, s);
2621 return float32_to_int32(tmp, s);
2624 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2627 if (env->teecr != val) {