9 static uint32_t cortexa8_cp15_c0_c1[8] =
10 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
12 static uint32_t cortexa8_cp15_c0_c2[8] =
13 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
15 static uint32_t mpcore_cp15_c0_c1[8] =
16 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
18 static uint32_t mpcore_cp15_c0_c2[8] =
19 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
21 static uint32_t arm1136_cp15_c0_c1[8] =
22 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
24 static uint32_t arm1136_cp15_c0_c2[8] =
25 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
27 static uint32_t cpu_arm_find_by_name(const char *name);
29 static inline void set_feature(CPUARMState *env, int feature)
31 env->features |= 1u << feature;
34 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
36 env->cp15.c0_cpuid = id;
38 case ARM_CPUID_ARM926:
39 set_feature(env, ARM_FEATURE_VFP);
40 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
41 env->cp15.c0_cachetype = 0x1dd20d2;
42 env->cp15.c1_sys = 0x00090078;
44 case ARM_CPUID_ARM946:
45 set_feature(env, ARM_FEATURE_MPU);
46 env->cp15.c0_cachetype = 0x0f004006;
47 env->cp15.c1_sys = 0x00000078;
49 case ARM_CPUID_ARM1026:
50 set_feature(env, ARM_FEATURE_VFP);
51 set_feature(env, ARM_FEATURE_AUXCR);
52 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
53 env->cp15.c0_cachetype = 0x1dd20d2;
54 env->cp15.c1_sys = 0x00090078;
56 case ARM_CPUID_ARM1136:
57 set_feature(env, ARM_FEATURE_V6);
58 set_feature(env, ARM_FEATURE_VFP);
59 set_feature(env, ARM_FEATURE_AUXCR);
60 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
61 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
62 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
63 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
64 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
65 env->cp15.c0_cachetype = 0x1dd20d2;
67 case ARM_CPUID_ARM11MPCORE:
68 set_feature(env, ARM_FEATURE_V6);
69 set_feature(env, ARM_FEATURE_V6K);
70 set_feature(env, ARM_FEATURE_VFP);
71 set_feature(env, ARM_FEATURE_AUXCR);
72 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
73 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
74 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
75 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
76 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
77 env->cp15.c0_cachetype = 0x1dd20d2;
79 case ARM_CPUID_CORTEXA8:
80 set_feature(env, ARM_FEATURE_V6);
81 set_feature(env, ARM_FEATURE_V6K);
82 set_feature(env, ARM_FEATURE_V7);
83 set_feature(env, ARM_FEATURE_AUXCR);
84 set_feature(env, ARM_FEATURE_THUMB2);
85 set_feature(env, ARM_FEATURE_VFP);
86 set_feature(env, ARM_FEATURE_VFP3);
87 set_feature(env, ARM_FEATURE_NEON);
88 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
89 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
90 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
91 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
92 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
93 env->cp15.c0_cachetype = 0x1dd20d2;
95 case ARM_CPUID_CORTEXM3:
96 set_feature(env, ARM_FEATURE_V6);
97 set_feature(env, ARM_FEATURE_THUMB2);
98 set_feature(env, ARM_FEATURE_V7);
99 set_feature(env, ARM_FEATURE_M);
100 set_feature(env, ARM_FEATURE_DIV);
102 case ARM_CPUID_ANY: /* For userspace emulation. */
103 set_feature(env, ARM_FEATURE_V6);
104 set_feature(env, ARM_FEATURE_V6K);
105 set_feature(env, ARM_FEATURE_V7);
106 set_feature(env, ARM_FEATURE_THUMB2);
107 set_feature(env, ARM_FEATURE_VFP);
108 set_feature(env, ARM_FEATURE_VFP3);
109 set_feature(env, ARM_FEATURE_NEON);
110 set_feature(env, ARM_FEATURE_DIV);
112 case ARM_CPUID_TI915T:
113 case ARM_CPUID_TI925T:
114 set_feature(env, ARM_FEATURE_OMAPCP);
115 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
116 env->cp15.c0_cachetype = 0x5109149;
117 env->cp15.c1_sys = 0x00000070;
118 env->cp15.c15_i_max = 0x000;
119 env->cp15.c15_i_min = 0xff0;
121 case ARM_CPUID_PXA250:
122 case ARM_CPUID_PXA255:
123 case ARM_CPUID_PXA260:
124 case ARM_CPUID_PXA261:
125 case ARM_CPUID_PXA262:
126 set_feature(env, ARM_FEATURE_XSCALE);
127 /* JTAG_ID is ((id << 28) | 0x09265013) */
128 env->cp15.c0_cachetype = 0xd172172;
129 env->cp15.c1_sys = 0x00000078;
131 case ARM_CPUID_PXA270_A0:
132 case ARM_CPUID_PXA270_A1:
133 case ARM_CPUID_PXA270_B0:
134 case ARM_CPUID_PXA270_B1:
135 case ARM_CPUID_PXA270_C0:
136 case ARM_CPUID_PXA270_C5:
137 set_feature(env, ARM_FEATURE_XSCALE);
138 /* JTAG_ID is ((id << 28) | 0x09265013) */
139 set_feature(env, ARM_FEATURE_IWMMXT);
140 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
141 env->cp15.c0_cachetype = 0xd172172;
142 env->cp15.c1_sys = 0x00000078;
145 cpu_abort(env, "Bad CPU ID: %x\n", id);
150 void cpu_reset(CPUARMState *env)
153 id = env->cp15.c0_cpuid;
154 memset(env, 0, offsetof(CPUARMState, breakpoints));
156 cpu_reset_model_id(env, id);
157 #if defined (CONFIG_USER_ONLY)
158 env->uncached_cpsr = ARM_CPU_MODE_USR;
159 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
161 /* SVC mode with interrupts disabled. */
162 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
163 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
166 env->uncached_cpsr &= ~CPSR_I;
167 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
173 CPUARMState *cpu_arm_init(const char *cpu_model)
178 id = cpu_arm_find_by_name(cpu_model);
181 env = qemu_mallocz(sizeof(CPUARMState));
185 env->cp15.c0_cpuid = id;
195 static const struct arm_cpu_t arm_cpu_names[] = {
196 { ARM_CPUID_ARM926, "arm926"},
197 { ARM_CPUID_ARM946, "arm946"},
198 { ARM_CPUID_ARM1026, "arm1026"},
199 { ARM_CPUID_ARM1136, "arm1136"},
200 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
201 { ARM_CPUID_CORTEXM3, "cortex-m3"},
202 { ARM_CPUID_CORTEXA8, "cortex-a8"},
203 { ARM_CPUID_TI925T, "ti925t" },
204 { ARM_CPUID_PXA250, "pxa250" },
205 { ARM_CPUID_PXA255, "pxa255" },
206 { ARM_CPUID_PXA260, "pxa260" },
207 { ARM_CPUID_PXA261, "pxa261" },
208 { ARM_CPUID_PXA262, "pxa262" },
209 { ARM_CPUID_PXA270, "pxa270" },
210 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
211 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
212 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
213 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
214 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
215 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
216 { ARM_CPUID_ANY, "any"},
220 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
224 (*cpu_fprintf)(f, "Available CPUs:\n");
225 for (i = 0; arm_cpu_names[i].name; i++) {
226 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
230 /* return 0 if not found */
231 static uint32_t cpu_arm_find_by_name(const char *name)
237 for (i = 0; arm_cpu_names[i].name; i++) {
238 if (strcmp(name, arm_cpu_names[i].name) == 0) {
239 id = arm_cpu_names[i].id;
246 void cpu_arm_close(CPUARMState *env)
251 /* Polynomial multiplication is like integer multiplcation except the
252 partial products are XORed, not added. */
253 uint32_t helper_neon_mul_p8(uint32_t op1, uint32_t op2)
265 mask |= (0xff << 16);
267 mask |= (0xff << 24);
268 result ^= op2 & mask;
269 op1 = (op1 >> 1) & 0x7f7f7f7f;
270 op2 = (op2 << 1) & 0xfefefefe;
275 #if defined(CONFIG_USER_ONLY)
277 void do_interrupt (CPUState *env)
279 env->exception_index = -1;
282 /* Structure used to record exclusive memory locations. */
283 typedef struct mmon_state {
284 struct mmon_state *next;
285 CPUARMState *cpu_env;
289 /* Chain of current locks. */
290 static mmon_state* mmon_head = NULL;
292 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
293 int mmu_idx, int is_softmmu)
296 env->exception_index = EXCP_PREFETCH_ABORT;
297 env->cp15.c6_insn = address;
299 env->exception_index = EXCP_DATA_ABORT;
300 env->cp15.c6_data = address;
305 static void allocate_mmon_state(CPUState *env)
307 env->mmon_entry = malloc(sizeof (mmon_state));
308 if (!env->mmon_entry)
310 memset (env->mmon_entry, 0, sizeof (mmon_state));
311 env->mmon_entry->cpu_env = env;
312 mmon_head = env->mmon_entry;
315 /* Flush any monitor locks for the specified address. */
316 static void flush_mmon(uint32_t addr)
320 for (mon = mmon_head; mon; mon = mon->next)
322 if (mon->addr != addr)
330 /* Mark an address for exclusive access. */
331 void helper_mark_exclusive(CPUState *env, uint32_t addr)
333 if (!env->mmon_entry)
334 allocate_mmon_state(env);
335 /* Clear any previous locks. */
337 env->mmon_entry->addr = addr;
340 /* Test if an exclusive address is still exclusive. Returns zero
341 if the address is still exclusive. */
342 int helper_test_exclusive(CPUState *env, uint32_t addr)
346 if (!env->mmon_entry)
348 if (env->mmon_entry->addr == addr)
356 void helper_clrex(CPUState *env)
358 if (!(env->mmon_entry && env->mmon_entry->addr))
360 flush_mmon(env->mmon_entry->addr);
363 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
368 /* These should probably raise undefined insn exceptions. */
369 void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
371 int op1 = (insn >> 8) & 0xf;
372 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
376 uint32_t helper_get_cp(CPUState *env, uint32_t insn)
378 int op1 = (insn >> 8) & 0xf;
379 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
383 void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
385 cpu_abort(env, "cp15 insn %08x\n", insn);
388 uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
390 cpu_abort(env, "cp15 insn %08x\n", insn);
394 /* These should probably raise undefined insn exceptions. */
395 void helper_v7m_msr(CPUState *env, int reg, uint32_t val)
397 cpu_abort(env, "v7m_mrs %d\n", reg);
400 uint32_t helper_v7m_mrs(CPUState *env, int reg)
402 cpu_abort(env, "v7m_mrs %d\n", reg);
406 void switch_mode(CPUState *env, int mode)
408 if (mode != ARM_CPU_MODE_USR)
409 cpu_abort(env, "Tried to switch out of user mode\n");
412 void helper_set_r13_banked(CPUState *env, int mode, uint32_t val)
414 cpu_abort(env, "banked r13 write\n");
417 uint32_t helper_get_r13_banked(CPUState *env, int mode)
419 cpu_abort(env, "banked r13 read\n");
425 extern int semihosting_enabled;
427 /* Map CPU modes onto saved register banks. */
428 static inline int bank_number (int mode)
431 case ARM_CPU_MODE_USR:
432 case ARM_CPU_MODE_SYS:
434 case ARM_CPU_MODE_SVC:
436 case ARM_CPU_MODE_ABT:
438 case ARM_CPU_MODE_UND:
440 case ARM_CPU_MODE_IRQ:
442 case ARM_CPU_MODE_FIQ:
445 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
449 void switch_mode(CPUState *env, int mode)
454 old_mode = env->uncached_cpsr & CPSR_M;
455 if (mode == old_mode)
458 if (old_mode == ARM_CPU_MODE_FIQ) {
459 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
460 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
461 } else if (mode == ARM_CPU_MODE_FIQ) {
462 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
463 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
466 i = bank_number(old_mode);
467 env->banked_r13[i] = env->regs[13];
468 env->banked_r14[i] = env->regs[14];
469 env->banked_spsr[i] = env->spsr;
471 i = bank_number(mode);
472 env->regs[13] = env->banked_r13[i];
473 env->regs[14] = env->banked_r14[i];
474 env->spsr = env->banked_spsr[i];
477 static void v7m_push(CPUARMState *env, uint32_t val)
480 stl_phys(env->regs[13], val);
483 static uint32_t v7m_pop(CPUARMState *env)
486 val = ldl_phys(env->regs[13]);
491 /* Switch to V7M main or process stack pointer. */
492 static void switch_v7m_sp(CPUARMState *env, int process)
495 if (env->v7m.current_sp != process) {
496 tmp = env->v7m.other_sp;
497 env->v7m.other_sp = env->regs[13];
499 env->v7m.current_sp = process;
503 static void do_v7m_exception_exit(CPUARMState *env)
508 type = env->regs[15];
509 if (env->v7m.exception != 0)
510 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
512 /* Switch to the target stack. */
513 switch_v7m_sp(env, (type & 4) != 0);
515 env->regs[0] = v7m_pop(env);
516 env->regs[1] = v7m_pop(env);
517 env->regs[2] = v7m_pop(env);
518 env->regs[3] = v7m_pop(env);
519 env->regs[12] = v7m_pop(env);
520 env->regs[14] = v7m_pop(env);
521 env->regs[15] = v7m_pop(env);
523 xpsr_write(env, xpsr, 0xfffffdff);
524 /* Undo stack alignment. */
527 /* ??? The exception return type specifies Thread/Handler mode. However
528 this is also implied by the xPSR value. Not sure what to do
529 if there is a mismatch. */
530 /* ??? Likewise for mismatches between the CONTROL register and the stack
534 void do_interrupt_v7m(CPUARMState *env)
536 uint32_t xpsr = xpsr_read(env);
541 if (env->v7m.current_sp)
543 if (env->v7m.exception == 0)
546 /* For exceptions we just mark as pending on the NVIC, and let that
548 /* TODO: Need to escalate if the current priority is higher than the
549 one we're raising. */
550 switch (env->exception_index) {
552 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
556 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
558 case EXCP_PREFETCH_ABORT:
559 case EXCP_DATA_ABORT:
560 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
563 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
566 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
568 case EXCP_EXCEPTION_EXIT:
569 do_v7m_exception_exit(env);
572 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
573 return; /* Never happens. Keep compiler happy. */
576 /* Align stack pointer. */
577 /* ??? Should only do this if Configuration Control Register
578 STACKALIGN bit is set. */
579 if (env->regs[13] & 4) {
583 /* Switch to the hander mode. */
585 v7m_push(env, env->regs[15]);
586 v7m_push(env, env->regs[14]);
587 v7m_push(env, env->regs[12]);
588 v7m_push(env, env->regs[3]);
589 v7m_push(env, env->regs[2]);
590 v7m_push(env, env->regs[1]);
591 v7m_push(env, env->regs[0]);
592 switch_v7m_sp(env, 0);
593 env->uncached_cpsr &= ~CPSR_IT;
595 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
596 env->regs[15] = addr & 0xfffffffe;
597 env->thumb = addr & 1;
600 /* Handle a CPU exception. */
601 void do_interrupt(CPUARMState *env)
609 do_interrupt_v7m(env);
612 /* TODO: Vectored interrupt controller. */
613 switch (env->exception_index) {
615 new_mode = ARM_CPU_MODE_UND;
624 if (semihosting_enabled) {
625 /* Check for semihosting interrupt. */
627 mask = lduw_code(env->regs[15] - 2) & 0xff;
629 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
631 /* Only intercept calls from privileged modes, to provide some
632 semblance of security. */
633 if (((mask == 0x123456 && !env->thumb)
634 || (mask == 0xab && env->thumb))
635 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
636 env->regs[0] = do_arm_semihosting(env);
640 new_mode = ARM_CPU_MODE_SVC;
643 /* The PC already points to the next instructon. */
647 /* See if this is a semihosting syscall. */
649 mask = lduw_code(env->regs[15]) & 0xff;
651 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
653 env->regs[0] = do_arm_semihosting(env);
657 /* Fall through to prefetch abort. */
658 case EXCP_PREFETCH_ABORT:
659 new_mode = ARM_CPU_MODE_ABT;
661 mask = CPSR_A | CPSR_I;
664 case EXCP_DATA_ABORT:
665 new_mode = ARM_CPU_MODE_ABT;
667 mask = CPSR_A | CPSR_I;
671 new_mode = ARM_CPU_MODE_IRQ;
673 /* Disable IRQ and imprecise data aborts. */
674 mask = CPSR_A | CPSR_I;
678 new_mode = ARM_CPU_MODE_FIQ;
680 /* Disable FIQ, IRQ and imprecise data aborts. */
681 mask = CPSR_A | CPSR_I | CPSR_F;
685 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
686 return; /* Never happens. Keep compiler happy. */
689 if (env->cp15.c1_sys & (1 << 13)) {
692 switch_mode (env, new_mode);
693 env->spsr = cpsr_read(env);
695 env->condexec_bits = 0;
696 /* Switch to the new mode, and switch to Arm mode. */
697 /* ??? Thumb interrupt handlers not implemented. */
698 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
699 env->uncached_cpsr |= mask;
701 env->regs[14] = env->regs[15] + offset;
702 env->regs[15] = addr;
703 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
706 /* Check section/page access permissions.
707 Returns the page protection flags, or zero if the access is not
709 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
715 return PAGE_READ | PAGE_WRITE;
717 if (access_type == 1)
724 if (access_type == 1)
726 switch ((env->cp15.c1_sys >> 8) & 3) {
728 return is_user ? 0 : PAGE_READ;
735 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
740 return PAGE_READ | PAGE_WRITE;
742 return PAGE_READ | PAGE_WRITE;
743 case 4: case 7: /* Reserved. */
746 return is_user ? 0 : prot_ro;
754 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
755 int is_user, uint32_t *phys_ptr, int *prot)
765 /* Pagetable walk. */
766 /* Lookup l1 descriptor. */
767 if (address & env->cp15.c2_mask)
768 table = env->cp15.c2_base1;
770 table = env->cp15.c2_base0;
771 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
772 desc = ldl_phys(table);
774 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
776 /* Secton translation fault. */
780 if (domain == 0 || domain == 2) {
782 code = 9; /* Section domain fault. */
784 code = 11; /* Page domain fault. */
789 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
790 ap = (desc >> 10) & 3;
793 /* Lookup l2 entry. */
795 /* Coarse pagetable. */
796 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
798 /* Fine pagetable. */
799 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
801 desc = ldl_phys(table);
803 case 0: /* Page translation fault. */
806 case 1: /* 64k page. */
807 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
808 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
810 case 2: /* 4k page. */
811 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
812 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
814 case 3: /* 1k page. */
816 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
817 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
819 /* Page translation fault. */
824 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
826 ap = (desc >> 4) & 3;
829 /* Never happens, but compiler isn't smart enough to tell. */
834 *prot = check_ap(env, ap, domain, access_type, is_user);
836 /* Access permission fault. */
839 *phys_ptr = phys_addr;
842 return code | (domain << 4);
845 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
846 int is_user, uint32_t *phys_ptr, int *prot)
857 /* Pagetable walk. */
858 /* Lookup l1 descriptor. */
859 if (address & env->cp15.c2_mask)
860 table = env->cp15.c2_base1;
862 table = env->cp15.c2_base0;
863 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
864 desc = ldl_phys(table);
867 /* Secton translation fault. */
871 } else if (type == 2 && (desc & (1 << 18))) {
875 /* Section or page. */
876 domain = (desc >> 4) & 0x1e;
878 domain = (env->cp15.c3 >> domain) & 3;
879 if (domain == 0 || domain == 2) {
881 code = 9; /* Section domain fault. */
883 code = 11; /* Page domain fault. */
887 if (desc & (1 << 18)) {
889 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
892 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
894 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
895 xn = desc & (1 << 4);
898 /* Lookup l2 entry. */
899 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
900 desc = ldl_phys(table);
901 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
903 case 0: /* Page translation fault. */
906 case 1: /* 64k page. */
907 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
908 xn = desc & (1 << 15);
910 case 2: case 3: /* 4k page. */
911 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
915 /* Never happens, but compiler isn't smart enough to tell. */
920 if (xn && access_type == 2)
923 *prot = check_ap(env, ap, domain, access_type, is_user);
925 /* Access permission fault. */
928 *phys_ptr = phys_addr;
931 return code | (domain << 4);
934 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
935 int is_user, uint32_t *phys_ptr, int *prot)
942 for (n = 7; n >= 0; n--) {
943 base = env->cp15.c6_region[n];
946 mask = 1 << ((base >> 1) & 0x1f);
947 /* Keep this shift separate from the above to avoid an
948 (undefined) << 32. */
949 mask = (mask << 1) - 1;
950 if (((base ^ address) & ~mask) == 0)
956 if (access_type == 2) {
957 mask = env->cp15.c5_insn;
959 mask = env->cp15.c5_data;
961 mask = (mask >> (n * 4)) & 0xf;
968 *prot = PAGE_READ | PAGE_WRITE;
976 *prot = PAGE_READ | PAGE_WRITE;
987 /* Bad permission. */
993 static inline int get_phys_addr(CPUState *env, uint32_t address,
994 int access_type, int is_user,
995 uint32_t *phys_ptr, int *prot)
997 /* Fast Context Switch Extension. */
998 if (address < 0x02000000)
999 address += env->cp15.c13_fcse;
1001 if ((env->cp15.c1_sys & 1) == 0) {
1002 /* MMU/MPU disabled. */
1003 *phys_ptr = address;
1004 *prot = PAGE_READ | PAGE_WRITE;
1006 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1007 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1009 } else if (env->cp15.c1_sys & (1 << 23)) {
1010 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1013 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1018 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1019 int access_type, int mmu_idx, int is_softmmu)
1025 is_user = mmu_idx == MMU_USER_IDX;
1026 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1028 /* Map a single [sub]page. */
1029 phys_addr &= ~(uint32_t)0x3ff;
1030 address &= ~(uint32_t)0x3ff;
1031 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
1035 if (access_type == 2) {
1036 env->cp15.c5_insn = ret;
1037 env->cp15.c6_insn = address;
1038 env->exception_index = EXCP_PREFETCH_ABORT;
1040 env->cp15.c5_data = ret;
1041 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1042 env->cp15.c5_data |= (1 << 11);
1043 env->cp15.c6_data = address;
1044 env->exception_index = EXCP_DATA_ABORT;
1049 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1055 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1063 /* Not really implemented. Need to figure out a sane way of doing this.
1064 Maybe add generic watchpoint support and use that. */
1066 void helper_mark_exclusive(CPUState *env, uint32_t addr)
1068 env->mmon_addr = addr;
1071 int helper_test_exclusive(CPUState *env, uint32_t addr)
1073 return (env->mmon_addr != addr);
1076 void helper_clrex(CPUState *env)
1078 env->mmon_addr = -1;
1081 void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
1083 int cp_num = (insn >> 8) & 0xf;
1084 int cp_info = (insn >> 5) & 7;
1085 int src = (insn >> 16) & 0xf;
1086 int operand = insn & 0xf;
1088 if (env->cp[cp_num].cp_write)
1089 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1090 cp_info, src, operand, val);
1093 uint32_t helper_get_cp(CPUState *env, uint32_t insn)
1095 int cp_num = (insn >> 8) & 0xf;
1096 int cp_info = (insn >> 5) & 7;
1097 int dest = (insn >> 16) & 0xf;
1098 int operand = insn & 0xf;
1100 if (env->cp[cp_num].cp_read)
1101 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1102 cp_info, dest, operand);
1106 /* Return basic MPU access permission bits. */
1107 static uint32_t simple_mpu_ap_bits(uint32_t val)
1114 for (i = 0; i < 16; i += 2) {
1115 ret |= (val >> i) & mask;
1121 /* Pad basic MPU access permission bits to extended format. */
1122 static uint32_t extended_mpu_ap_bits(uint32_t val)
1129 for (i = 0; i < 16; i += 2) {
1130 ret |= (val & mask) << i;
1136 void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
1142 op1 = (insn >> 21) & 7;
1143 op2 = (insn >> 5) & 7;
1145 switch ((insn >> 16) & 0xf) {
1147 if (((insn >> 21) & 7) == 2) {
1148 /* ??? Select cache level. Ignore. */
1152 if (arm_feature(env, ARM_FEATURE_XSCALE))
1154 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1157 case 1: /* System configuration. */
1158 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1162 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1163 env->cp15.c1_sys = val;
1164 /* ??? Lots of these bits are not implemented. */
1165 /* This may enable/disable the MMU, so do a TLB flush. */
1168 case 1: /* Auxiliary cotrol register. */
1169 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1170 env->cp15.c1_xscaleauxcr = val;
1173 /* Not implemented. */
1176 if (arm_feature(env, ARM_FEATURE_XSCALE))
1178 env->cp15.c1_coproc = val;
1179 /* ??? Is this safe when called from within a TB? */
1186 case 2: /* MMU Page table control / MPU cache control. */
1187 if (arm_feature(env, ARM_FEATURE_MPU)) {
1190 env->cp15.c2_data = val;
1193 env->cp15.c2_insn = val;
1201 env->cp15.c2_base0 = val;
1204 env->cp15.c2_base1 = val;
1207 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1214 case 3: /* MMU Domain access control / MPU write buffer control. */
1216 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1218 case 4: /* Reserved. */
1220 case 5: /* MMU Fault status / MPU access permission. */
1221 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1225 if (arm_feature(env, ARM_FEATURE_MPU))
1226 val = extended_mpu_ap_bits(val);
1227 env->cp15.c5_data = val;
1230 if (arm_feature(env, ARM_FEATURE_MPU))
1231 val = extended_mpu_ap_bits(val);
1232 env->cp15.c5_insn = val;
1235 if (!arm_feature(env, ARM_FEATURE_MPU))
1237 env->cp15.c5_data = val;
1240 if (!arm_feature(env, ARM_FEATURE_MPU))
1242 env->cp15.c5_insn = val;
1248 case 6: /* MMU Fault address / MPU base/size. */
1249 if (arm_feature(env, ARM_FEATURE_MPU)) {
1252 env->cp15.c6_region[crm] = val;
1254 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1258 env->cp15.c6_data = val;
1260 case 1: /* ??? This is WFAR on armv6 */
1262 env->cp15.c6_insn = val;
1269 case 7: /* Cache control. */
1270 env->cp15.c15_i_max = 0x000;
1271 env->cp15.c15_i_min = 0xff0;
1272 /* No cache, so nothing to do. */
1273 /* ??? MPCore has VA to PA translation functions. */
1275 case 8: /* MMU TLB control. */
1277 case 0: /* Invalidate all. */
1280 case 1: /* Invalidate single TLB entry. */
1282 /* ??? This is wrong for large pages and sections. */
1283 /* As an ugly hack to make linux work we always flush a 4K
1286 tlb_flush_page(env, val);
1287 tlb_flush_page(env, val + 0x400);
1288 tlb_flush_page(env, val + 0x800);
1289 tlb_flush_page(env, val + 0xc00);
1294 case 2: /* Invalidate on ASID. */
1295 tlb_flush(env, val == 0);
1297 case 3: /* Invalidate single entry on MVA. */
1298 /* ??? This is like case 1, but ignores ASID. */
1306 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1309 case 0: /* Cache lockdown. */
1311 case 0: /* L1 cache. */
1314 env->cp15.c9_data = val;
1317 env->cp15.c9_insn = val;
1323 case 1: /* L2 cache. */
1324 /* Ignore writes to L2 lockdown/auxiliary registers. */
1330 case 1: /* TCM memory region registers. */
1331 /* Not implemented. */
1337 case 10: /* MMU TLB lockdown. */
1338 /* ??? TLB lockdown not implemented. */
1340 case 12: /* Reserved. */
1342 case 13: /* Process ID. */
1345 /* Unlike real hardware the qemu TLB uses virtual addresses,
1346 not modified virtual addresses, so this causes a TLB flush.
1348 if (env->cp15.c13_fcse != val)
1350 env->cp15.c13_fcse = val;
1353 /* This changes the ASID, so do a TLB flush. */
1354 if (env->cp15.c13_context != val
1355 && !arm_feature(env, ARM_FEATURE_MPU))
1357 env->cp15.c13_context = val;
1360 env->cp15.c13_tls1 = val;
1363 env->cp15.c13_tls2 = val;
1366 env->cp15.c13_tls3 = val;
1372 case 14: /* Reserved. */
1374 case 15: /* Implementation specific. */
1375 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1376 if (op2 == 0 && crm == 1) {
1377 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1378 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1380 env->cp15.c15_cpar = val & 0x3fff;
1386 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1390 case 1: /* Set TI925T configuration. */
1391 env->cp15.c15_ticonfig = val & 0xe7;
1392 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1393 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1395 case 2: /* Set I_max. */
1396 env->cp15.c15_i_max = val;
1398 case 3: /* Set I_min. */
1399 env->cp15.c15_i_min = val;
1401 case 4: /* Set thread-ID. */
1402 env->cp15.c15_threadid = val & 0xffff;
1404 case 8: /* Wait-for-interrupt (deprecated). */
1405 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1415 /* ??? For debugging only. Should raise illegal instruction exception. */
1416 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1417 (insn >> 16) & 0xf, crm, op1, op2);
1420 uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
1426 op1 = (insn >> 21) & 7;
1427 op2 = (insn >> 5) & 7;
1429 switch ((insn >> 16) & 0xf) {
1430 case 0: /* ID codes. */
1436 case 0: /* Device ID. */
1437 return env->cp15.c0_cpuid;
1438 case 1: /* Cache Type. */
1439 return env->cp15.c0_cachetype;
1440 case 2: /* TCM status. */
1442 case 3: /* TLB type register. */
1443 return 0; /* No lockable TLB entries. */
1444 case 5: /* CPU ID */
1445 return env->cpu_index;
1450 if (!arm_feature(env, ARM_FEATURE_V6))
1452 return env->cp15.c0_c1[op2];
1454 if (!arm_feature(env, ARM_FEATURE_V6))
1456 return env->cp15.c0_c2[op2];
1457 case 3: case 4: case 5: case 6: case 7:
1463 /* These registers aren't documented on arm11 cores. However
1464 Linux looks at them anyway. */
1465 if (!arm_feature(env, ARM_FEATURE_V6))
1469 if (arm_feature(env, ARM_FEATURE_XSCALE))
1475 case 1: /* System configuration. */
1476 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1479 case 0: /* Control register. */
1480 return env->cp15.c1_sys;
1481 case 1: /* Auxiliary control register. */
1482 if (arm_feature(env, ARM_FEATURE_XSCALE))
1483 return env->cp15.c1_xscaleauxcr;
1484 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1486 switch (ARM_CPUID(env)) {
1487 case ARM_CPUID_ARM1026:
1489 case ARM_CPUID_ARM1136:
1491 case ARM_CPUID_ARM11MPCORE:
1493 case ARM_CPUID_CORTEXA8:
1498 case 2: /* Coprocessor access register. */
1499 if (arm_feature(env, ARM_FEATURE_XSCALE))
1501 return env->cp15.c1_coproc;
1505 case 2: /* MMU Page table control / MPU cache control. */
1506 if (arm_feature(env, ARM_FEATURE_MPU)) {
1509 return env->cp15.c2_data;
1512 return env->cp15.c2_insn;
1520 return env->cp15.c2_base0;
1522 return env->cp15.c2_base1;
1528 mask = env->cp15.c2_mask;
1539 case 3: /* MMU Domain access control / MPU write buffer control. */
1540 return env->cp15.c3;
1541 case 4: /* Reserved. */
1543 case 5: /* MMU Fault status / MPU access permission. */
1544 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1548 if (arm_feature(env, ARM_FEATURE_MPU))
1549 return simple_mpu_ap_bits(env->cp15.c5_data);
1550 return env->cp15.c5_data;
1552 if (arm_feature(env, ARM_FEATURE_MPU))
1553 return simple_mpu_ap_bits(env->cp15.c5_data);
1554 return env->cp15.c5_insn;
1556 if (!arm_feature(env, ARM_FEATURE_MPU))
1558 return env->cp15.c5_data;
1560 if (!arm_feature(env, ARM_FEATURE_MPU))
1562 return env->cp15.c5_insn;
1566 case 6: /* MMU Fault address. */
1567 if (arm_feature(env, ARM_FEATURE_MPU)) {
1570 return env->cp15.c6_region[crm];
1572 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1576 return env->cp15.c6_data;
1578 if (arm_feature(env, ARM_FEATURE_V6)) {
1579 /* Watchpoint Fault Adrress. */
1580 return 0; /* Not implemented. */
1582 /* Instruction Fault Adrress. */
1583 /* Arm9 doesn't have an IFAR, but implementing it anyway
1584 shouldn't do any harm. */
1585 return env->cp15.c6_insn;
1588 if (arm_feature(env, ARM_FEATURE_V6)) {
1589 /* Instruction Fault Adrress. */
1590 return env->cp15.c6_insn;
1598 case 7: /* Cache control. */
1599 /* ??? This is for test, clean and invaidate operations that set the
1600 Z flag. We can't represent N = Z = 1, so it also clears
1601 the N flag. Oh well. */
1604 case 8: /* MMU TLB control. */
1606 case 9: /* Cache lockdown. */
1608 case 0: /* L1 cache. */
1609 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1613 return env->cp15.c9_data;
1615 return env->cp15.c9_insn;
1619 case 1: /* L2 cache */
1622 /* L2 Lockdown and Auxiliary control. */
1627 case 10: /* MMU TLB lockdown. */
1628 /* ??? TLB lockdown not implemented. */
1630 case 11: /* TCM DMA control. */
1631 case 12: /* Reserved. */
1633 case 13: /* Process ID. */
1636 return env->cp15.c13_fcse;
1638 return env->cp15.c13_context;
1640 return env->cp15.c13_tls1;
1642 return env->cp15.c13_tls2;
1644 return env->cp15.c13_tls3;
1648 case 14: /* Reserved. */
1650 case 15: /* Implementation specific. */
1651 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1652 if (op2 == 0 && crm == 1)
1653 return env->cp15.c15_cpar;
1657 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1661 case 1: /* Read TI925T configuration. */
1662 return env->cp15.c15_ticonfig;
1663 case 2: /* Read I_max. */
1664 return env->cp15.c15_i_max;
1665 case 3: /* Read I_min. */
1666 return env->cp15.c15_i_min;
1667 case 4: /* Read thread-ID. */
1668 return env->cp15.c15_threadid;
1669 case 8: /* TI925T_status */
1677 /* ??? For debugging only. Should raise illegal instruction exception. */
1678 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1679 (insn >> 16) & 0xf, crm, op1, op2);
1683 void helper_set_r13_banked(CPUState *env, int mode, uint32_t val)
1685 env->banked_r13[bank_number(mode)] = val;
1688 uint32_t helper_get_r13_banked(CPUState *env, int mode)
1690 return env->banked_r13[bank_number(mode)];
1693 uint32_t helper_v7m_mrs(CPUState *env, int reg)
1697 return xpsr_read(env) & 0xf8000000;
1699 return xpsr_read(env) & 0xf80001ff;
1701 return xpsr_read(env) & 0xff00fc00;
1703 return xpsr_read(env) & 0xff00fdff;
1705 return xpsr_read(env) & 0x000001ff;
1707 return xpsr_read(env) & 0x0700fc00;
1709 return xpsr_read(env) & 0x0700edff;
1711 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1713 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1714 case 16: /* PRIMASK */
1715 return (env->uncached_cpsr & CPSR_I) != 0;
1716 case 17: /* FAULTMASK */
1717 return (env->uncached_cpsr & CPSR_F) != 0;
1718 case 18: /* BASEPRI */
1719 case 19: /* BASEPRI_MAX */
1720 return env->v7m.basepri;
1721 case 20: /* CONTROL */
1722 return env->v7m.control;
1724 /* ??? For debugging only. */
1725 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1730 void helper_v7m_msr(CPUState *env, int reg, uint32_t val)
1734 xpsr_write(env, val, 0xf8000000);
1737 xpsr_write(env, val, 0xf8000000);
1740 xpsr_write(env, val, 0xfe00fc00);
1743 xpsr_write(env, val, 0xfe00fc00);
1746 /* IPSR bits are readonly. */
1749 xpsr_write(env, val, 0x0600fc00);
1752 xpsr_write(env, val, 0x0600fc00);
1755 if (env->v7m.current_sp)
1756 env->v7m.other_sp = val;
1758 env->regs[13] = val;
1761 if (env->v7m.current_sp)
1762 env->regs[13] = val;
1764 env->v7m.other_sp = val;
1766 case 16: /* PRIMASK */
1768 env->uncached_cpsr |= CPSR_I;
1770 env->uncached_cpsr &= ~CPSR_I;
1772 case 17: /* FAULTMASK */
1774 env->uncached_cpsr |= CPSR_F;
1776 env->uncached_cpsr &= ~CPSR_F;
1778 case 18: /* BASEPRI */
1779 env->v7m.basepri = val & 0xff;
1781 case 19: /* BASEPRI_MAX */
1783 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1784 env->v7m.basepri = val;
1786 case 20: /* CONTROL */
1787 env->v7m.control = val & 3;
1788 switch_v7m_sp(env, (val & 2) != 0);
1791 /* ??? For debugging only. */
1792 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1797 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1798 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1801 if (cpnum < 0 || cpnum > 14) {
1802 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1806 env->cp[cpnum].cp_read = cp_read;
1807 env->cp[cpnum].cp_write = cp_write;
1808 env->cp[cpnum].opaque = opaque;