9 static uint32_t cortexa8_cp15_c0_c1[8] =
10 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
12 static uint32_t cortexa8_cp15_c0_c2[8] =
13 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
15 static uint32_t mpcore_cp15_c0_c1[8] =
16 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
18 static uint32_t mpcore_cp15_c0_c2[8] =
19 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
21 static uint32_t arm1136_cp15_c0_c1[8] =
22 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
24 static uint32_t arm1136_cp15_c0_c2[8] =
25 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
27 static uint32_t cpu_arm_find_by_name(const char *name);
29 static inline void set_feature(CPUARMState *env, int feature)
31 env->features |= 1u << feature;
34 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
36 env->cp15.c0_cpuid = id;
38 case ARM_CPUID_ARM926:
39 set_feature(env, ARM_FEATURE_VFP);
40 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
41 env->cp15.c0_cachetype = 0x1dd20d2;
42 env->cp15.c1_sys = 0x00090078;
44 case ARM_CPUID_ARM946:
45 set_feature(env, ARM_FEATURE_MPU);
46 env->cp15.c0_cachetype = 0x0f004006;
47 env->cp15.c1_sys = 0x00000078;
49 case ARM_CPUID_ARM1026:
50 set_feature(env, ARM_FEATURE_VFP);
51 set_feature(env, ARM_FEATURE_AUXCR);
52 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
53 env->cp15.c0_cachetype = 0x1dd20d2;
54 env->cp15.c1_sys = 0x00090078;
56 case ARM_CPUID_ARM1136:
57 set_feature(env, ARM_FEATURE_V6);
58 set_feature(env, ARM_FEATURE_VFP);
59 set_feature(env, ARM_FEATURE_AUXCR);
60 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
61 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
62 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
63 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
64 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
65 env->cp15.c0_cachetype = 0x1dd20d2;
67 case ARM_CPUID_ARM11MPCORE:
68 set_feature(env, ARM_FEATURE_V6);
69 set_feature(env, ARM_FEATURE_V6K);
70 set_feature(env, ARM_FEATURE_VFP);
71 set_feature(env, ARM_FEATURE_AUXCR);
72 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
73 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
74 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
75 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
76 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
77 env->cp15.c0_cachetype = 0x1dd20d2;
79 case ARM_CPUID_CORTEXA8:
80 set_feature(env, ARM_FEATURE_V6);
81 set_feature(env, ARM_FEATURE_V6K);
82 set_feature(env, ARM_FEATURE_V7);
83 set_feature(env, ARM_FEATURE_AUXCR);
84 set_feature(env, ARM_FEATURE_THUMB2);
85 set_feature(env, ARM_FEATURE_VFP);
86 set_feature(env, ARM_FEATURE_VFP3);
87 set_feature(env, ARM_FEATURE_NEON);
88 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
89 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
90 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
91 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
92 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
93 env->cp15.c0_cachetype = 0x1dd20d2;
95 case ARM_CPUID_CORTEXM3:
96 set_feature(env, ARM_FEATURE_V6);
97 set_feature(env, ARM_FEATURE_THUMB2);
98 set_feature(env, ARM_FEATURE_V7);
99 set_feature(env, ARM_FEATURE_M);
100 set_feature(env, ARM_FEATURE_DIV);
102 case ARM_CPUID_ANY: /* For userspace emulation. */
103 set_feature(env, ARM_FEATURE_V6);
104 set_feature(env, ARM_FEATURE_V6K);
105 set_feature(env, ARM_FEATURE_V7);
106 set_feature(env, ARM_FEATURE_THUMB2);
107 set_feature(env, ARM_FEATURE_VFP);
108 set_feature(env, ARM_FEATURE_VFP3);
109 set_feature(env, ARM_FEATURE_NEON);
110 set_feature(env, ARM_FEATURE_DIV);
112 case ARM_CPUID_TI915T:
113 case ARM_CPUID_TI925T:
114 set_feature(env, ARM_FEATURE_OMAPCP);
115 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
116 env->cp15.c0_cachetype = 0x5109149;
117 env->cp15.c1_sys = 0x00000070;
118 env->cp15.c15_i_max = 0x000;
119 env->cp15.c15_i_min = 0xff0;
121 case ARM_CPUID_PXA250:
122 case ARM_CPUID_PXA255:
123 case ARM_CPUID_PXA260:
124 case ARM_CPUID_PXA261:
125 case ARM_CPUID_PXA262:
126 set_feature(env, ARM_FEATURE_XSCALE);
127 /* JTAG_ID is ((id << 28) | 0x09265013) */
128 env->cp15.c0_cachetype = 0xd172172;
129 env->cp15.c1_sys = 0x00000078;
131 case ARM_CPUID_PXA270_A0:
132 case ARM_CPUID_PXA270_A1:
133 case ARM_CPUID_PXA270_B0:
134 case ARM_CPUID_PXA270_B1:
135 case ARM_CPUID_PXA270_C0:
136 case ARM_CPUID_PXA270_C5:
137 set_feature(env, ARM_FEATURE_XSCALE);
138 /* JTAG_ID is ((id << 28) | 0x09265013) */
139 set_feature(env, ARM_FEATURE_IWMMXT);
140 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
141 env->cp15.c0_cachetype = 0xd172172;
142 env->cp15.c1_sys = 0x00000078;
145 cpu_abort(env, "Bad CPU ID: %x\n", id);
150 void cpu_reset(CPUARMState *env)
153 id = env->cp15.c0_cpuid;
154 memset(env, 0, offsetof(CPUARMState, breakpoints));
156 cpu_reset_model_id(env, id);
157 #if defined (CONFIG_USER_ONLY)
158 env->uncached_cpsr = ARM_CPU_MODE_USR;
159 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
161 /* SVC mode with interrupts disabled. */
162 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
163 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
166 env->uncached_cpsr &= ~CPSR_I;
167 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
173 CPUARMState *cpu_arm_init(const char *cpu_model)
178 id = cpu_arm_find_by_name(cpu_model);
181 env = qemu_mallocz(sizeof(CPUARMState));
185 env->cpu_model_str = cpu_model;
186 env->cp15.c0_cpuid = id;
196 static const struct arm_cpu_t arm_cpu_names[] = {
197 { ARM_CPUID_ARM926, "arm926"},
198 { ARM_CPUID_ARM946, "arm946"},
199 { ARM_CPUID_ARM1026, "arm1026"},
200 { ARM_CPUID_ARM1136, "arm1136"},
201 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
202 { ARM_CPUID_CORTEXM3, "cortex-m3"},
203 { ARM_CPUID_CORTEXA8, "cortex-a8"},
204 { ARM_CPUID_TI925T, "ti925t" },
205 { ARM_CPUID_PXA250, "pxa250" },
206 { ARM_CPUID_PXA255, "pxa255" },
207 { ARM_CPUID_PXA260, "pxa260" },
208 { ARM_CPUID_PXA261, "pxa261" },
209 { ARM_CPUID_PXA262, "pxa262" },
210 { ARM_CPUID_PXA270, "pxa270" },
211 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
212 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
213 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
214 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
215 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
216 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
217 { ARM_CPUID_ANY, "any"},
221 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
225 (*cpu_fprintf)(f, "Available CPUs:\n");
226 for (i = 0; arm_cpu_names[i].name; i++) {
227 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
231 /* return 0 if not found */
232 static uint32_t cpu_arm_find_by_name(const char *name)
238 for (i = 0; arm_cpu_names[i].name; i++) {
239 if (strcmp(name, arm_cpu_names[i].name) == 0) {
240 id = arm_cpu_names[i].id;
247 void cpu_arm_close(CPUARMState *env)
252 /* Polynomial multiplication is like integer multiplcation except the
253 partial products are XORed, not added. */
254 uint32_t helper_neon_mul_p8(uint32_t op1, uint32_t op2)
266 mask |= (0xff << 16);
268 mask |= (0xff << 24);
269 result ^= op2 & mask;
270 op1 = (op1 >> 1) & 0x7f7f7f7f;
271 op2 = (op2 << 1) & 0xfefefefe;
276 uint32_t cpsr_read(CPUARMState *env)
279 ZF = (env->NZF == 0);
280 return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
281 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
282 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
283 | ((env->condexec_bits & 0xfc) << 8)
287 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
289 /* NOTE: N = 1 and Z = 1 cannot be stored currently */
290 if (mask & CPSR_NZCV) {
291 env->NZF = (val & 0xc0000000) ^ 0x40000000;
292 env->CF = (val >> 29) & 1;
293 env->VF = (val << 3) & 0x80000000;
296 env->QF = ((val & CPSR_Q) != 0);
298 env->thumb = ((val & CPSR_T) != 0);
299 if (mask & CPSR_IT_0_1) {
300 env->condexec_bits &= ~3;
301 env->condexec_bits |= (val >> 25) & 3;
303 if (mask & CPSR_IT_2_7) {
304 env->condexec_bits &= 3;
305 env->condexec_bits |= (val >> 8) & 0xfc;
307 if (mask & CPSR_GE) {
308 env->GE = (val >> 16) & 0xf;
311 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
312 switch_mode(env, val & CPSR_M);
314 mask &= ~CACHED_CPSR_BITS;
315 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
318 #if defined(CONFIG_USER_ONLY)
320 void do_interrupt (CPUState *env)
322 env->exception_index = -1;
325 /* Structure used to record exclusive memory locations. */
326 typedef struct mmon_state {
327 struct mmon_state *next;
328 CPUARMState *cpu_env;
332 /* Chain of current locks. */
333 static mmon_state* mmon_head = NULL;
335 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
336 int mmu_idx, int is_softmmu)
339 env->exception_index = EXCP_PREFETCH_ABORT;
340 env->cp15.c6_insn = address;
342 env->exception_index = EXCP_DATA_ABORT;
343 env->cp15.c6_data = address;
348 static void allocate_mmon_state(CPUState *env)
350 env->mmon_entry = malloc(sizeof (mmon_state));
351 if (!env->mmon_entry)
353 memset (env->mmon_entry, 0, sizeof (mmon_state));
354 env->mmon_entry->cpu_env = env;
355 mmon_head = env->mmon_entry;
358 /* Flush any monitor locks for the specified address. */
359 static void flush_mmon(uint32_t addr)
363 for (mon = mmon_head; mon; mon = mon->next)
365 if (mon->addr != addr)
373 /* Mark an address for exclusive access. */
374 void helper_mark_exclusive(CPUState *env, uint32_t addr)
376 if (!env->mmon_entry)
377 allocate_mmon_state(env);
378 /* Clear any previous locks. */
380 env->mmon_entry->addr = addr;
383 /* Test if an exclusive address is still exclusive. Returns zero
384 if the address is still exclusive. */
385 int helper_test_exclusive(CPUState *env, uint32_t addr)
389 if (!env->mmon_entry)
391 if (env->mmon_entry->addr == addr)
399 void helper_clrex(CPUState *env)
401 if (!(env->mmon_entry && env->mmon_entry->addr))
403 flush_mmon(env->mmon_entry->addr);
406 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
411 /* These should probably raise undefined insn exceptions. */
412 void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
414 int op1 = (insn >> 8) & 0xf;
415 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
419 uint32_t helper_get_cp(CPUState *env, uint32_t insn)
421 int op1 = (insn >> 8) & 0xf;
422 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
426 void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
428 cpu_abort(env, "cp15 insn %08x\n", insn);
431 uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
433 cpu_abort(env, "cp15 insn %08x\n", insn);
437 /* These should probably raise undefined insn exceptions. */
438 void helper_v7m_msr(CPUState *env, int reg, uint32_t val)
440 cpu_abort(env, "v7m_mrs %d\n", reg);
443 uint32_t helper_v7m_mrs(CPUState *env, int reg)
445 cpu_abort(env, "v7m_mrs %d\n", reg);
449 void switch_mode(CPUState *env, int mode)
451 if (mode != ARM_CPU_MODE_USR)
452 cpu_abort(env, "Tried to switch out of user mode\n");
455 void helper_set_r13_banked(CPUState *env, int mode, uint32_t val)
457 cpu_abort(env, "banked r13 write\n");
460 uint32_t helper_get_r13_banked(CPUState *env, int mode)
462 cpu_abort(env, "banked r13 read\n");
468 extern int semihosting_enabled;
470 /* Map CPU modes onto saved register banks. */
471 static inline int bank_number (int mode)
474 case ARM_CPU_MODE_USR:
475 case ARM_CPU_MODE_SYS:
477 case ARM_CPU_MODE_SVC:
479 case ARM_CPU_MODE_ABT:
481 case ARM_CPU_MODE_UND:
483 case ARM_CPU_MODE_IRQ:
485 case ARM_CPU_MODE_FIQ:
488 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
492 void switch_mode(CPUState *env, int mode)
497 old_mode = env->uncached_cpsr & CPSR_M;
498 if (mode == old_mode)
501 if (old_mode == ARM_CPU_MODE_FIQ) {
502 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
503 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
504 } else if (mode == ARM_CPU_MODE_FIQ) {
505 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
506 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
509 i = bank_number(old_mode);
510 env->banked_r13[i] = env->regs[13];
511 env->banked_r14[i] = env->regs[14];
512 env->banked_spsr[i] = env->spsr;
514 i = bank_number(mode);
515 env->regs[13] = env->banked_r13[i];
516 env->regs[14] = env->banked_r14[i];
517 env->spsr = env->banked_spsr[i];
520 static void v7m_push(CPUARMState *env, uint32_t val)
523 stl_phys(env->regs[13], val);
526 static uint32_t v7m_pop(CPUARMState *env)
529 val = ldl_phys(env->regs[13]);
534 /* Switch to V7M main or process stack pointer. */
535 static void switch_v7m_sp(CPUARMState *env, int process)
538 if (env->v7m.current_sp != process) {
539 tmp = env->v7m.other_sp;
540 env->v7m.other_sp = env->regs[13];
542 env->v7m.current_sp = process;
546 static void do_v7m_exception_exit(CPUARMState *env)
551 type = env->regs[15];
552 if (env->v7m.exception != 0)
553 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
555 /* Switch to the target stack. */
556 switch_v7m_sp(env, (type & 4) != 0);
558 env->regs[0] = v7m_pop(env);
559 env->regs[1] = v7m_pop(env);
560 env->regs[2] = v7m_pop(env);
561 env->regs[3] = v7m_pop(env);
562 env->regs[12] = v7m_pop(env);
563 env->regs[14] = v7m_pop(env);
564 env->regs[15] = v7m_pop(env);
566 xpsr_write(env, xpsr, 0xfffffdff);
567 /* Undo stack alignment. */
570 /* ??? The exception return type specifies Thread/Handler mode. However
571 this is also implied by the xPSR value. Not sure what to do
572 if there is a mismatch. */
573 /* ??? Likewise for mismatches between the CONTROL register and the stack
577 void do_interrupt_v7m(CPUARMState *env)
579 uint32_t xpsr = xpsr_read(env);
584 if (env->v7m.current_sp)
586 if (env->v7m.exception == 0)
589 /* For exceptions we just mark as pending on the NVIC, and let that
591 /* TODO: Need to escalate if the current priority is higher than the
592 one we're raising. */
593 switch (env->exception_index) {
595 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
599 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
601 case EXCP_PREFETCH_ABORT:
602 case EXCP_DATA_ABORT:
603 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
606 if (semihosting_enabled) {
608 nr = lduw_code(env->regs[15]) & 0xff;
611 env->regs[0] = do_arm_semihosting(env);
615 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
618 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
620 case EXCP_EXCEPTION_EXIT:
621 do_v7m_exception_exit(env);
624 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
625 return; /* Never happens. Keep compiler happy. */
628 /* Align stack pointer. */
629 /* ??? Should only do this if Configuration Control Register
630 STACKALIGN bit is set. */
631 if (env->regs[13] & 4) {
635 /* Switch to the hander mode. */
637 v7m_push(env, env->regs[15]);
638 v7m_push(env, env->regs[14]);
639 v7m_push(env, env->regs[12]);
640 v7m_push(env, env->regs[3]);
641 v7m_push(env, env->regs[2]);
642 v7m_push(env, env->regs[1]);
643 v7m_push(env, env->regs[0]);
644 switch_v7m_sp(env, 0);
645 env->uncached_cpsr &= ~CPSR_IT;
647 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
648 env->regs[15] = addr & 0xfffffffe;
649 env->thumb = addr & 1;
652 /* Handle a CPU exception. */
653 void do_interrupt(CPUARMState *env)
661 do_interrupt_v7m(env);
664 /* TODO: Vectored interrupt controller. */
665 switch (env->exception_index) {
667 new_mode = ARM_CPU_MODE_UND;
676 if (semihosting_enabled) {
677 /* Check for semihosting interrupt. */
679 mask = lduw_code(env->regs[15] - 2) & 0xff;
681 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
683 /* Only intercept calls from privileged modes, to provide some
684 semblance of security. */
685 if (((mask == 0x123456 && !env->thumb)
686 || (mask == 0xab && env->thumb))
687 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
688 env->regs[0] = do_arm_semihosting(env);
692 new_mode = ARM_CPU_MODE_SVC;
695 /* The PC already points to the next instructon. */
699 /* See if this is a semihosting syscall. */
700 if (env->thumb && semihosting_enabled) {
701 mask = lduw_code(env->regs[15]) & 0xff;
703 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
705 env->regs[0] = do_arm_semihosting(env);
709 /* Fall through to prefetch abort. */
710 case EXCP_PREFETCH_ABORT:
711 new_mode = ARM_CPU_MODE_ABT;
713 mask = CPSR_A | CPSR_I;
716 case EXCP_DATA_ABORT:
717 new_mode = ARM_CPU_MODE_ABT;
719 mask = CPSR_A | CPSR_I;
723 new_mode = ARM_CPU_MODE_IRQ;
725 /* Disable IRQ and imprecise data aborts. */
726 mask = CPSR_A | CPSR_I;
730 new_mode = ARM_CPU_MODE_FIQ;
732 /* Disable FIQ, IRQ and imprecise data aborts. */
733 mask = CPSR_A | CPSR_I | CPSR_F;
737 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
738 return; /* Never happens. Keep compiler happy. */
741 if (env->cp15.c1_sys & (1 << 13)) {
744 switch_mode (env, new_mode);
745 env->spsr = cpsr_read(env);
747 env->condexec_bits = 0;
748 /* Switch to the new mode, and switch to Arm mode. */
749 /* ??? Thumb interrupt handlers not implemented. */
750 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
751 env->uncached_cpsr |= mask;
753 env->regs[14] = env->regs[15] + offset;
754 env->regs[15] = addr;
755 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
758 /* Check section/page access permissions.
759 Returns the page protection flags, or zero if the access is not
761 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
767 return PAGE_READ | PAGE_WRITE;
769 if (access_type == 1)
776 if (access_type == 1)
778 switch ((env->cp15.c1_sys >> 8) & 3) {
780 return is_user ? 0 : PAGE_READ;
787 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
792 return PAGE_READ | PAGE_WRITE;
794 return PAGE_READ | PAGE_WRITE;
795 case 4: case 7: /* Reserved. */
798 return is_user ? 0 : prot_ro;
806 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
807 int is_user, uint32_t *phys_ptr, int *prot)
817 /* Pagetable walk. */
818 /* Lookup l1 descriptor. */
819 if (address & env->cp15.c2_mask)
820 table = env->cp15.c2_base1;
822 table = env->cp15.c2_base0;
823 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
824 desc = ldl_phys(table);
826 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
828 /* Secton translation fault. */
832 if (domain == 0 || domain == 2) {
834 code = 9; /* Section domain fault. */
836 code = 11; /* Page domain fault. */
841 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
842 ap = (desc >> 10) & 3;
845 /* Lookup l2 entry. */
847 /* Coarse pagetable. */
848 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
850 /* Fine pagetable. */
851 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
853 desc = ldl_phys(table);
855 case 0: /* Page translation fault. */
858 case 1: /* 64k page. */
859 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
860 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
862 case 2: /* 4k page. */
863 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
864 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
866 case 3: /* 1k page. */
868 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
869 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
871 /* Page translation fault. */
876 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
878 ap = (desc >> 4) & 3;
881 /* Never happens, but compiler isn't smart enough to tell. */
886 *prot = check_ap(env, ap, domain, access_type, is_user);
888 /* Access permission fault. */
891 *phys_ptr = phys_addr;
894 return code | (domain << 4);
897 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
898 int is_user, uint32_t *phys_ptr, int *prot)
909 /* Pagetable walk. */
910 /* Lookup l1 descriptor. */
911 if (address & env->cp15.c2_mask)
912 table = env->cp15.c2_base1;
914 table = env->cp15.c2_base0;
915 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
916 desc = ldl_phys(table);
919 /* Secton translation fault. */
923 } else if (type == 2 && (desc & (1 << 18))) {
927 /* Section or page. */
928 domain = (desc >> 4) & 0x1e;
930 domain = (env->cp15.c3 >> domain) & 3;
931 if (domain == 0 || domain == 2) {
933 code = 9; /* Section domain fault. */
935 code = 11; /* Page domain fault. */
939 if (desc & (1 << 18)) {
941 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
944 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
946 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
947 xn = desc & (1 << 4);
950 /* Lookup l2 entry. */
951 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
952 desc = ldl_phys(table);
953 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
955 case 0: /* Page translation fault. */
958 case 1: /* 64k page. */
959 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
960 xn = desc & (1 << 15);
962 case 2: case 3: /* 4k page. */
963 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
967 /* Never happens, but compiler isn't smart enough to tell. */
972 if (xn && access_type == 2)
975 *prot = check_ap(env, ap, domain, access_type, is_user);
977 /* Access permission fault. */
980 *phys_ptr = phys_addr;
983 return code | (domain << 4);
986 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
987 int is_user, uint32_t *phys_ptr, int *prot)
994 for (n = 7; n >= 0; n--) {
995 base = env->cp15.c6_region[n];
998 mask = 1 << ((base >> 1) & 0x1f);
999 /* Keep this shift separate from the above to avoid an
1000 (undefined) << 32. */
1001 mask = (mask << 1) - 1;
1002 if (((base ^ address) & ~mask) == 0)
1008 if (access_type == 2) {
1009 mask = env->cp15.c5_insn;
1011 mask = env->cp15.c5_data;
1013 mask = (mask >> (n * 4)) & 0xf;
1020 *prot = PAGE_READ | PAGE_WRITE;
1025 *prot |= PAGE_WRITE;
1028 *prot = PAGE_READ | PAGE_WRITE;
1039 /* Bad permission. */
1045 static inline int get_phys_addr(CPUState *env, uint32_t address,
1046 int access_type, int is_user,
1047 uint32_t *phys_ptr, int *prot)
1049 /* Fast Context Switch Extension. */
1050 if (address < 0x02000000)
1051 address += env->cp15.c13_fcse;
1053 if ((env->cp15.c1_sys & 1) == 0) {
1054 /* MMU/MPU disabled. */
1055 *phys_ptr = address;
1056 *prot = PAGE_READ | PAGE_WRITE;
1058 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1059 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1061 } else if (env->cp15.c1_sys & (1 << 23)) {
1062 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1065 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1070 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1071 int access_type, int mmu_idx, int is_softmmu)
1077 is_user = mmu_idx == MMU_USER_IDX;
1078 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1080 /* Map a single [sub]page. */
1081 phys_addr &= ~(uint32_t)0x3ff;
1082 address &= ~(uint32_t)0x3ff;
1083 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
1087 if (access_type == 2) {
1088 env->cp15.c5_insn = ret;
1089 env->cp15.c6_insn = address;
1090 env->exception_index = EXCP_PREFETCH_ABORT;
1092 env->cp15.c5_data = ret;
1093 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1094 env->cp15.c5_data |= (1 << 11);
1095 env->cp15.c6_data = address;
1096 env->exception_index = EXCP_DATA_ABORT;
1101 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1107 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1115 /* Not really implemented. Need to figure out a sane way of doing this.
1116 Maybe add generic watchpoint support and use that. */
1118 void helper_mark_exclusive(CPUState *env, uint32_t addr)
1120 env->mmon_addr = addr;
1123 int helper_test_exclusive(CPUState *env, uint32_t addr)
1125 return (env->mmon_addr != addr);
1128 void helper_clrex(CPUState *env)
1130 env->mmon_addr = -1;
1133 void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
1135 int cp_num = (insn >> 8) & 0xf;
1136 int cp_info = (insn >> 5) & 7;
1137 int src = (insn >> 16) & 0xf;
1138 int operand = insn & 0xf;
1140 if (env->cp[cp_num].cp_write)
1141 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1142 cp_info, src, operand, val);
1145 uint32_t helper_get_cp(CPUState *env, uint32_t insn)
1147 int cp_num = (insn >> 8) & 0xf;
1148 int cp_info = (insn >> 5) & 7;
1149 int dest = (insn >> 16) & 0xf;
1150 int operand = insn & 0xf;
1152 if (env->cp[cp_num].cp_read)
1153 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1154 cp_info, dest, operand);
1158 /* Return basic MPU access permission bits. */
1159 static uint32_t simple_mpu_ap_bits(uint32_t val)
1166 for (i = 0; i < 16; i += 2) {
1167 ret |= (val >> i) & mask;
1173 /* Pad basic MPU access permission bits to extended format. */
1174 static uint32_t extended_mpu_ap_bits(uint32_t val)
1181 for (i = 0; i < 16; i += 2) {
1182 ret |= (val & mask) << i;
1188 void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
1194 op1 = (insn >> 21) & 7;
1195 op2 = (insn >> 5) & 7;
1197 switch ((insn >> 16) & 0xf) {
1199 if (((insn >> 21) & 7) == 2) {
1200 /* ??? Select cache level. Ignore. */
1204 if (arm_feature(env, ARM_FEATURE_XSCALE))
1206 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1209 case 1: /* System configuration. */
1210 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1214 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1215 env->cp15.c1_sys = val;
1216 /* ??? Lots of these bits are not implemented. */
1217 /* This may enable/disable the MMU, so do a TLB flush. */
1220 case 1: /* Auxiliary cotrol register. */
1221 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1222 env->cp15.c1_xscaleauxcr = val;
1225 /* Not implemented. */
1228 if (arm_feature(env, ARM_FEATURE_XSCALE))
1230 env->cp15.c1_coproc = val;
1231 /* ??? Is this safe when called from within a TB? */
1238 case 2: /* MMU Page table control / MPU cache control. */
1239 if (arm_feature(env, ARM_FEATURE_MPU)) {
1242 env->cp15.c2_data = val;
1245 env->cp15.c2_insn = val;
1253 env->cp15.c2_base0 = val;
1256 env->cp15.c2_base1 = val;
1259 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1266 case 3: /* MMU Domain access control / MPU write buffer control. */
1268 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1270 case 4: /* Reserved. */
1272 case 5: /* MMU Fault status / MPU access permission. */
1273 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1277 if (arm_feature(env, ARM_FEATURE_MPU))
1278 val = extended_mpu_ap_bits(val);
1279 env->cp15.c5_data = val;
1282 if (arm_feature(env, ARM_FEATURE_MPU))
1283 val = extended_mpu_ap_bits(val);
1284 env->cp15.c5_insn = val;
1287 if (!arm_feature(env, ARM_FEATURE_MPU))
1289 env->cp15.c5_data = val;
1292 if (!arm_feature(env, ARM_FEATURE_MPU))
1294 env->cp15.c5_insn = val;
1300 case 6: /* MMU Fault address / MPU base/size. */
1301 if (arm_feature(env, ARM_FEATURE_MPU)) {
1304 env->cp15.c6_region[crm] = val;
1306 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1310 env->cp15.c6_data = val;
1312 case 1: /* ??? This is WFAR on armv6 */
1314 env->cp15.c6_insn = val;
1321 case 7: /* Cache control. */
1322 env->cp15.c15_i_max = 0x000;
1323 env->cp15.c15_i_min = 0xff0;
1324 /* No cache, so nothing to do. */
1325 /* ??? MPCore has VA to PA translation functions. */
1327 case 8: /* MMU TLB control. */
1329 case 0: /* Invalidate all. */
1332 case 1: /* Invalidate single TLB entry. */
1334 /* ??? This is wrong for large pages and sections. */
1335 /* As an ugly hack to make linux work we always flush a 4K
1338 tlb_flush_page(env, val);
1339 tlb_flush_page(env, val + 0x400);
1340 tlb_flush_page(env, val + 0x800);
1341 tlb_flush_page(env, val + 0xc00);
1346 case 2: /* Invalidate on ASID. */
1347 tlb_flush(env, val == 0);
1349 case 3: /* Invalidate single entry on MVA. */
1350 /* ??? This is like case 1, but ignores ASID. */
1358 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1361 case 0: /* Cache lockdown. */
1363 case 0: /* L1 cache. */
1366 env->cp15.c9_data = val;
1369 env->cp15.c9_insn = val;
1375 case 1: /* L2 cache. */
1376 /* Ignore writes to L2 lockdown/auxiliary registers. */
1382 case 1: /* TCM memory region registers. */
1383 /* Not implemented. */
1389 case 10: /* MMU TLB lockdown. */
1390 /* ??? TLB lockdown not implemented. */
1392 case 12: /* Reserved. */
1394 case 13: /* Process ID. */
1397 /* Unlike real hardware the qemu TLB uses virtual addresses,
1398 not modified virtual addresses, so this causes a TLB flush.
1400 if (env->cp15.c13_fcse != val)
1402 env->cp15.c13_fcse = val;
1405 /* This changes the ASID, so do a TLB flush. */
1406 if (env->cp15.c13_context != val
1407 && !arm_feature(env, ARM_FEATURE_MPU))
1409 env->cp15.c13_context = val;
1412 env->cp15.c13_tls1 = val;
1415 env->cp15.c13_tls2 = val;
1418 env->cp15.c13_tls3 = val;
1424 case 14: /* Reserved. */
1426 case 15: /* Implementation specific. */
1427 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1428 if (op2 == 0 && crm == 1) {
1429 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1430 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1432 env->cp15.c15_cpar = val & 0x3fff;
1438 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1442 case 1: /* Set TI925T configuration. */
1443 env->cp15.c15_ticonfig = val & 0xe7;
1444 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1445 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1447 case 2: /* Set I_max. */
1448 env->cp15.c15_i_max = val;
1450 case 3: /* Set I_min. */
1451 env->cp15.c15_i_min = val;
1453 case 4: /* Set thread-ID. */
1454 env->cp15.c15_threadid = val & 0xffff;
1456 case 8: /* Wait-for-interrupt (deprecated). */
1457 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1467 /* ??? For debugging only. Should raise illegal instruction exception. */
1468 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1469 (insn >> 16) & 0xf, crm, op1, op2);
1472 uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
1478 op1 = (insn >> 21) & 7;
1479 op2 = (insn >> 5) & 7;
1481 switch ((insn >> 16) & 0xf) {
1482 case 0: /* ID codes. */
1488 case 0: /* Device ID. */
1489 return env->cp15.c0_cpuid;
1490 case 1: /* Cache Type. */
1491 return env->cp15.c0_cachetype;
1492 case 2: /* TCM status. */
1494 case 3: /* TLB type register. */
1495 return 0; /* No lockable TLB entries. */
1496 case 5: /* CPU ID */
1497 return env->cpu_index;
1502 if (!arm_feature(env, ARM_FEATURE_V6))
1504 return env->cp15.c0_c1[op2];
1506 if (!arm_feature(env, ARM_FEATURE_V6))
1508 return env->cp15.c0_c2[op2];
1509 case 3: case 4: case 5: case 6: case 7:
1515 /* These registers aren't documented on arm11 cores. However
1516 Linux looks at them anyway. */
1517 if (!arm_feature(env, ARM_FEATURE_V6))
1521 if (arm_feature(env, ARM_FEATURE_XSCALE))
1527 case 1: /* System configuration. */
1528 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1531 case 0: /* Control register. */
1532 return env->cp15.c1_sys;
1533 case 1: /* Auxiliary control register. */
1534 if (arm_feature(env, ARM_FEATURE_XSCALE))
1535 return env->cp15.c1_xscaleauxcr;
1536 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1538 switch (ARM_CPUID(env)) {
1539 case ARM_CPUID_ARM1026:
1541 case ARM_CPUID_ARM1136:
1543 case ARM_CPUID_ARM11MPCORE:
1545 case ARM_CPUID_CORTEXA8:
1550 case 2: /* Coprocessor access register. */
1551 if (arm_feature(env, ARM_FEATURE_XSCALE))
1553 return env->cp15.c1_coproc;
1557 case 2: /* MMU Page table control / MPU cache control. */
1558 if (arm_feature(env, ARM_FEATURE_MPU)) {
1561 return env->cp15.c2_data;
1564 return env->cp15.c2_insn;
1572 return env->cp15.c2_base0;
1574 return env->cp15.c2_base1;
1580 mask = env->cp15.c2_mask;
1591 case 3: /* MMU Domain access control / MPU write buffer control. */
1592 return env->cp15.c3;
1593 case 4: /* Reserved. */
1595 case 5: /* MMU Fault status / MPU access permission. */
1596 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1600 if (arm_feature(env, ARM_FEATURE_MPU))
1601 return simple_mpu_ap_bits(env->cp15.c5_data);
1602 return env->cp15.c5_data;
1604 if (arm_feature(env, ARM_FEATURE_MPU))
1605 return simple_mpu_ap_bits(env->cp15.c5_data);
1606 return env->cp15.c5_insn;
1608 if (!arm_feature(env, ARM_FEATURE_MPU))
1610 return env->cp15.c5_data;
1612 if (!arm_feature(env, ARM_FEATURE_MPU))
1614 return env->cp15.c5_insn;
1618 case 6: /* MMU Fault address. */
1619 if (arm_feature(env, ARM_FEATURE_MPU)) {
1622 return env->cp15.c6_region[crm];
1624 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1628 return env->cp15.c6_data;
1630 if (arm_feature(env, ARM_FEATURE_V6)) {
1631 /* Watchpoint Fault Adrress. */
1632 return 0; /* Not implemented. */
1634 /* Instruction Fault Adrress. */
1635 /* Arm9 doesn't have an IFAR, but implementing it anyway
1636 shouldn't do any harm. */
1637 return env->cp15.c6_insn;
1640 if (arm_feature(env, ARM_FEATURE_V6)) {
1641 /* Instruction Fault Adrress. */
1642 return env->cp15.c6_insn;
1650 case 7: /* Cache control. */
1651 /* ??? This is for test, clean and invaidate operations that set the
1652 Z flag. We can't represent N = Z = 1, so it also clears
1653 the N flag. Oh well. */
1656 case 8: /* MMU TLB control. */
1658 case 9: /* Cache lockdown. */
1660 case 0: /* L1 cache. */
1661 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1665 return env->cp15.c9_data;
1667 return env->cp15.c9_insn;
1671 case 1: /* L2 cache */
1674 /* L2 Lockdown and Auxiliary control. */
1679 case 10: /* MMU TLB lockdown. */
1680 /* ??? TLB lockdown not implemented. */
1682 case 11: /* TCM DMA control. */
1683 case 12: /* Reserved. */
1685 case 13: /* Process ID. */
1688 return env->cp15.c13_fcse;
1690 return env->cp15.c13_context;
1692 return env->cp15.c13_tls1;
1694 return env->cp15.c13_tls2;
1696 return env->cp15.c13_tls3;
1700 case 14: /* Reserved. */
1702 case 15: /* Implementation specific. */
1703 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1704 if (op2 == 0 && crm == 1)
1705 return env->cp15.c15_cpar;
1709 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1713 case 1: /* Read TI925T configuration. */
1714 return env->cp15.c15_ticonfig;
1715 case 2: /* Read I_max. */
1716 return env->cp15.c15_i_max;
1717 case 3: /* Read I_min. */
1718 return env->cp15.c15_i_min;
1719 case 4: /* Read thread-ID. */
1720 return env->cp15.c15_threadid;
1721 case 8: /* TI925T_status */
1729 /* ??? For debugging only. Should raise illegal instruction exception. */
1730 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1731 (insn >> 16) & 0xf, crm, op1, op2);
1735 void helper_set_r13_banked(CPUState *env, int mode, uint32_t val)
1737 env->banked_r13[bank_number(mode)] = val;
1740 uint32_t helper_get_r13_banked(CPUState *env, int mode)
1742 return env->banked_r13[bank_number(mode)];
1745 uint32_t helper_v7m_mrs(CPUState *env, int reg)
1749 return xpsr_read(env) & 0xf8000000;
1751 return xpsr_read(env) & 0xf80001ff;
1753 return xpsr_read(env) & 0xff00fc00;
1755 return xpsr_read(env) & 0xff00fdff;
1757 return xpsr_read(env) & 0x000001ff;
1759 return xpsr_read(env) & 0x0700fc00;
1761 return xpsr_read(env) & 0x0700edff;
1763 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1765 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1766 case 16: /* PRIMASK */
1767 return (env->uncached_cpsr & CPSR_I) != 0;
1768 case 17: /* FAULTMASK */
1769 return (env->uncached_cpsr & CPSR_F) != 0;
1770 case 18: /* BASEPRI */
1771 case 19: /* BASEPRI_MAX */
1772 return env->v7m.basepri;
1773 case 20: /* CONTROL */
1774 return env->v7m.control;
1776 /* ??? For debugging only. */
1777 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1782 void helper_v7m_msr(CPUState *env, int reg, uint32_t val)
1786 xpsr_write(env, val, 0xf8000000);
1789 xpsr_write(env, val, 0xf8000000);
1792 xpsr_write(env, val, 0xfe00fc00);
1795 xpsr_write(env, val, 0xfe00fc00);
1798 /* IPSR bits are readonly. */
1801 xpsr_write(env, val, 0x0600fc00);
1804 xpsr_write(env, val, 0x0600fc00);
1807 if (env->v7m.current_sp)
1808 env->v7m.other_sp = val;
1810 env->regs[13] = val;
1813 if (env->v7m.current_sp)
1814 env->regs[13] = val;
1816 env->v7m.other_sp = val;
1818 case 16: /* PRIMASK */
1820 env->uncached_cpsr |= CPSR_I;
1822 env->uncached_cpsr &= ~CPSR_I;
1824 case 17: /* FAULTMASK */
1826 env->uncached_cpsr |= CPSR_F;
1828 env->uncached_cpsr &= ~CPSR_F;
1830 case 18: /* BASEPRI */
1831 env->v7m.basepri = val & 0xff;
1833 case 19: /* BASEPRI_MAX */
1835 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1836 env->v7m.basepri = val;
1838 case 20: /* CONTROL */
1839 env->v7m.control = val & 3;
1840 switch_v7m_sp(env, (val & 2) != 0);
1843 /* ??? For debugging only. */
1844 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1849 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1850 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1853 if (cpnum < 0 || cpnum > 14) {
1854 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1858 env->cp[cpnum].cp_read = cp_read;
1859 env->cp[cpnum].cp_write = cp_write;
1860 env->cp[cpnum].opaque = opaque;