9 #include "qemu-common.h"
11 static uint32_t cortexa8_cp15_c0_c1[8] =
12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14 static uint32_t cortexa8_cp15_c0_c2[8] =
15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17 static uint32_t cortexa8r2_cp16_c0_c2[8] =
18 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00011142, 0, 0, 0 };
20 static uint32_t mpcore_cp15_c0_c1[8] =
21 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
23 static uint32_t mpcore_cp15_c0_c2[8] =
24 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
26 static uint32_t arm1136_cp15_c0_c1[8] =
27 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
29 static uint32_t arm1136_cp15_c0_c2[8] =
30 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
32 static uint32_t cpu_arm_find_by_name(const char *name);
34 static inline void set_feature(CPUARMState *env, int feature)
36 env->features |= 1u << feature;
39 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
41 env->cp15.c0_cpuid = id;
43 case ARM_CPUID_ARM926:
44 set_feature(env, ARM_FEATURE_VFP);
45 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
46 env->cp15.c0_cachetype = 0x1dd20d2;
47 env->cp15.c1_sys = 0x00090078;
49 case ARM_CPUID_ARM946:
50 set_feature(env, ARM_FEATURE_MPU);
51 env->cp15.c0_cachetype = 0x0f004006;
52 env->cp15.c1_sys = 0x00000078;
54 case ARM_CPUID_ARM1026:
55 set_feature(env, ARM_FEATURE_VFP);
56 set_feature(env, ARM_FEATURE_AUXCR);
57 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
58 env->cp15.c0_cachetype = 0x1dd20d2;
59 env->cp15.c1_sys = 0x00090078;
61 case ARM_CPUID_ARM1136_R2:
62 case ARM_CPUID_ARM1136:
63 set_feature(env, ARM_FEATURE_V6);
64 set_feature(env, ARM_FEATURE_VFP);
65 set_feature(env, ARM_FEATURE_AUXCR);
66 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
67 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
68 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
69 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
70 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
71 env->cp15.c0_cachetype = 0x1dd20d2;
73 case ARM_CPUID_ARM11MPCORE:
74 set_feature(env, ARM_FEATURE_V6);
75 set_feature(env, ARM_FEATURE_V6K);
76 set_feature(env, ARM_FEATURE_VFP);
77 set_feature(env, ARM_FEATURE_AUXCR);
78 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
79 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
80 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
81 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
82 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
83 env->cp15.c0_cachetype = 0x1dd20d2;
85 case ARM_CPUID_CORTEXA8:
86 set_feature(env, ARM_FEATURE_V6);
87 set_feature(env, ARM_FEATURE_V6K);
88 set_feature(env, ARM_FEATURE_V7);
89 set_feature(env, ARM_FEATURE_AUXCR);
90 set_feature(env, ARM_FEATURE_THUMB2);
91 set_feature(env, ARM_FEATURE_VFP);
92 set_feature(env, ARM_FEATURE_VFP3);
93 set_feature(env, ARM_FEATURE_NEON);
94 set_feature(env, ARM_FEATURE_THUMB2EE);
95 set_feature(env, ARM_FEATURE_TRUSTZONE);
96 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
97 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
98 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
99 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
100 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
101 env->cp15.c0_cachetype = 0x82048004;
102 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
103 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
104 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
105 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
107 case ARM_CPUID_CORTEXA8_R2:
108 set_feature(env, ARM_FEATURE_V6);
109 set_feature(env, ARM_FEATURE_V6K);
110 set_feature(env, ARM_FEATURE_V7);
111 set_feature(env, ARM_FEATURE_AUXCR);
112 set_feature(env, ARM_FEATURE_THUMB2);
113 set_feature(env, ARM_FEATURE_VFP);
114 set_feature(env, ARM_FEATURE_VFP3);
115 set_feature(env, ARM_FEATURE_NEON);
116 set_feature(env, ARM_FEATURE_THUMB2EE);
117 set_feature(env, ARM_FEATURE_TRUSTZONE);
118 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c2;
119 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
120 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; /* should be 0x00011111 */
121 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
122 memcpy(env->cp15.c0_c2, cortexa8r2_cp16_c0_c2, 8 * sizeof(uint32_t));
123 env->cp15.c0_cachetype = 0x82048004;
124 env->cp15.c0_clid = (1 << 27) | (2 << 24) | (4 << 3) | 3;
125 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
126 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
127 env->cp15.c0_ccsid[2] = 0xf03fe03a; /* 256k L2 cache. */
129 case ARM_CPUID_CORTEXM3:
130 set_feature(env, ARM_FEATURE_V6);
131 set_feature(env, ARM_FEATURE_THUMB2);
132 set_feature(env, ARM_FEATURE_V7);
133 set_feature(env, ARM_FEATURE_M);
134 set_feature(env, ARM_FEATURE_DIV);
136 case ARM_CPUID_ANY: /* For userspace emulation. */
137 set_feature(env, ARM_FEATURE_V6);
138 set_feature(env, ARM_FEATURE_V6K);
139 set_feature(env, ARM_FEATURE_V7);
140 set_feature(env, ARM_FEATURE_THUMB2);
141 set_feature(env, ARM_FEATURE_VFP);
142 set_feature(env, ARM_FEATURE_VFP3);
143 set_feature(env, ARM_FEATURE_NEON);
144 set_feature(env, ARM_FEATURE_THUMB2EE);
145 set_feature(env, ARM_FEATURE_DIV);
147 case ARM_CPUID_TI915T:
148 case ARM_CPUID_TI925T:
149 set_feature(env, ARM_FEATURE_OMAPCP);
150 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
151 env->cp15.c0_cachetype = 0x5109149;
152 env->cp15.c1_sys = 0x00000070;
153 env->cp15.c15_i_max = 0x000;
154 env->cp15.c15_i_min = 0xff0;
156 case ARM_CPUID_PXA250:
157 case ARM_CPUID_PXA255:
158 case ARM_CPUID_PXA260:
159 case ARM_CPUID_PXA261:
160 case ARM_CPUID_PXA262:
161 set_feature(env, ARM_FEATURE_XSCALE);
162 /* JTAG_ID is ((id << 28) | 0x09265013) */
163 env->cp15.c0_cachetype = 0xd172172;
164 env->cp15.c1_sys = 0x00000078;
166 case ARM_CPUID_PXA270_A0:
167 case ARM_CPUID_PXA270_A1:
168 case ARM_CPUID_PXA270_B0:
169 case ARM_CPUID_PXA270_B1:
170 case ARM_CPUID_PXA270_C0:
171 case ARM_CPUID_PXA270_C5:
172 set_feature(env, ARM_FEATURE_XSCALE);
173 /* JTAG_ID is ((id << 28) | 0x09265013) */
174 set_feature(env, ARM_FEATURE_IWMMXT);
175 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
176 env->cp15.c0_cachetype = 0xd172172;
177 env->cp15.c1_sys = 0x00000078;
180 cpu_abort(env, "Bad CPU ID: %x\n", id);
185 void cpu_reset(CPUARMState *env)
189 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
190 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
191 log_cpu_state(env, 0);
194 id = env->cp15.c0_cpuid;
195 memset(env, 0, offsetof(CPUARMState, breakpoints));
197 cpu_reset_model_id(env, id);
198 #if defined (CONFIG_USER_ONLY)
199 env->uncached_cpsr = ARM_CPU_MODE_USR;
200 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
202 /* SVC mode with interrupts disabled. */
203 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
204 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
207 env->uncached_cpsr &= ~CPSR_I;
208 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
209 env->cp15.c2_base_mask = 0xffffc000u;
215 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
219 /* VFP data registers are always little-endian. */
220 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
222 stfq_le_p(buf, env->vfp.regs[reg]);
225 if (arm_feature(env, ARM_FEATURE_NEON)) {
226 /* Aliases for Q regs. */
229 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
230 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
234 switch (reg - nregs) {
235 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
236 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
237 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
242 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
246 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
248 env->vfp.regs[reg] = ldfq_le_p(buf);
251 if (arm_feature(env, ARM_FEATURE_NEON)) {
254 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
255 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
259 switch (reg - nregs) {
260 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
261 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
262 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;
267 CPUARMState *cpu_arm_init(const char *cpu_model)
271 static int inited = 0;
273 id = cpu_arm_find_by_name(cpu_model);
276 env = qemu_mallocz(sizeof(CPUARMState));
280 arm_translate_init();
283 env->cpu_model_str = cpu_model;
284 env->cp15.c0_cpuid = id;
286 if (arm_feature(env, ARM_FEATURE_NEON)) {
287 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
288 51, "arm-neon.xml", 0);
289 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
290 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
291 35, "arm-vfp3.xml", 0);
292 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
293 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
294 19, "arm-vfp.xml", 0);
304 static const struct arm_cpu_t arm_cpu_names[] = {
305 { ARM_CPUID_ARM926, "arm926"},
306 { ARM_CPUID_ARM946, "arm946"},
307 { ARM_CPUID_ARM1026, "arm1026"},
308 { ARM_CPUID_ARM1136, "arm1136"},
309 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
310 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
311 { ARM_CPUID_CORTEXM3, "cortex-m3"},
312 { ARM_CPUID_CORTEXA8, "cortex-a8"},
313 { ARM_CPUID_CORTEXA8_R2, "cortex-a8-r2"},
314 { ARM_CPUID_TI925T, "ti925t" },
315 { ARM_CPUID_PXA250, "pxa250" },
316 { ARM_CPUID_PXA255, "pxa255" },
317 { ARM_CPUID_PXA260, "pxa260" },
318 { ARM_CPUID_PXA261, "pxa261" },
319 { ARM_CPUID_PXA262, "pxa262" },
320 { ARM_CPUID_PXA270, "pxa270" },
321 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
322 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
323 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
324 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
325 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
326 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
327 { ARM_CPUID_ANY, "any"},
331 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
335 (*cpu_fprintf)(f, "Available CPUs:\n");
336 for (i = 0; arm_cpu_names[i].name; i++) {
337 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
341 /* return 0 if not found */
342 static uint32_t cpu_arm_find_by_name(const char *name)
348 for (i = 0; arm_cpu_names[i].name; i++) {
349 if (strcmp(name, arm_cpu_names[i].name) == 0) {
350 id = arm_cpu_names[i].id;
357 void cpu_arm_close(CPUARMState *env)
362 uint32_t cpsr_read(CPUARMState *env)
366 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
367 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
368 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
369 | ((env->condexec_bits & 0xfc) << 8)
373 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
375 if (mask & CPSR_NZCV) {
376 env->ZF = (~val) & CPSR_Z;
378 env->CF = (val >> 29) & 1;
379 env->VF = (val << 3) & 0x80000000;
382 env->QF = ((val & CPSR_Q) != 0);
384 env->thumb = ((val & CPSR_T) != 0);
385 if (mask & CPSR_IT_0_1) {
386 env->condexec_bits &= ~3;
387 env->condexec_bits |= (val >> 25) & 3;
389 if (mask & CPSR_IT_2_7) {
390 env->condexec_bits &= 3;
391 env->condexec_bits |= (val >> 8) & 0xfc;
393 if (mask & CPSR_GE) {
394 env->GE = (val >> 16) & 0xf;
397 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
398 switch_mode(env, val & CPSR_M);
400 mask &= ~CACHED_CPSR_BITS;
401 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
404 /* Sign/zero extend */
405 uint32_t HELPER(sxtb16)(uint32_t x)
408 res = (uint16_t)(int8_t)x;
409 res |= (uint32_t)(int8_t)(x >> 16) << 16;
413 uint32_t HELPER(uxtb16)(uint32_t x)
416 res = (uint16_t)(uint8_t)x;
417 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
421 uint32_t HELPER(clz)(uint32_t x)
424 for (count = 32; x; count--)
429 int32_t HELPER(sdiv)(int32_t num, int32_t den)
436 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
443 uint32_t HELPER(rbit)(uint32_t x)
445 x = ((x & 0xff000000) >> 24)
446 | ((x & 0x00ff0000) >> 8)
447 | ((x & 0x0000ff00) << 8)
448 | ((x & 0x000000ff) << 24);
449 x = ((x & 0xf0f0f0f0) >> 4)
450 | ((x & 0x0f0f0f0f) << 4);
451 x = ((x & 0x88888888) >> 3)
452 | ((x & 0x44444444) >> 1)
453 | ((x & 0x22222222) << 1)
454 | ((x & 0x11111111) << 3);
458 uint32_t HELPER(abs)(uint32_t x)
460 return ((int32_t)x < 0) ? -x : x;
463 #if defined(CONFIG_USER_ONLY)
465 void do_interrupt (CPUState *env)
467 env->exception_index = -1;
470 /* Structure used to record exclusive memory locations. */
471 typedef struct mmon_state {
472 struct mmon_state *next;
473 CPUARMState *cpu_env;
477 /* Chain of current locks. */
478 static mmon_state* mmon_head = NULL;
480 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
481 int mmu_idx, int is_softmmu)
484 env->exception_index = EXCP_PREFETCH_ABORT;
485 env->cp15.c6_insn = address;
487 env->exception_index = EXCP_DATA_ABORT;
488 env->cp15.c6_data = address;
493 static void allocate_mmon_state(CPUState *env)
495 env->mmon_entry = malloc(sizeof (mmon_state));
496 memset (env->mmon_entry, 0, sizeof (mmon_state));
497 env->mmon_entry->cpu_env = env;
498 mmon_head = env->mmon_entry;
501 /* Flush any monitor locks for the specified address. */
502 static void flush_mmon(uint32_t addr)
506 for (mon = mmon_head; mon; mon = mon->next)
508 if (mon->addr != addr)
516 /* Mark an address for exclusive access. */
517 void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
519 if (!env->mmon_entry)
520 allocate_mmon_state(env);
521 /* Clear any previous locks. */
523 env->mmon_entry->addr = addr;
526 /* Test if an exclusive address is still exclusive. Returns zero
527 if the address is still exclusive. */
528 uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
532 if (!env->mmon_entry)
534 if (env->mmon_entry->addr == addr)
542 void HELPER(clrex)(CPUState *env)
544 if (!(env->mmon_entry && env->mmon_entry->addr))
546 flush_mmon(env->mmon_entry->addr);
549 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
554 /* These should probably raise undefined insn exceptions. */
555 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
557 int op1 = (insn >> 8) & 0xf;
558 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
562 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
564 int op1 = (insn >> 8) & 0xf;
565 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
569 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
571 cpu_abort(env, "cp15 insn %08x\n", insn);
574 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
576 cpu_abort(env, "cp15 insn %08x\n", insn);
580 /* These should probably raise undefined insn exceptions. */
581 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
583 cpu_abort(env, "v7m_mrs %d\n", reg);
586 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
588 cpu_abort(env, "v7m_mrs %d\n", reg);
592 void switch_mode(CPUState *env, int mode)
594 if (mode != ARM_CPU_MODE_USR)
595 cpu_abort(env, "Tried to switch out of user mode\n");
598 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
600 cpu_abort(env, "banked r13 write\n");
603 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
605 cpu_abort(env, "banked r13 read\n");
611 extern int semihosting_enabled;
613 /* Map CPU modes onto saved register banks. */
614 static inline int bank_number (int mode)
617 case ARM_CPU_MODE_USR:
618 case ARM_CPU_MODE_SYS:
620 case ARM_CPU_MODE_SVC:
622 case ARM_CPU_MODE_ABT:
624 case ARM_CPU_MODE_UND:
626 case ARM_CPU_MODE_IRQ:
628 case ARM_CPU_MODE_FIQ:
631 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
635 void switch_mode(CPUState *env, int mode)
640 old_mode = env->uncached_cpsr & CPSR_M;
641 if (mode == old_mode)
644 if (old_mode == ARM_CPU_MODE_FIQ) {
645 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
646 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
647 } else if (mode == ARM_CPU_MODE_FIQ) {
648 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
649 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
652 i = bank_number(old_mode);
653 env->banked_r13[i] = env->regs[13];
654 env->banked_r14[i] = env->regs[14];
655 env->banked_spsr[i] = env->spsr;
657 i = bank_number(mode);
658 env->regs[13] = env->banked_r13[i];
659 env->regs[14] = env->banked_r14[i];
660 env->spsr = env->banked_spsr[i];
663 static void v7m_push(CPUARMState *env, uint32_t val)
666 stl_phys(env->regs[13], val);
669 static uint32_t v7m_pop(CPUARMState *env)
672 val = ldl_phys(env->regs[13]);
677 /* Switch to V7M main or process stack pointer. */
678 static void switch_v7m_sp(CPUARMState *env, int process)
681 if (env->v7m.current_sp != process) {
682 tmp = env->v7m.other_sp;
683 env->v7m.other_sp = env->regs[13];
685 env->v7m.current_sp = process;
689 static void do_v7m_exception_exit(CPUARMState *env)
694 type = env->regs[15];
695 if (env->v7m.exception != 0)
696 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
698 /* Switch to the target stack. */
699 switch_v7m_sp(env, (type & 4) != 0);
701 env->regs[0] = v7m_pop(env);
702 env->regs[1] = v7m_pop(env);
703 env->regs[2] = v7m_pop(env);
704 env->regs[3] = v7m_pop(env);
705 env->regs[12] = v7m_pop(env);
706 env->regs[14] = v7m_pop(env);
707 env->regs[15] = v7m_pop(env);
709 xpsr_write(env, xpsr, 0xfffffdff);
710 /* Undo stack alignment. */
713 /* ??? The exception return type specifies Thread/Handler mode. However
714 this is also implied by the xPSR value. Not sure what to do
715 if there is a mismatch. */
716 /* ??? Likewise for mismatches between the CONTROL register and the stack
720 static void do_interrupt_v7m(CPUARMState *env)
722 uint32_t xpsr = xpsr_read(env);
727 if (env->v7m.current_sp)
729 if (env->v7m.exception == 0)
732 /* For exceptions we just mark as pending on the NVIC, and let that
734 /* TODO: Need to escalate if the current priority is higher than the
735 one we're raising. */
736 switch (env->exception_index) {
738 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
742 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
744 case EXCP_PREFETCH_ABORT:
745 case EXCP_DATA_ABORT:
746 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
749 if (semihosting_enabled) {
751 nr = lduw_code(env->regs[15]) & 0xff;
754 env->regs[0] = do_arm_semihosting(env);
758 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
761 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
763 case EXCP_EXCEPTION_EXIT:
764 do_v7m_exception_exit(env);
767 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
768 return; /* Never happens. Keep compiler happy. */
771 /* Align stack pointer. */
772 /* ??? Should only do this if Configuration Control Register
773 STACKALIGN bit is set. */
774 if (env->regs[13] & 4) {
778 /* Switch to the handler mode. */
780 v7m_push(env, env->regs[15]);
781 v7m_push(env, env->regs[14]);
782 v7m_push(env, env->regs[12]);
783 v7m_push(env, env->regs[3]);
784 v7m_push(env, env->regs[2]);
785 v7m_push(env, env->regs[1]);
786 v7m_push(env, env->regs[0]);
787 switch_v7m_sp(env, 0);
788 env->uncached_cpsr &= ~CPSR_IT;
790 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
791 env->regs[15] = addr & 0xfffffffe;
792 env->thumb = addr & 1;
795 /* Handle a CPU exception. */
796 void do_interrupt(CPUARMState *env)
804 do_interrupt_v7m(env);
807 /* TODO: Vectored interrupt controller. */
808 switch (env->exception_index) {
810 new_mode = ARM_CPU_MODE_UND;
819 if (semihosting_enabled) {
820 /* Check for semihosting interrupt. */
822 mask = lduw_code(env->regs[15] - 2) & 0xff;
824 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
826 /* Only intercept calls from privileged modes, to provide some
827 semblance of security. */
828 if (((mask == 0x123456 && !env->thumb)
829 || (mask == 0xab && env->thumb))
830 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
831 env->regs[0] = do_arm_semihosting(env);
835 new_mode = ARM_CPU_MODE_SVC;
838 /* The PC already points to the next instruction. */
842 /* See if this is a semihosting syscall. */
843 if (env->thumb && semihosting_enabled) {
844 mask = lduw_code(env->regs[15]) & 0xff;
846 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
848 env->regs[0] = do_arm_semihosting(env);
852 /* Fall through to prefetch abort. */
853 case EXCP_PREFETCH_ABORT:
854 new_mode = ARM_CPU_MODE_ABT;
856 mask = CPSR_A | CPSR_I;
859 case EXCP_DATA_ABORT:
860 new_mode = ARM_CPU_MODE_ABT;
862 mask = CPSR_A | CPSR_I;
866 new_mode = ARM_CPU_MODE_IRQ;
868 /* Disable IRQ and imprecise data aborts. */
869 mask = CPSR_A | CPSR_I;
873 new_mode = ARM_CPU_MODE_FIQ;
875 /* Disable FIQ, IRQ and imprecise data aborts. */
876 mask = CPSR_A | CPSR_I | CPSR_F;
880 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
881 return; /* Never happens. Keep compiler happy. */
884 if (env->cp15.c1_sys & (1 << 13)) {
887 switch_mode (env, new_mode);
888 env->spsr = cpsr_read(env);
890 env->condexec_bits = 0;
891 /* Switch to the new mode, and switch to Arm mode. */
892 /* ??? Thumb interrupt handlers not implemented. */
893 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
894 env->uncached_cpsr |= mask;
896 env->regs[14] = env->regs[15] + offset;
897 env->regs[15] = addr;
898 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
901 /* Check section/page access permissions.
902 Returns the page protection flags, or zero if the access is not
904 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
910 return PAGE_READ | PAGE_WRITE;
912 if (access_type == 1)
919 if (access_type == 1)
921 switch ((env->cp15.c1_sys >> 8) & 3) {
923 return is_user ? 0 : PAGE_READ;
930 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
935 return PAGE_READ | PAGE_WRITE;
937 return PAGE_READ | PAGE_WRITE;
938 case 4: /* Reserved. */
941 return is_user ? 0 : prot_ro;
945 if (!arm_feature (env, ARM_FEATURE_V7))
953 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
957 if (address & env->cp15.c2_mask)
958 table = env->cp15.c2_base1 & 0xffffc000;
960 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
962 table |= (address >> 18) & 0x3ffc;
966 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
967 int is_user, uint32_t *phys_ptr, int *prot)
977 /* Pagetable walk. */
978 /* Lookup l1 descriptor. */
979 table = get_level1_table_address(env, address);
980 desc = ldl_phys(table);
982 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
984 /* Section translation fault. */
988 if (domain == 0 || domain == 2) {
990 code = 9; /* Section domain fault. */
992 code = 11; /* Page domain fault. */
997 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
998 ap = (desc >> 10) & 3;
1001 /* Lookup l2 entry. */
1003 /* Coarse pagetable. */
1004 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1006 /* Fine pagetable. */
1007 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1009 desc = ldl_phys(table);
1011 case 0: /* Page translation fault. */
1014 case 1: /* 64k page. */
1015 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1016 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
1018 case 2: /* 4k page. */
1019 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1020 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
1022 case 3: /* 1k page. */
1024 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1025 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1027 /* Page translation fault. */
1032 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1034 ap = (desc >> 4) & 3;
1037 /* Never happens, but compiler isn't smart enough to tell. */
1042 *prot = check_ap(env, ap, domain, access_type, is_user);
1044 /* Access permission fault. */
1047 *phys_ptr = phys_addr;
1050 return code | (domain << 4);
1053 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1054 int is_user, uint32_t *phys_ptr, int *prot)
1065 /* Pagetable walk. */
1066 /* Lookup l1 descriptor. */
1067 table = get_level1_table_address(env, address);
1068 desc = ldl_phys(table);
1071 /* Section translation fault. */
1075 } else if (type == 2 && (desc & (1 << 18))) {
1079 /* Section or page. */
1080 domain = (desc >> 4) & 0x1e;
1082 domain = (env->cp15.c3 >> domain) & 3;
1083 if (domain == 0 || domain == 2) {
1085 code = 9; /* Section domain fault. */
1087 code = 11; /* Page domain fault. */
1091 if (desc & (1 << 18)) {
1093 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
1096 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1098 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1099 xn = desc & (1 << 4);
1102 /* Lookup l2 entry. */
1103 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1104 desc = ldl_phys(table);
1105 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1107 case 0: /* Page translation fault. */
1110 case 1: /* 64k page. */
1111 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1112 xn = desc & (1 << 15);
1114 case 2: case 3: /* 4k page. */
1115 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1119 /* Never happens, but compiler isn't smart enough to tell. */
1124 if (xn && access_type == 2)
1127 /* The simplified model uses AP[0] as an access control bit. */
1128 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1129 /* Access flag fault. */
1130 code = (code == 15) ? 6 : 3;
1133 *prot = check_ap(env, ap, domain, access_type, is_user);
1135 /* Access permission fault. */
1138 *phys_ptr = phys_addr;
1141 return code | (domain << 4);
1144 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1145 int is_user, uint32_t *phys_ptr, int *prot)
1151 *phys_ptr = address;
1152 for (n = 7; n >= 0; n--) {
1153 base = env->cp15.c6_region[n];
1154 if ((base & 1) == 0)
1156 mask = 1 << ((base >> 1) & 0x1f);
1157 /* Keep this shift separate from the above to avoid an
1158 (undefined) << 32. */
1159 mask = (mask << 1) - 1;
1160 if (((base ^ address) & ~mask) == 0)
1166 if (access_type == 2) {
1167 mask = env->cp15.c5_insn;
1169 mask = env->cp15.c5_data;
1171 mask = (mask >> (n * 4)) & 0xf;
1178 *prot = PAGE_READ | PAGE_WRITE;
1183 *prot |= PAGE_WRITE;
1186 *prot = PAGE_READ | PAGE_WRITE;
1197 /* Bad permission. */
1203 static inline int get_phys_addr(CPUState *env, uint32_t address,
1204 int access_type, int is_user,
1205 uint32_t *phys_ptr, int *prot)
1207 /* Fast Context Switch Extension. */
1208 if (address < 0x02000000)
1209 address += env->cp15.c13_fcse;
1211 if ((env->cp15.c1_sys & 1) == 0) {
1212 /* MMU/MPU disabled. */
1213 *phys_ptr = address;
1214 *prot = PAGE_READ | PAGE_WRITE;
1216 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1217 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1219 } else if (env->cp15.c1_sys & (1 << 23)) {
1220 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1223 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1228 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1229 int access_type, int mmu_idx, int is_softmmu)
1235 is_user = mmu_idx == MMU_USER_IDX;
1236 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1238 /* Map a single [sub]page. */
1239 phys_addr &= ~(uint32_t)0x3ff;
1240 address &= ~(uint32_t)0x3ff;
1241 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
1245 if (access_type == 2) {
1246 env->cp15.c5_insn = ret;
1247 env->cp15.c6_insn = address;
1248 env->exception_index = EXCP_PREFETCH_ABORT;
1250 env->cp15.c5_data = ret;
1251 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1252 env->cp15.c5_data |= (1 << 11);
1253 env->cp15.c6_data = address;
1254 env->exception_index = EXCP_DATA_ABORT;
1259 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1265 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1273 /* Not really implemented. Need to figure out a sane way of doing this.
1274 Maybe add generic watchpoint support and use that. */
1276 void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
1278 env->mmon_addr = addr;
1281 uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
1283 return (env->mmon_addr != addr);
1286 void HELPER(clrex)(CPUState *env)
1288 env->mmon_addr = -1;
1291 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1293 int cp_num = (insn >> 8) & 0xf;
1294 int cp_info = (insn >> 5) & 7;
1295 int src = (insn >> 16) & 0xf;
1296 int operand = insn & 0xf;
1298 if (env->cp[cp_num].cp_write)
1299 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1300 cp_info, src, operand, val);
1303 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1305 int cp_num = (insn >> 8) & 0xf;
1306 int cp_info = (insn >> 5) & 7;
1307 int dest = (insn >> 16) & 0xf;
1308 int operand = insn & 0xf;
1310 if (env->cp[cp_num].cp_read)
1311 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1312 cp_info, dest, operand);
1316 /* Return basic MPU access permission bits. */
1317 static uint32_t simple_mpu_ap_bits(uint32_t val)
1324 for (i = 0; i < 16; i += 2) {
1325 ret |= (val >> i) & mask;
1331 /* Pad basic MPU access permission bits to extended format. */
1332 static uint32_t extended_mpu_ap_bits(uint32_t val)
1339 for (i = 0; i < 16; i += 2) {
1340 ret |= (val & mask) << i;
1346 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1352 op1 = (insn >> 21) & 7;
1353 op2 = (insn >> 5) & 7;
1355 switch ((insn >> 16) & 0xf) {
1358 if (arm_feature(env, ARM_FEATURE_XSCALE))
1360 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1362 if (arm_feature(env, ARM_FEATURE_V7)
1363 && op1 == 2 && crm == 0 && op2 == 0) {
1364 env->cp15.c0_cssel = val & 0xf;
1368 case 1: /* System configuration. */
1371 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1375 if (!arm_feature(env, ARM_FEATURE_XSCALE))
1376 env->cp15.c1_sys = val;
1377 /* ??? Lots of these bits are not implemented. */
1378 /* This may enable/disable the MMU, so do a TLB flush. */
1381 case 1: /* Auxiliary cotrol register. */
1382 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1383 env->cp15.c1_xscaleauxcr = val;
1386 /* Not implemented. */
1389 if (arm_feature(env, ARM_FEATURE_XSCALE))
1391 if (env->cp15.c1_coproc != val) {
1392 env->cp15.c1_coproc = val;
1393 /* ??? Is this safe when called from within a TB? */
1402 if (!arm_feature(env, ARM_FEATURE_TRUSTZONE)
1403 || (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
1406 case 0: /* Secure configuration register. */
1407 if (env->cp15.c1_secfg & 1)
1409 env->cp15.c1_secfg = val;
1411 case 1: /* Secure debug enable register. */
1412 if (env->cp15.c1_secfg & 1)
1414 env->cp15.c1_sedbg = val;
1416 case 2: /* Nonsecure access control register. */
1417 if (env->cp15.c1_secfg & 1)
1419 env->cp15.c1_nseac = val;
1429 case 2: /* MMU Page table control / MPU cache control. */
1430 if (arm_feature(env, ARM_FEATURE_MPU)) {
1433 env->cp15.c2_data = val;
1436 env->cp15.c2_insn = val;
1444 env->cp15.c2_base0 = val;
1447 env->cp15.c2_base1 = val;
1451 env->cp15.c2_control = val;
1452 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1453 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1460 case 3: /* MMU Domain access control / MPU write buffer control. */
1462 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1464 case 4: /* Reserved. */
1466 case 5: /* MMU Fault status / MPU access permission. */
1467 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1471 if (arm_feature(env, ARM_FEATURE_MPU))
1472 val = extended_mpu_ap_bits(val);
1473 env->cp15.c5_data = val;
1476 if (arm_feature(env, ARM_FEATURE_MPU))
1477 val = extended_mpu_ap_bits(val);
1478 env->cp15.c5_insn = val;
1481 if (!arm_feature(env, ARM_FEATURE_MPU))
1483 env->cp15.c5_data = val;
1486 if (!arm_feature(env, ARM_FEATURE_MPU))
1488 env->cp15.c5_insn = val;
1494 case 6: /* MMU Fault address / MPU base/size. */
1495 if (arm_feature(env, ARM_FEATURE_MPU)) {
1498 env->cp15.c6_region[crm] = val;
1500 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1504 env->cp15.c6_data = val;
1506 case 1: /* ??? This is WFAR on armv6 */
1508 env->cp15.c6_insn = val;
1515 case 7: /* Cache control. */
1516 env->cp15.c15_i_max = 0x000;
1517 env->cp15.c15_i_min = 0xff0;
1518 /* No cache, so nothing to do. */
1519 /* ??? MPCore has VA to PA translation functions. */
1521 case 8: /* MMU TLB control. */
1523 case 0: /* Invalidate all. */
1526 case 1: /* Invalidate single TLB entry. */
1528 /* ??? This is wrong for large pages and sections. */
1529 /* As an ugly hack to make linux work we always flush a 4K
1532 tlb_flush_page(env, val);
1533 tlb_flush_page(env, val + 0x400);
1534 tlb_flush_page(env, val + 0x800);
1535 tlb_flush_page(env, val + 0xc00);
1540 case 2: /* Invalidate on ASID. */
1541 tlb_flush(env, val == 0);
1543 case 3: /* Invalidate single entry on MVA. */
1544 /* ??? This is like case 1, but ignores ASID. */
1552 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1555 case 0: /* Cache lockdown. */
1557 case 0: /* L1 cache. */
1560 env->cp15.c9_data = val;
1563 env->cp15.c9_insn = val;
1569 case 1: /* L2 cache. */
1570 /* Ignore writes to L2 lockdown/auxiliary registers. */
1576 case 1: /* TCM memory region registers. */
1577 /* Not implemented. */
1583 case 10: /* MMU TLB lockdown. */
1584 /* ??? TLB lockdown not implemented. */
1586 case 12: /* Reserved. */
1588 case 13: /* Process ID. */
1591 /* Unlike real hardware the qemu TLB uses virtual addresses,
1592 not modified virtual addresses, so this causes a TLB flush.
1594 if (env->cp15.c13_fcse != val)
1596 env->cp15.c13_fcse = val;
1599 /* This changes the ASID, so do a TLB flush. */
1600 if (env->cp15.c13_context != val
1601 && !arm_feature(env, ARM_FEATURE_MPU))
1603 env->cp15.c13_context = val;
1606 env->cp15.c13_tls1 = val;
1609 env->cp15.c13_tls2 = val;
1612 env->cp15.c13_tls3 = val;
1618 case 14: /* Reserved. */
1620 case 15: /* Implementation specific. */
1621 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1622 if (op2 == 0 && crm == 1) {
1623 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1624 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1626 env->cp15.c15_cpar = val & 0x3fff;
1632 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1636 case 1: /* Set TI925T configuration. */
1637 env->cp15.c15_ticonfig = val & 0xe7;
1638 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1639 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1641 case 2: /* Set I_max. */
1642 env->cp15.c15_i_max = val;
1644 case 3: /* Set I_min. */
1645 env->cp15.c15_i_min = val;
1647 case 4: /* Set thread-ID. */
1648 env->cp15.c15_threadid = val & 0xffff;
1650 case 8: /* Wait-for-interrupt (deprecated). */
1651 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1661 /* ??? For debugging only. Should raise illegal instruction exception. */
1662 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1663 (insn >> 16) & 0xf, crm, op1, op2);
1666 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1672 op1 = (insn >> 21) & 7;
1673 op2 = (insn >> 5) & 7;
1675 switch ((insn >> 16) & 0xf) {
1676 case 0: /* ID codes. */
1682 case 0: /* Device ID. */
1683 return env->cp15.c0_cpuid;
1684 case 1: /* Cache Type. */
1685 return env->cp15.c0_cachetype;
1686 case 2: /* TCM status. */
1688 case 3: /* TLB type register. */
1689 return 0; /* No lockable TLB entries. */
1690 case 5: /* CPU ID */
1691 return env->cpu_index;
1696 if (!arm_feature(env, ARM_FEATURE_V6))
1698 return env->cp15.c0_c1[op2];
1700 if (!arm_feature(env, ARM_FEATURE_V6))
1702 return env->cp15.c0_c2[op2];
1703 case 3: case 4: case 5: case 6: case 7:
1710 /* These registers aren't documented on arm11 cores. However
1711 Linux looks at them anyway. */
1712 if (!arm_feature(env, ARM_FEATURE_V6))
1716 if (!arm_feature(env, ARM_FEATURE_V7))
1721 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1723 return env->cp15.c0_clid;
1729 if (op2 != 0 || crm != 0)
1731 return env->cp15.c0_cssel;
1736 case 1: /* System configuration. */
1739 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1742 case 0: /* Control register. */
1743 return env->cp15.c1_sys;
1744 case 1: /* Auxiliary control register. */
1745 if (arm_feature(env, ARM_FEATURE_XSCALE))
1746 return env->cp15.c1_xscaleauxcr;
1747 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1749 switch (ARM_CPUID(env)) {
1750 case ARM_CPUID_ARM1026:
1752 case ARM_CPUID_ARM1136:
1753 case ARM_CPUID_ARM1136_R2:
1755 case ARM_CPUID_ARM11MPCORE:
1757 case ARM_CPUID_CORTEXA8:
1758 case ARM_CPUID_CORTEXA8_R2:
1764 case 2: /* Coprocessor access register. */
1765 if (arm_feature(env, ARM_FEATURE_XSCALE))
1767 return env->cp15.c1_coproc;
1773 if (!arm_feature(env, ARM_FEATURE_TRUSTZONE)
1774 || (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
1777 case 0: /* Secure configuration register. */
1778 if (env->cp15.c1_secfg & 1)
1780 return env->cp15.c1_secfg;
1781 case 1: /* Secure debug enable register. */
1782 if (env->cp15.c1_secfg & 1)
1784 return env->cp15.c1_sedbg;
1785 case 2: /* Nonsecure access control register. */
1786 return env->cp15.c1_nseac;
1795 case 2: /* MMU Page table control / MPU cache control. */
1796 if (arm_feature(env, ARM_FEATURE_MPU)) {
1799 return env->cp15.c2_data;
1802 return env->cp15.c2_insn;
1810 return env->cp15.c2_base0;
1812 return env->cp15.c2_base1;
1814 return env->cp15.c2_control;
1819 case 3: /* MMU Domain access control / MPU write buffer control. */
1820 return env->cp15.c3;
1821 case 4: /* Reserved. */
1823 case 5: /* MMU Fault status / MPU access permission. */
1824 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1828 if (arm_feature(env, ARM_FEATURE_MPU))
1829 return simple_mpu_ap_bits(env->cp15.c5_data);
1830 return env->cp15.c5_data;
1832 if (arm_feature(env, ARM_FEATURE_MPU))
1833 return simple_mpu_ap_bits(env->cp15.c5_data);
1834 return env->cp15.c5_insn;
1836 if (!arm_feature(env, ARM_FEATURE_MPU))
1838 return env->cp15.c5_data;
1840 if (!arm_feature(env, ARM_FEATURE_MPU))
1842 return env->cp15.c5_insn;
1846 case 6: /* MMU Fault address. */
1847 if (arm_feature(env, ARM_FEATURE_MPU)) {
1850 return env->cp15.c6_region[crm];
1852 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1856 return env->cp15.c6_data;
1858 if (arm_feature(env, ARM_FEATURE_V6)) {
1859 /* Watchpoint Fault Adrress. */
1860 return 0; /* Not implemented. */
1862 /* Instruction Fault Adrress. */
1863 /* Arm9 doesn't have an IFAR, but implementing it anyway
1864 shouldn't do any harm. */
1865 return env->cp15.c6_insn;
1867 if (arm_feature(env, ARM_FEATURE_V6)) {
1868 /* Instruction Fault Adrress. */
1869 return env->cp15.c6_insn;
1876 case 7: /* Cache control. */
1877 if (((insn >> 12) & 0xf) == 0xf) /* clear ZF only if destination is r15 */
1880 case 8: /* MMU TLB control. */
1882 case 9: /* Cache lockdown. */
1884 case 0: /* L1 cache. */
1885 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1889 return env->cp15.c9_data;
1891 return env->cp15.c9_insn;
1895 case 1: /* L2 cache */
1898 /* L2 Lockdown and Auxiliary control. */
1903 case 10: /* MMU TLB lockdown. */
1904 /* ??? TLB lockdown not implemented. */
1906 case 11: /* TCM DMA control. */
1907 case 12: /* Reserved. */
1909 case 13: /* Process ID. */
1912 return env->cp15.c13_fcse;
1914 return env->cp15.c13_context;
1916 return env->cp15.c13_tls1;
1918 return env->cp15.c13_tls2;
1920 return env->cp15.c13_tls3;
1924 case 14: /* Reserved. */
1926 case 15: /* Implementation specific. */
1927 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1928 if (op2 == 0 && crm == 1)
1929 return env->cp15.c15_cpar;
1933 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1937 case 1: /* Read TI925T configuration. */
1938 return env->cp15.c15_ticonfig;
1939 case 2: /* Read I_max. */
1940 return env->cp15.c15_i_max;
1941 case 3: /* Read I_min. */
1942 return env->cp15.c15_i_min;
1943 case 4: /* Read thread-ID. */
1944 return env->cp15.c15_threadid;
1945 case 8: /* TI925T_status */
1948 /* TODO: Peripheral port remap register:
1949 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1950 * controller base address at $rn & ~0xfff and map size of
1951 * 0x200 << ($rn & 0xfff), when MMU is off. */
1957 /* ??? For debugging only. Should raise illegal instruction exception. */
1958 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1959 (insn >> 16) & 0xf, crm, op1, op2);
1963 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1965 env->banked_r13[bank_number(mode)] = val;
1968 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
1970 return env->banked_r13[bank_number(mode)];
1973 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
1977 return xpsr_read(env) & 0xf8000000;
1979 return xpsr_read(env) & 0xf80001ff;
1981 return xpsr_read(env) & 0xff00fc00;
1983 return xpsr_read(env) & 0xff00fdff;
1985 return xpsr_read(env) & 0x000001ff;
1987 return xpsr_read(env) & 0x0700fc00;
1989 return xpsr_read(env) & 0x0700edff;
1991 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1993 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1994 case 16: /* PRIMASK */
1995 return (env->uncached_cpsr & CPSR_I) != 0;
1996 case 17: /* FAULTMASK */
1997 return (env->uncached_cpsr & CPSR_F) != 0;
1998 case 18: /* BASEPRI */
1999 case 19: /* BASEPRI_MAX */
2000 return env->v7m.basepri;
2001 case 20: /* CONTROL */
2002 return env->v7m.control;
2004 /* ??? For debugging only. */
2005 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2010 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
2014 xpsr_write(env, val, 0xf8000000);
2017 xpsr_write(env, val, 0xf8000000);
2020 xpsr_write(env, val, 0xfe00fc00);
2023 xpsr_write(env, val, 0xfe00fc00);
2026 /* IPSR bits are readonly. */
2029 xpsr_write(env, val, 0x0600fc00);
2032 xpsr_write(env, val, 0x0600fc00);
2035 if (env->v7m.current_sp)
2036 env->v7m.other_sp = val;
2038 env->regs[13] = val;
2041 if (env->v7m.current_sp)
2042 env->regs[13] = val;
2044 env->v7m.other_sp = val;
2046 case 16: /* PRIMASK */
2048 env->uncached_cpsr |= CPSR_I;
2050 env->uncached_cpsr &= ~CPSR_I;
2052 case 17: /* FAULTMASK */
2054 env->uncached_cpsr |= CPSR_F;
2056 env->uncached_cpsr &= ~CPSR_F;
2058 case 18: /* BASEPRI */
2059 env->v7m.basepri = val & 0xff;
2061 case 19: /* BASEPRI_MAX */
2063 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2064 env->v7m.basepri = val;
2066 case 20: /* CONTROL */
2067 env->v7m.control = val & 3;
2068 switch_v7m_sp(env, (val & 2) != 0);
2071 /* ??? For debugging only. */
2072 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2077 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2078 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2081 if (cpnum < 0 || cpnum > 14) {
2082 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2086 env->cp[cpnum].cp_read = cp_read;
2087 env->cp[cpnum].cp_write = cp_write;
2088 env->cp[cpnum].opaque = opaque;
2093 /* Note that signed overflow is undefined in C. The following routines are
2094 careful to use unsigned types where modulo arithmetic is required.
2095 Failure to do so _will_ break on newer gcc. */
2097 /* Signed saturating arithmetic. */
2099 /* Perform 16-bit signed saturating addition. */
2100 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2105 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2114 /* Perform 8-bit signed saturating addition. */
2115 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2120 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2129 /* Perform 16-bit signed saturating subtraction. */
2130 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2135 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2144 /* Perform 8-bit signed saturating subtraction. */
2145 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2150 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2159 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2160 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2161 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2162 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2165 #include "op_addsub.h"
2167 /* Unsigned saturating arithmetic. */
2168 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2177 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2185 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2194 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2202 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2203 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2204 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2205 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2208 #include "op_addsub.h"
2210 /* Signed modulo arithmetic. */
2211 #define SARITH16(a, b, n, op) do { \
2213 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2214 RESULT(sum, n, 16); \
2216 ge |= 3 << (n * 2); \
2219 #define SARITH8(a, b, n, op) do { \
2221 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2222 RESULT(sum, n, 8); \
2228 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2229 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2230 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2231 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2235 #include "op_addsub.h"
2237 /* Unsigned modulo arithmetic. */
2238 #define ADD16(a, b, n) do { \
2240 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2241 RESULT(sum, n, 16); \
2242 if ((sum >> 16) == 1) \
2243 ge |= 3 << (n * 2); \
2246 #define ADD8(a, b, n) do { \
2248 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2249 RESULT(sum, n, 8); \
2250 if ((sum >> 8) == 1) \
2254 #define SUB16(a, b, n) do { \
2256 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2257 RESULT(sum, n, 16); \
2258 if ((sum >> 16) == 0) \
2259 ge |= 3 << (n * 2); \
2262 #define SUB8(a, b, n) do { \
2264 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2265 RESULT(sum, n, 8); \
2266 if ((sum >> 8) == 0) \
2273 #include "op_addsub.h"
2275 /* Halved signed arithmetic. */
2276 #define ADD16(a, b, n) \
2277 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2278 #define SUB16(a, b, n) \
2279 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2280 #define ADD8(a, b, n) \
2281 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2282 #define SUB8(a, b, n) \
2283 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2286 #include "op_addsub.h"
2288 /* Halved unsigned arithmetic. */
2289 #define ADD16(a, b, n) \
2290 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2291 #define SUB16(a, b, n) \
2292 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2293 #define ADD8(a, b, n) \
2294 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2295 #define SUB8(a, b, n) \
2296 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2299 #include "op_addsub.h"
2301 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2309 /* Unsigned sum of absolute byte differences. */
2310 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2313 sum = do_usad(a, b);
2314 sum += do_usad(a >> 8, b >> 8);
2315 sum += do_usad(a >> 16, b >>16);
2316 sum += do_usad(a >> 24, b >> 24);
2320 /* For ARMv6 SEL instruction. */
2321 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2334 return (a & mask) | (b & ~mask);
2337 uint32_t HELPER(logicq_cc)(uint64_t val)
2339 return (val >> 32) | (val != 0);
2342 /* VFP support. We follow the convention used for VFP instrunctions:
2343 Single precition routines have a "s" suffix, double precision a
2346 /* Convert host exception flags to vfp form. */
2347 static inline int vfp_exceptbits_from_host(int host_bits)
2349 int target_bits = 0;
2351 if (host_bits & float_flag_invalid)
2353 if (host_bits & float_flag_divbyzero)
2355 if (host_bits & float_flag_overflow)
2357 if (host_bits & float_flag_underflow)
2359 if (host_bits & float_flag_inexact)
2360 target_bits |= 0x10;
2364 uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2369 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2370 | (env->vfp.vec_len << 16)
2371 | (env->vfp.vec_stride << 20);
2372 i = get_float_exception_flags(&env->vfp.fp_status);
2373 fpscr |= vfp_exceptbits_from_host(i);
2377 /* Convert vfp exception flags to target form. */
2378 static inline int vfp_exceptbits_to_host(int target_bits)
2382 if (target_bits & 1)
2383 host_bits |= float_flag_invalid;
2384 if (target_bits & 2)
2385 host_bits |= float_flag_divbyzero;
2386 if (target_bits & 4)
2387 host_bits |= float_flag_overflow;
2388 if (target_bits & 8)
2389 host_bits |= float_flag_underflow;
2390 if (target_bits & 0x10)
2391 host_bits |= float_flag_inexact;
2395 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2400 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2401 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2402 env->vfp.vec_len = (val >> 16) & 7;
2403 env->vfp.vec_stride = (val >> 20) & 3;
2406 if (changed & (3 << 22)) {
2407 i = (val >> 22) & 3;
2410 i = float_round_nearest_even;
2416 i = float_round_down;
2419 i = float_round_to_zero;
2422 set_float_rounding_mode(i, &env->vfp.fp_status);
2424 if (changed & (1 << 24))
2425 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2426 if (changed & (1 << 25))
2427 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2429 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2430 set_float_exception_flags(i, &env->vfp.fp_status);
2433 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2435 #define VFP_BINOP(name) \
2436 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2438 return float32_ ## name (a, b, &env->vfp.fp_status); \
2440 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2442 return float64_ ## name (a, b, &env->vfp.fp_status); \
2450 float32 VFP_HELPER(neg, s)(float32 a)
2452 return float32_chs(a);
2455 float64 VFP_HELPER(neg, d)(float64 a)
2457 return float64_chs(a);
2460 float32 VFP_HELPER(abs, s)(float32 a)
2462 return float32_abs(a);
2465 float64 VFP_HELPER(abs, d)(float64 a)
2467 return float64_abs(a);
2470 float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2472 return float32_sqrt(a, &env->vfp.fp_status);
2475 float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2477 return float64_sqrt(a, &env->vfp.fp_status);
2480 /* XXX: check quiet/signaling case */
2481 #define DO_VFP_cmp(p, type) \
2482 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2485 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2486 case 0: flags = 0x6; break; \
2487 case -1: flags = 0x8; break; \
2488 case 1: flags = 0x2; break; \
2489 default: case 2: flags = 0x3; break; \
2491 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2492 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2494 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2497 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2498 case 0: flags = 0x6; break; \
2499 case -1: flags = 0x8; break; \
2500 case 1: flags = 0x2; break; \
2501 default: case 2: flags = 0x3; break; \
2503 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2504 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2506 DO_VFP_cmp(s, float32)
2507 DO_VFP_cmp(d, float64)
2510 /* Helper routines to perform bitwise copies between float and int. */
2511 static inline float32 vfp_itos(uint32_t i)
2522 static inline uint32_t vfp_stoi(float32 s)
2533 static inline float64 vfp_itod(uint64_t i)
2544 static inline uint64_t vfp_dtoi(float64 d)
2555 /* Integer to float conversion. */
2556 float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2558 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2561 float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2563 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2566 float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2568 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2571 float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2573 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2576 /* Float to integer conversion. */
2577 float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2579 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2582 float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2584 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2587 float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2589 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2592 float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2594 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2597 float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2599 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2602 float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2604 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2607 float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2609 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2612 float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2614 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2617 /* floating point conversion */
2618 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2620 return float32_to_float64(x, &env->vfp.fp_status);
2623 float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2625 return float64_to_float32(x, &env->vfp.fp_status);
2628 /* VFP3 fixed point conversion. */
2629 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2630 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2633 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2634 &env->vfp.fp_status); \
2635 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2637 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2640 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2641 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2642 &env->vfp.fp_status)); \
2645 VFP_CONV_FIX(sh, d, float64, int16, )
2646 VFP_CONV_FIX(sl, d, float64, int32, )
2647 VFP_CONV_FIX(uh, d, float64, uint16, u)
2648 VFP_CONV_FIX(ul, d, float64, uint32, u)
2649 VFP_CONV_FIX(sh, s, float32, int16, )
2650 VFP_CONV_FIX(sl, s, float32, int32, )
2651 VFP_CONV_FIX(uh, s, float32, uint16, u)
2652 VFP_CONV_FIX(ul, s, float32, uint32, u)
2655 float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2657 float_status *s = &env->vfp.fp_status;
2658 float32 two = int32_to_float32(2, s);
2659 return float32_sub(two, float32_mul(a, b, s), s);
2662 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2664 float_status *s = &env->vfp.fp_status;
2665 float32 three = int32_to_float32(3, s);
2666 return float32_sub(three, float32_mul(a, b, s), s);
2671 /* TODO: The architecture specifies the value that the estimate functions
2672 should return. We return the exact reciprocal/root instead. */
2673 float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2675 float_status *s = &env->vfp.fp_status;
2676 float32 one = int32_to_float32(1, s);
2677 return float32_div(one, a, s);
2680 float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2682 float_status *s = &env->vfp.fp_status;
2683 float32 one = int32_to_float32(1, s);
2684 return float32_div(one, float32_sqrt(a, s), s);
2687 uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2689 float_status *s = &env->vfp.fp_status;
2691 tmp = int32_to_float32(a, s);
2692 tmp = float32_scalbn(tmp, -32, s);
2693 tmp = helper_recpe_f32(tmp, env);
2694 tmp = float32_scalbn(tmp, 31, s);
2695 return float32_to_int32(tmp, s);
2698 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2700 float_status *s = &env->vfp.fp_status;
2702 tmp = int32_to_float32(a, s);
2703 tmp = float32_scalbn(tmp, -32, s);
2704 tmp = helper_rsqrte_f32(tmp, env);
2705 tmp = float32_scalbn(tmp, 31, s);
2706 return float32_to_int32(tmp, s);
2709 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2712 if (env->teecr != val) {