4 void cpu_save(QEMUFile *f, void *opaque)
7 CPUARMState *env = (CPUARMState *)opaque;
9 for (i = 0; i < 16; i++) {
10 qemu_put_be32(f, env->regs[i]);
12 qemu_put_be32(f, cpsr_read(env));
13 qemu_put_be32(f, env->spsr);
14 for (i = 0; i < 6; i++) {
15 qemu_put_be32(f, env->banked_spsr[i]);
16 qemu_put_be32(f, env->banked_r13[i]);
17 qemu_put_be32(f, env->banked_r14[i]);
19 for (i = 0; i < 5; i++) {
20 qemu_put_be32(f, env->usr_regs[i]);
21 qemu_put_be32(f, env->fiq_regs[i]);
23 qemu_put_be32(f, env->cp15.c0_cpuid);
24 qemu_put_be32(f, env->cp15.c0_cachetype);
25 qemu_put_be32(f, env->cp15.c1_sys);
26 qemu_put_be32(f, env->cp15.c1_coproc);
27 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
28 qemu_put_be32(f, env->cp15.c1_secfg);
29 qemu_put_be32(f, env->cp15.c1_sedbg);
30 qemu_put_be32(f, env->cp15.c1_nseac);
31 qemu_put_be32(f, env->cp15.c2_base0);
32 qemu_put_be32(f, env->cp15.c2_base1);
33 qemu_put_be32(f, env->cp15.c2_mask);
34 qemu_put_be32(f, env->cp15.c2_data);
35 qemu_put_be32(f, env->cp15.c2_insn);
36 qemu_put_be32(f, env->cp15.c3);
37 qemu_put_be32(f, env->cp15.c5_insn);
38 qemu_put_be32(f, env->cp15.c5_data);
39 for (i = 0; i < 8; i++) {
40 qemu_put_be32(f, env->cp15.c6_region[i]);
42 qemu_put_be32(f, env->cp15.c6_insn);
43 qemu_put_be32(f, env->cp15.c6_data);
44 qemu_put_be32(f, env->cp15.c9_insn);
45 qemu_put_be32(f, env->cp15.c9_data);
46 qemu_put_be32(f, env->cp15.c13_fcse);
47 qemu_put_be32(f, env->cp15.c13_context);
48 qemu_put_be32(f, env->cp15.c13_tls1);
49 qemu_put_be32(f, env->cp15.c13_tls2);
50 qemu_put_be32(f, env->cp15.c13_tls3);
51 qemu_put_be32(f, env->cp15.c15_cpar);
53 qemu_put_be32(f, env->features);
55 if (arm_feature(env, ARM_FEATURE_VFP)) {
56 for (i = 0; i < 16; i++) {
58 u.d = env->vfp.regs[i];
59 qemu_put_be32(f, u.l.upper);
60 qemu_put_be32(f, u.l.lower);
62 for (i = 0; i < 16; i++) {
63 qemu_put_be32(f, env->vfp.xregs[i]);
66 /* TODO: Should use proper FPSCR access functions. */
67 qemu_put_be32(f, env->vfp.vec_len);
68 qemu_put_be32(f, env->vfp.vec_stride);
70 if (arm_feature(env, ARM_FEATURE_VFP3)) {
71 for (i = 16; i < 32; i++) {
73 u.d = env->vfp.regs[i];
74 qemu_put_be32(f, u.l.upper);
75 qemu_put_be32(f, u.l.lower);
80 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
81 for (i = 0; i < 16; i++) {
82 qemu_put_be64(f, env->iwmmxt.regs[i]);
84 for (i = 0; i < 16; i++) {
85 qemu_put_be32(f, env->iwmmxt.cregs[i]);
89 if (arm_feature(env, ARM_FEATURE_M)) {
90 qemu_put_be32(f, env->v7m.other_sp);
91 qemu_put_be32(f, env->v7m.vecbase);
92 qemu_put_be32(f, env->v7m.basepri);
93 qemu_put_be32(f, env->v7m.control);
94 qemu_put_be32(f, env->v7m.current_sp);
95 qemu_put_be32(f, env->v7m.exception);
99 int cpu_load(QEMUFile *f, void *opaque, int version_id)
101 CPUARMState *env = (CPUARMState *)opaque;
104 if (version_id != CPU_SAVE_VERSION)
107 for (i = 0; i < 16; i++) {
108 env->regs[i] = qemu_get_be32(f);
110 cpsr_write(env, qemu_get_be32(f), 0xffffffff);
111 env->spsr = qemu_get_be32(f);
112 for (i = 0; i < 6; i++) {
113 env->banked_spsr[i] = qemu_get_be32(f);
114 env->banked_r13[i] = qemu_get_be32(f);
115 env->banked_r14[i] = qemu_get_be32(f);
117 for (i = 0; i < 5; i++) {
118 env->usr_regs[i] = qemu_get_be32(f);
119 env->fiq_regs[i] = qemu_get_be32(f);
121 env->cp15.c0_cpuid = qemu_get_be32(f);
122 env->cp15.c0_cachetype = qemu_get_be32(f);
123 env->cp15.c1_sys = qemu_get_be32(f);
124 env->cp15.c1_coproc = qemu_get_be32(f);
125 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
126 env->cp15.c1_secfg = qemu_get_be32(f);
127 env->cp15.c1_sedbg = qemu_get_be32(f);
128 env->cp15.c1_nseac = qemu_get_be32(f);
129 env->cp15.c2_base0 = qemu_get_be32(f);
130 env->cp15.c2_base1 = qemu_get_be32(f);
131 env->cp15.c2_mask = qemu_get_be32(f);
132 env->cp15.c2_data = qemu_get_be32(f);
133 env->cp15.c2_insn = qemu_get_be32(f);
134 env->cp15.c3 = qemu_get_be32(f);
135 env->cp15.c5_insn = qemu_get_be32(f);
136 env->cp15.c5_data = qemu_get_be32(f);
137 for (i = 0; i < 8; i++) {
138 env->cp15.c6_region[i] = qemu_get_be32(f);
140 env->cp15.c6_insn = qemu_get_be32(f);
141 env->cp15.c6_data = qemu_get_be32(f);
142 env->cp15.c9_insn = qemu_get_be32(f);
143 env->cp15.c9_data = qemu_get_be32(f);
144 env->cp15.c13_fcse = qemu_get_be32(f);
145 env->cp15.c13_context = qemu_get_be32(f);
146 env->cp15.c13_tls1 = qemu_get_be32(f);
147 env->cp15.c13_tls2 = qemu_get_be32(f);
148 env->cp15.c13_tls3 = qemu_get_be32(f);
149 env->cp15.c15_cpar = qemu_get_be32(f);
151 env->features = qemu_get_be32(f);
153 if (arm_feature(env, ARM_FEATURE_VFP)) {
154 for (i = 0; i < 16; i++) {
156 u.l.upper = qemu_get_be32(f);
157 u.l.lower = qemu_get_be32(f);
158 env->vfp.regs[i] = u.d;
160 for (i = 0; i < 16; i++) {
161 env->vfp.xregs[i] = qemu_get_be32(f);
164 /* TODO: Should use proper FPSCR access functions. */
165 env->vfp.vec_len = qemu_get_be32(f);
166 env->vfp.vec_stride = qemu_get_be32(f);
168 if (arm_feature(env, ARM_FEATURE_VFP3)) {
169 for (i = 0; i < 16; i++) {
171 u.l.upper = qemu_get_be32(f);
172 u.l.lower = qemu_get_be32(f);
173 env->vfp.regs[i] = u.d;
178 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
179 for (i = 0; i < 16; i++) {
180 env->iwmmxt.regs[i] = qemu_get_be64(f);
182 for (i = 0; i < 16; i++) {
183 env->iwmmxt.cregs[i] = qemu_get_be32(f);
187 if (arm_feature(env, ARM_FEATURE_M)) {
188 env->v7m.other_sp = qemu_get_be32(f);
189 env->v7m.vecbase = qemu_get_be32(f);
190 env->v7m.basepri = qemu_get_be32(f);
191 env->v7m.control = qemu_get_be32(f);
192 env->v7m.current_sp = qemu_get_be32(f);
193 env->v7m.exception = qemu_get_be32(f);