2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #if defined(CONFIG_USER_ONLY)
32 void do_interrupt (CPUState *env)
34 env->exception_index = -1;
37 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
38 int mmu_idx, int is_softmmu)
40 env->exception_index = 0xaa;
41 env->debug1 = address;
42 cpu_dump_state(env, stderr, fprintf, 0);
43 printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc);
47 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
52 #else /* !CONFIG_USER_ONLY */
54 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
55 int mmu_idx, int is_softmmu)
57 struct cris_mmu_result_t res;
61 address &= TARGET_PAGE_MASK;
62 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
63 // printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu);
64 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
67 /* handle the miss. */
69 env->exception_index = EXCP_MMU_MISS;
75 // printf ("a=%x phy=%x\n", address, phy);
76 return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
80 static void cris_shift_ccs(CPUState *env)
83 /* Apply the ccs shift. */
84 ccs = env->pregs[SR_CCS];
85 ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
86 // printf ("ccs=%x %x\n", env->pregs[SR_CCS], ccs);
87 env->pregs[SR_CCS] = ccs;
90 void do_interrupt(CPUState *env)
98 printf ("exception index=%d interrupt_req=%d\n",
100 env->interrupt_request);
103 switch (env->exception_index)
106 // printf ("BREAK! %d\n", env->trapnr);
107 irqnum = env->trapnr;
108 ebp = env->pregs[SR_EBP];
109 isr = ldl_code(ebp + irqnum * 4);
110 env->pregs[SR_ERP] = env->pc + 2;
117 // printf ("MMU miss\n");
119 ebp = env->pregs[SR_EBP];
120 isr = ldl_code(ebp + irqnum * 4);
121 env->pregs[SR_ERP] = env->pc;
128 /* Maybe the irq was acked by sw before we got a
129 change to take it. */
130 if (env->interrupt_request & CPU_INTERRUPT_HARD) {
131 if (!env->pending_interrupts)
133 if (!(env->pregs[SR_CCS] & I_FLAG)) {
138 __builtin_clz(env->pending_interrupts);
140 ebp = env->pregs[SR_EBP];
141 isr = ldl_code(ebp + irqnum * 4);
142 env->pregs[SR_ERP] = env->pc;
147 printf ("%s ebp=%x %x isr=%x %d"
148 " ir=%x pending=%x\n",
150 ebp, ebp + irqnum * 4,
151 isr, env->exception_index,
152 env->interrupt_request,
153 env->pending_interrupts);
162 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
164 // printf ("%s\n", __func__);
166 struct cris_mmu_result_t res;
168 miss = cris_mmu_translate(&res, env, addr, 0, 0);