2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include "host-utils.h"
31 #if defined(CONFIG_USER_ONLY)
33 void do_interrupt (CPUState *env)
35 env->exception_index = -1;
36 env->pregs[PR_ERP] = env->pc;
39 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
40 int mmu_idx, int is_softmmu)
42 env->exception_index = 0xaa;
43 env->debug1 = address;
44 cpu_dump_state(env, stderr, fprintf, 0);
45 env->pregs[PR_ERP] = env->pc;
49 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
54 #else /* !CONFIG_USER_ONLY */
56 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
57 int mmu_idx, int is_softmmu)
59 struct cris_mmu_result_t res;
63 address &= TARGET_PAGE_MASK;
64 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
65 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
68 /* handle the miss. */
70 env->exception_index = EXCP_MMU_MISS;
76 return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
80 static void cris_shift_ccs(CPUState *env)
83 /* Apply the ccs shift. */
84 ccs = env->pregs[PR_CCS];
85 ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
86 env->pregs[PR_CCS] = ccs;
89 void do_interrupt(CPUState *env)
97 printf ("exception index=%d interrupt_req=%d\n",
99 env->interrupt_request);
102 switch (env->exception_index)
105 irqnum = env->trapnr;
106 ebp = env->pregs[PR_EBP];
107 isr = ldl_code(ebp + irqnum * 4);
108 env->pregs[PR_ERP] = env->pc + 2;
116 ebp = env->pregs[PR_EBP];
117 isr = ldl_code(ebp + irqnum * 4);
118 env->pregs[PR_ERP] = env->pc;
125 /* Maybe the irq was acked by sw before we got a
126 change to take it. */
127 if (env->interrupt_request & CPU_INTERRUPT_HARD) {
128 if (!env->pending_interrupts)
130 if (!(env->pregs[PR_CCS] & I_FLAG)) {
134 irqnum = 31 - clz32(env->pending_interrupts);
136 ebp = env->pregs[PR_EBP];
137 isr = ldl_code(ebp + irqnum * 4);
138 env->pregs[PR_ERP] = env->pc;
143 printf ("%s ebp=%x %x isr=%x %d"
144 " ir=%x pending=%x\n",
146 ebp, ebp + irqnum * 4,
147 isr, env->exception_index,
148 env->interrupt_request,
149 env->pending_interrupts);
158 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
161 struct cris_mmu_result_t res;
163 miss = cris_mmu_translate(&res, env, addr, 0, 0);