4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #ifndef CONFIG_USER_ONLY
35 static int cris_mmu_enabled(uint32_t rw_gc_cfg)
37 return (rw_gc_cfg & 12) != 0;
40 static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
42 return (1 << seg) & rw_mm_cfg;
45 static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
51 base = env->sregs[SFR_RW_MM_KBASE_LO];
53 base = env->sregs[SFR_RW_MM_KBASE_HI];
62 /* Used by the tlb decoder. */
63 #define EXTRACT_FIELD(src, start, end) \
64 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66 static inline void set_field(uint32_t *dst, unsigned int val,
67 unsigned int offset, unsigned int width)
71 mask = (1 << width) - 1;
80 static void dump_tlb(CPUState *env, int mmu)
84 uint32_t hi, lo, tlb_vpn, tlb_pfn;
86 for (set = 0; set < 4; set++) {
87 for (idx = 0; idx < 16; idx++) {
88 lo = env->tlbsets[mmu][set][idx].lo;
89 hi = env->tlbsets[mmu][set][idx].hi;
90 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
91 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
93 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
94 set, idx, hi, lo, tlb_vpn, tlb_pfn);
99 /* rw 0 = read, 1 = write, 2 = exec. */
100 static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
101 CPUState *env, uint32_t vaddr,
102 int rw, int usermode)
107 uint32_t tlb_vpn, tlb_pfn = 0;
108 int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
109 int cfg_v, cfg_k, cfg_w, cfg_x;
114 int mmu = 1; /* Data mmu is default. */
117 r_cause = env->sregs[SFR_R_MM_CAUSE];
118 r_cfg = env->sregs[SFR_RW_MM_CFG];
121 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
122 case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
124 case 0: rwcause = CRIS_MMU_ERR_READ; break;
127 /* I exception vectors 4 - 7, D 8 - 11. */
128 vect_base = (mmu + 1) * 4;
132 /* We know the index which to check on each set.
133 Scan both I and D. */
135 for (set = 0; set < 4; set++) {
136 for (idx = 0; idx < 16; idx++) {
137 lo = env->tlbsets[mmu][set][idx].lo;
138 hi = env->tlbsets[mmu][set][idx].hi;
139 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
140 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
142 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
143 set, idx, hi, lo, tlb_vpn, tlb_pfn);
149 for (set = 0; set < 4; set++)
151 lo = env->tlbsets[mmu][set][idx].lo;
152 hi = env->tlbsets[mmu][set][idx].hi;
154 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
155 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
157 D(printf("TLB[%d][%d] v=%x vpage=%x -> pfn=%x lo=%x hi=%x\n",
158 i, idx, tlb_vpn, vpage, tlb_pfn, lo, hi));
159 if (tlb_vpn == vpage) {
165 res->bf_vec = vect_base;
167 cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
168 cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
169 cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
170 cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
172 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
173 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
174 tlb_g = EXTRACT_FIELD(lo, 4, 4);
175 tlb_v = EXTRACT_FIELD(lo, 3, 3);
176 tlb_k = EXTRACT_FIELD(lo, 2, 2);
177 tlb_w = EXTRACT_FIELD(lo, 1, 1);
178 tlb_x = EXTRACT_FIELD(lo, 0, 0);
181 set_exception_vector(0x04, i_mmu_refill);
182 set_exception_vector(0x05, i_mmu_invalid);
183 set_exception_vector(0x06, i_mmu_access);
184 set_exception_vector(0x07, i_mmu_execute);
185 set_exception_vector(0x08, d_mmu_refill);
186 set_exception_vector(0x09, d_mmu_invalid);
187 set_exception_vector(0x0a, d_mmu_access);
188 set_exception_vector(0x0b, d_mmu_write);
191 && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
192 D(printf ("tlb: wrong pid %x %x pc=%x\n",
193 tlb_pid, env->pregs[PR_PID], env->pc));
195 res->bf_vec = vect_base;
196 } else if (rw == 1 && cfg_w && !tlb_w) {
197 D(printf ("tlb: write protected %x lo=%x\n",
200 res->bf_vec = vect_base + 3;
201 } else if (cfg_v && !tlb_v) {
202 D(printf ("tlb: invalid %x\n", vaddr));
203 set_field(&r_cause, rwcause, 8, 9);
205 res->bf_vec = vect_base + 1;
210 res->prot |= PAGE_READ;
212 res->prot |= PAGE_WRITE;
214 res->prot |= PAGE_EXEC;
217 D(dump_tlb(env, mmu));
219 env->sregs[SFR_RW_MM_TLB_HI] = hi;
220 env->sregs[SFR_RW_MM_TLB_LO] = lo;
228 /* Update RW_MM_TLB_SEL. */
229 env->sregs[SFR_RW_MM_TLB_SEL] = 0;
230 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
231 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 5);
233 /* Update RW_MM_CAUSE. */
234 set_field(&r_cause, rwcause, 8, 2);
235 set_field(&r_cause, vpage, 13, 19);
236 set_field(&r_cause, env->pregs[PR_PID], 0, 8);
237 env->sregs[SFR_R_MM_CAUSE] = r_cause;
238 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
242 D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
243 " %x cause=%x sel=%x sp=%x %x %x\n",
244 __func__, rw, match, env->pc,
246 tlb_vpn, tlb_pfn, tlb_pid,
249 env->sregs[SFR_RW_MM_TLB_SEL],
250 env->regs[R_SP], env->pregs[PR_USP], env->ksp));
256 /* Give us the vaddr corresponding to the latest TLB update. */
257 target_ulong cris_mmu_tlb_latest_update(CPUState *env, uint32_t new_lo)
259 uint32_t sel = env->sregs[SFR_RW_MM_TLB_SEL];
265 idx = EXTRACT_FIELD(sel, 0, 4);
266 set = EXTRACT_FIELD(sel, 4, 5);
268 hi = env->tlbsets[1][set][idx].hi;
269 vaddr = EXTRACT_FIELD(hi, 13, 31);
270 return vaddr << TARGET_PAGE_BITS;
273 int cris_mmu_translate(struct cris_mmu_result_t *res,
274 CPUState *env, uint32_t vaddr,
277 uint32_t phy = vaddr;
280 int is_user = mmu_idx == MMU_USER_IDX;
283 old_srs= env->pregs[PR_SRS];
285 /* rw == 2 means exec, map the access to the insn mmu. */
286 env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
288 if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
290 res->prot = PAGE_BITS;
295 if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
300 base = cris_mmu_translate_seg(env, seg);
301 phy = base | (0x0fffffff & vaddr);
303 res->prot = PAGE_BITS;
307 miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
308 phy = (res->pfn << 13);
312 env->pregs[PR_SRS] = old_srs;