2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
96 unsigned int zsize, zzsize;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
108 int clear_x; /* Clear x after this insn? */
110 int user; /* user or kernel mode. */
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
130 cris_prepare_jmp (dc, 0x70000000 + line);
133 const char *regnames[] =
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
140 const char *pregnames[] =
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
148 /* We need this table to handle preg-moves with implicit width. */
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
220 tcg_gen_helper_0_0(helper_tlb_flush);
222 tcg_gen_mov_tl(cpu_PR[r], tn);
226 static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
228 tcg_gen_movi_tl(tn, val);
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
310 /* Extended arithmetics on CRIS. */
311 static inline void t_gen_add_flag(TCGv d, int flag)
315 c = tcg_temp_new(TCG_TYPE_TL);
316 t_gen_mov_TN_preg(c, PR_CCS);
317 /* Propagate carry into d. */
318 tcg_gen_andi_tl(c, c, 1 << flag);
320 tcg_gen_shri_tl(c, c, flag);
321 tcg_gen_add_tl(d, d, c);
322 tcg_gen_discard_tl(c);
325 static inline void t_gen_addx_carry(TCGv d)
329 x = tcg_temp_new(TCG_TYPE_TL);
330 c = tcg_temp_new(TCG_TYPE_TL);
331 t_gen_mov_TN_preg(x, PR_CCS);
332 tcg_gen_mov_tl(c, x);
334 /* Propagate carry into d if X is set. Branch free. */
335 tcg_gen_andi_tl(c, c, C_FLAG);
336 tcg_gen_andi_tl(x, x, X_FLAG);
337 tcg_gen_shri_tl(x, x, 4);
339 tcg_gen_and_tl(x, x, c);
340 tcg_gen_add_tl(d, d, x);
341 tcg_gen_discard_tl(x);
342 tcg_gen_discard_tl(c);
345 static inline void t_gen_subx_carry(TCGv d)
349 x = tcg_temp_new(TCG_TYPE_TL);
350 c = tcg_temp_new(TCG_TYPE_TL);
351 t_gen_mov_TN_preg(x, PR_CCS);
352 tcg_gen_mov_tl(c, x);
354 /* Propagate carry into d if X is set. Branch free. */
355 tcg_gen_andi_tl(c, c, C_FLAG);
356 tcg_gen_andi_tl(x, x, X_FLAG);
357 tcg_gen_shri_tl(x, x, 4);
359 tcg_gen_and_tl(x, x, c);
360 tcg_gen_sub_tl(d, d, x);
361 tcg_gen_discard_tl(x);
362 tcg_gen_discard_tl(c);
365 /* Swap the two bytes within each half word of the s operand.
366 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
367 static inline void t_gen_swapb(TCGv d, TCGv s)
371 t = tcg_temp_new(TCG_TYPE_TL);
372 org_s = tcg_temp_new(TCG_TYPE_TL);
374 /* d and s may refer to the same object. */
375 tcg_gen_mov_tl(org_s, s);
376 tcg_gen_shli_tl(t, org_s, 8);
377 tcg_gen_andi_tl(d, t, 0xff00ff00);
378 tcg_gen_shri_tl(t, org_s, 8);
379 tcg_gen_andi_tl(t, t, 0x00ff00ff);
380 tcg_gen_or_tl(d, d, t);
381 tcg_gen_discard_tl(t);
382 tcg_gen_discard_tl(org_s);
385 /* Swap the halfwords of the s operand. */
386 static inline void t_gen_swapw(TCGv d, TCGv s)
389 /* d and s refer the same object. */
390 t = tcg_temp_new(TCG_TYPE_TL);
391 tcg_gen_mov_tl(t, s);
392 tcg_gen_shli_tl(d, t, 16);
393 tcg_gen_shri_tl(t, t, 16);
394 tcg_gen_or_tl(d, d, t);
395 tcg_gen_discard_tl(t);
398 /* Reverse the within each byte.
399 T0 = (((T0 << 7) & 0x80808080) |
400 ((T0 << 5) & 0x40404040) |
401 ((T0 << 3) & 0x20202020) |
402 ((T0 << 1) & 0x10101010) |
403 ((T0 >> 1) & 0x08080808) |
404 ((T0 >> 3) & 0x04040404) |
405 ((T0 >> 5) & 0x02020202) |
406 ((T0 >> 7) & 0x01010101));
408 static inline void t_gen_swapr(TCGv d, TCGv s)
411 int shift; /* LSL when positive, LSR when negative. */
426 /* d and s refer the same object. */
427 t = tcg_temp_new(TCG_TYPE_TL);
428 org_s = tcg_temp_new(TCG_TYPE_TL);
429 tcg_gen_mov_tl(org_s, s);
431 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
432 tcg_gen_andi_tl(d, t, bitrev[0].mask);
433 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
434 if (bitrev[i].shift >= 0) {
435 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
437 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
439 tcg_gen_andi_tl(t, t, bitrev[i].mask);
440 tcg_gen_or_tl(d, d, t);
442 tcg_gen_discard_tl(t);
443 tcg_gen_discard_tl(org_s);
446 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
448 TranslationBlock *tb;
450 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
452 tcg_gen_movi_tl(env_pc, dest);
453 tcg_gen_exit_tb((long)tb + n);
455 tcg_gen_mov_tl(env_pc, cpu_T[0]);
460 /* Sign extend at translation time. */
461 static int sign_extend(unsigned int val, unsigned int width)
473 static inline void cris_clear_x_flag(DisasContext *dc)
476 || (dc->flagx_live && dc->flags_x)
477 || dc->cc_op != CC_OP_FLAGS)
478 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
483 static void cris_evaluate_flags(DisasContext *dc)
485 if (!dc->flags_live) {
486 tcg_gen_movi_tl(cc_op, dc->cc_op);
487 tcg_gen_movi_tl(cc_size, dc->cc_size);
488 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
493 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
496 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
499 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
505 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
508 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
511 tcg_gen_helper_0_0(helper_evaluate_flags);
523 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
526 tcg_gen_helper_0_0(helper_evaluate_flags);
536 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
540 /* Check if we need to evaluate the condition codes due to
542 ovl = (dc->cc_mask ^ mask) & ~mask;
544 /* TODO: optimize this case. It trigs all the time. */
545 cris_evaluate_flags (dc);
556 static void cris_update_cc_op(DisasContext *dc, int op, int size)
563 /* op is the operation.
564 T0, T1 are the operands.
565 dst is the destination reg.
567 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
571 cris_update_cc_op(dc, op, size);
572 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
574 /* FIXME: This shouldn't be needed. But we don't pass the
575 tests without it. Investigate. */
576 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
577 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
580 /* Emit the ALU insns. */
584 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
585 /* Extended arithmetics. */
586 t_gen_addx_carry(cpu_T[0]);
589 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
590 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
593 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
594 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
597 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
598 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
599 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
600 /* CRIS flag evaluation needs ~src. */
601 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
603 /* Extended arithmetics. */
604 t_gen_subx_carry(cpu_T[0]);
607 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
610 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
613 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
616 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
619 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
622 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
625 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
628 /* Hopefully the TCG backend recognizes this pattern
629 and makes a real neg out of it. */
630 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
631 /* Extended arithmetics. */
632 t_gen_subx_carry(cpu_T[0]);
644 mof = tcg_temp_new(TCG_TYPE_TL);
645 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
646 t_gen_mov_preg_TN(PR_MOF, mof);
647 tcg_gen_discard_tl(mof);
653 mof = tcg_temp_new(TCG_TYPE_TL);
654 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
655 t_gen_mov_preg_TN(PR_MOF, mof);
656 tcg_gen_discard_tl(mof);
660 gen_op_dstep_T0_T1();
665 l1 = gen_new_label();
666 tcg_gen_brcond_tl(TCG_COND_LEU,
667 cpu_T[0], cpu_T[1], l1);
668 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
673 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
674 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
675 /* CRIS flag evaluation needs ~src. */
676 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
677 /* CRIS flag evaluation needs ~src. */
678 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
680 /* Extended arithmetics. */
681 t_gen_subx_carry(cpu_T[0]);
685 fprintf (logfile, "illegal ALU op.\n");
691 tcg_gen_mov_tl(cc_src, cpu_T[1]);
694 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
696 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
701 t_gen_mov_reg_TN(rd, cpu_T[0]);
703 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
704 t_gen_mov_TN_reg(cpu_T[0], rd);
706 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
708 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
709 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
710 t_gen_mov_reg_TN(rd, cpu_T[0]);
711 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
715 tcg_gen_mov_tl(cc_result, cpu_T[0]);
718 /* TODO: Optimize this. */
720 cris_evaluate_flags(dc);
724 static int arith_cc(DisasContext *dc)
728 case CC_OP_ADD: return 1;
729 case CC_OP_SUB: return 1;
730 case CC_OP_LSL: return 1;
731 case CC_OP_LSR: return 1;
732 case CC_OP_ASR: return 1;
733 case CC_OP_CMP: return 1;
741 static void gen_tst_cc (DisasContext *dc, int cond)
745 /* TODO: optimize more condition codes. */
746 arith_opt = arith_cc(dc) && !dc->flags_live;
750 gen_op_tst_cc_eq_fast ();
752 cris_evaluate_flags(dc);
758 gen_op_tst_cc_ne_fast ();
760 cris_evaluate_flags(dc);
765 cris_evaluate_flags(dc);
769 cris_evaluate_flags(dc);
773 cris_evaluate_flags(dc);
777 cris_evaluate_flags(dc);
782 gen_op_tst_cc_pl_fast ();
784 cris_evaluate_flags(dc);
790 gen_op_tst_cc_mi_fast ();
792 cris_evaluate_flags(dc);
797 cris_evaluate_flags(dc);
801 cris_evaluate_flags(dc);
805 cris_evaluate_flags(dc);
809 cris_evaluate_flags(dc);
813 cris_evaluate_flags(dc);
817 cris_evaluate_flags(dc);
821 cris_evaluate_flags(dc);
825 cris_evaluate_flags(dc);
826 gen_op_movl_T0_im (1);
834 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
836 /* This helps us re-schedule the micro-code to insns in delay-slots
837 before the actual jump. */
838 dc->delayed_branch = 2;
839 dc->delayed_pc = dc->pc + offset;
843 gen_tst_cc (dc, cond);
844 gen_op_evaluate_bcc ();
846 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
850 /* Dynamic jumps, when the dest is in a live reg for example. */
851 void cris_prepare_dyn_jmp (DisasContext *dc)
853 /* This helps us re-schedule the micro-code to insns in delay-slots
854 before the actual jump. */
855 dc->delayed_branch = 2;
860 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
862 /* This helps us re-schedule the micro-code to insns in delay-slots
863 before the actual jump. */
864 dc->delayed_branch = 2;
865 dc->delayed_pc = dst;
870 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
871 unsigned int size, int sign)
873 int mem_index = cpu_mmu_index(dc->env);
875 /* FIXME: qemu_ld does not act as a barrier? */
876 tcg_gen_helper_0_0(helper_dummy);
877 cris_evaluate_flags(dc);
880 tcg_gen_qemu_ld8s(dst, addr, mem_index);
882 tcg_gen_qemu_ld8u(dst, addr, mem_index);
884 else if (size == 2) {
886 tcg_gen_qemu_ld16s(dst, addr, mem_index);
888 tcg_gen_qemu_ld16u(dst, addr, mem_index);
891 tcg_gen_qemu_ld32s(dst, addr, mem_index);
895 void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
897 int mem_index = cpu_mmu_index(dc->env);
899 /* FIXME: qemu_st does not act as a barrier? */
900 tcg_gen_helper_0_0(helper_dummy);
901 cris_evaluate_flags(dc);
903 /* Remember, operands are flipped. CRIS has reversed order. */
905 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
907 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
909 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
912 static inline void t_gen_sext(TCGv d, TCGv s, int size)
915 tcg_gen_ext8s_i32(d, s);
917 tcg_gen_ext16s_i32(d, s);
919 tcg_gen_mov_tl(d, s);
922 static inline void t_gen_zext(TCGv d, TCGv s, int size)
924 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
926 tcg_gen_andi_i32(d, s, 0xff);
928 tcg_gen_andi_i32(d, s, 0xffff);
930 tcg_gen_mov_tl(d, s);
934 static char memsize_char(int size)
938 case 1: return 'b'; break;
939 case 2: return 'w'; break;
940 case 4: return 'd'; break;
948 static unsigned int memsize_z(DisasContext *dc)
950 return dc->zsize + 1;
953 static unsigned int memsize_zz(DisasContext *dc)
964 static inline void do_postinc (DisasContext *dc, int size)
967 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
971 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
975 t_gen_sext(cpu_T[1], cpu_R[rs], size);
977 t_gen_zext(cpu_T[1], cpu_R[rs], size);
980 /* Prepare T0 and T1 for a register alu operation.
981 s_ext decides if the operand1 should be sign-extended or zero-extended when
983 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
986 dec_prep_move_r(dc, rs, rd, size, s_ext);
989 t_gen_sext(cpu_T[0], cpu_R[rd], size);
991 t_gen_zext(cpu_T[0], cpu_R[rd], size);
994 /* Prepare T0 and T1 for a memory + alu operation.
995 s_ext decides if the operand1 should be sign-extended or zero-extended when
997 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1006 is_imm = rs == 15 && dc->postinc;
1008 /* Load [$rs] onto T1. */
1010 insn_len = 2 + memsize;
1014 imm = ldl_code(dc->pc + 2);
1017 imm = sign_extend(imm, (memsize * 8) - 1);
1025 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1026 imm, rd, s_ext, memsize));
1027 tcg_gen_movi_tl(cpu_T[1], imm);
1030 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1032 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1034 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1037 /* put dest in T0. */
1038 t_gen_mov_TN_reg(cpu_T[0], rd);
1043 static const char *cc_name(int cc)
1045 static char *cc_names[16] = {
1046 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1047 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1050 return cc_names[cc];
1054 /* Start of insn decoders. */
1056 static unsigned int dec_bccq(DisasContext *dc)
1060 uint32_t cond = dc->op2;
1063 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1064 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1067 offset |= sign << 8;
1069 offset = sign_extend(offset, 8);
1071 /* op2 holds the condition-code. */
1072 cris_cc_mask(dc, 0);
1073 cris_prepare_cc_branch (dc, offset, cond);
1076 static unsigned int dec_addoq(DisasContext *dc)
1080 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1081 imm = sign_extend(dc->op1, 7);
1083 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1084 cris_cc_mask(dc, 0);
1085 /* Fetch register operand, */
1086 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1089 static unsigned int dec_addq(DisasContext *dc)
1091 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1093 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1095 cris_cc_mask(dc, CC_MASK_NZVC);
1096 /* Fetch register operand, */
1097 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1098 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1099 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1102 static unsigned int dec_moveq(DisasContext *dc)
1106 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1107 imm = sign_extend(dc->op1, 5);
1108 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1110 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1113 static unsigned int dec_subq(DisasContext *dc)
1115 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1117 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1119 cris_cc_mask(dc, CC_MASK_NZVC);
1120 /* Fetch register operand, */
1121 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1122 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1123 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1126 static unsigned int dec_cmpq(DisasContext *dc)
1129 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1130 imm = sign_extend(dc->op1, 5);
1132 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1133 cris_cc_mask(dc, CC_MASK_NZVC);
1134 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1135 t_gen_mov_TN_im(cpu_T[1], imm);
1136 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1139 static unsigned int dec_andq(DisasContext *dc)
1142 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1143 imm = sign_extend(dc->op1, 5);
1145 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1146 cris_cc_mask(dc, CC_MASK_NZ);
1147 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1148 t_gen_mov_TN_im(cpu_T[1], imm);
1149 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1152 static unsigned int dec_orq(DisasContext *dc)
1155 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1156 imm = sign_extend(dc->op1, 5);
1157 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1158 cris_cc_mask(dc, CC_MASK_NZ);
1159 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1160 t_gen_mov_TN_im(cpu_T[1], imm);
1161 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1164 static unsigned int dec_btstq(DisasContext *dc)
1166 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1167 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1168 cris_cc_mask(dc, CC_MASK_NZ);
1169 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1170 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1171 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1173 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1174 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1178 static unsigned int dec_asrq(DisasContext *dc)
1180 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1181 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1182 cris_cc_mask(dc, CC_MASK_NZ);
1183 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1184 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1185 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1188 static unsigned int dec_lslq(DisasContext *dc)
1190 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1191 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1193 cris_cc_mask(dc, CC_MASK_NZ);
1194 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1195 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1196 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1199 static unsigned int dec_lsrq(DisasContext *dc)
1201 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1202 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1204 cris_cc_mask(dc, CC_MASK_NZ);
1205 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1206 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1207 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1211 static unsigned int dec_move_r(DisasContext *dc)
1213 int size = memsize_zz(dc);
1215 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1216 memsize_char(size), dc->op1, dc->op2));
1218 cris_cc_mask(dc, CC_MASK_NZ);
1219 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1220 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1224 static unsigned int dec_scc_r(DisasContext *dc)
1228 DIS(fprintf (logfile, "s%s $r%u\n",
1229 cc_name(cond), dc->op1));
1233 gen_tst_cc (dc, cond);
1234 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1237 tcg_gen_movi_tl(cpu_T[1], 1);
1239 cris_cc_mask(dc, 0);
1240 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1244 static unsigned int dec_and_r(DisasContext *dc)
1246 int size = memsize_zz(dc);
1248 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1249 memsize_char(size), dc->op1, dc->op2));
1250 cris_cc_mask(dc, CC_MASK_NZ);
1251 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1252 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1256 static unsigned int dec_lz_r(DisasContext *dc)
1258 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1260 cris_cc_mask(dc, CC_MASK_NZ);
1261 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1262 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1266 static unsigned int dec_lsl_r(DisasContext *dc)
1268 int size = memsize_zz(dc);
1270 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1271 memsize_char(size), dc->op1, dc->op2));
1272 cris_cc_mask(dc, CC_MASK_NZ);
1273 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1274 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1275 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1279 static unsigned int dec_lsr_r(DisasContext *dc)
1281 int size = memsize_zz(dc);
1283 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1284 memsize_char(size), dc->op1, dc->op2));
1285 cris_cc_mask(dc, CC_MASK_NZ);
1286 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1287 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1288 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1292 static unsigned int dec_asr_r(DisasContext *dc)
1294 int size = memsize_zz(dc);
1296 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1297 memsize_char(size), dc->op1, dc->op2));
1298 cris_cc_mask(dc, CC_MASK_NZ);
1299 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1300 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1301 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1305 static unsigned int dec_muls_r(DisasContext *dc)
1307 int size = memsize_zz(dc);
1309 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1310 memsize_char(size), dc->op1, dc->op2));
1311 cris_cc_mask(dc, CC_MASK_NZV);
1312 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1313 t_gen_sext(cpu_T[0], cpu_T[0], size);
1314 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1318 static unsigned int dec_mulu_r(DisasContext *dc)
1320 int size = memsize_zz(dc);
1322 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1323 memsize_char(size), dc->op1, dc->op2));
1324 cris_cc_mask(dc, CC_MASK_NZV);
1325 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1326 t_gen_zext(cpu_T[0], cpu_T[0], size);
1327 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1332 static unsigned int dec_dstep_r(DisasContext *dc)
1334 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1335 cris_cc_mask(dc, CC_MASK_NZ);
1336 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1337 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1338 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1342 static unsigned int dec_xor_r(DisasContext *dc)
1344 int size = memsize_zz(dc);
1345 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1346 memsize_char(size), dc->op1, dc->op2));
1347 BUG_ON(size != 4); /* xor is dword. */
1348 cris_cc_mask(dc, CC_MASK_NZ);
1349 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1350 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1354 static unsigned int dec_bound_r(DisasContext *dc)
1356 int size = memsize_zz(dc);
1357 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1358 memsize_char(size), dc->op1, dc->op2));
1359 cris_cc_mask(dc, CC_MASK_NZ);
1360 /* TODO: needs optmimization. */
1361 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1362 /* rd should be 4. */
1363 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1364 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1368 static unsigned int dec_cmp_r(DisasContext *dc)
1370 int size = memsize_zz(dc);
1371 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1372 memsize_char(size), dc->op1, dc->op2));
1373 cris_cc_mask(dc, CC_MASK_NZVC);
1374 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1375 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1379 static unsigned int dec_abs_r(DisasContext *dc)
1383 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1385 cris_cc_mask(dc, CC_MASK_NZ);
1386 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1388 /* TODO: consider a branch free approach. */
1389 l1 = gen_new_label();
1390 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1391 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1393 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1397 static unsigned int dec_add_r(DisasContext *dc)
1399 int size = memsize_zz(dc);
1400 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1401 memsize_char(size), dc->op1, dc->op2));
1402 cris_cc_mask(dc, CC_MASK_NZVC);
1403 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1404 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1408 static unsigned int dec_addc_r(DisasContext *dc)
1410 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1412 cris_evaluate_flags(dc);
1413 cris_cc_mask(dc, CC_MASK_NZVC);
1414 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1415 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1419 static unsigned int dec_mcp_r(DisasContext *dc)
1421 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1423 cris_evaluate_flags(dc);
1424 cris_cc_mask(dc, CC_MASK_RNZV);
1425 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1426 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1427 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1432 static char * swapmode_name(int mode, char *modename) {
1435 modename[i++] = 'n';
1437 modename[i++] = 'w';
1439 modename[i++] = 'b';
1441 modename[i++] = 'r';
1447 static unsigned int dec_swap_r(DisasContext *dc)
1449 DIS(char modename[4]);
1450 DIS(fprintf (logfile, "swap%s $r%u\n",
1451 swapmode_name(dc->op2, modename), dc->op1));
1453 cris_cc_mask(dc, CC_MASK_NZ);
1454 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1456 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1458 t_gen_swapw(cpu_T[0], cpu_T[0]);
1460 t_gen_swapb(cpu_T[0], cpu_T[0]);
1462 t_gen_swapr(cpu_T[0], cpu_T[0]);
1463 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1464 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1468 static unsigned int dec_or_r(DisasContext *dc)
1470 int size = memsize_zz(dc);
1471 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1472 memsize_char(size), dc->op1, dc->op2));
1473 cris_cc_mask(dc, CC_MASK_NZ);
1474 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1475 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1479 static unsigned int dec_addi_r(DisasContext *dc)
1481 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1482 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1483 cris_cc_mask(dc, 0);
1484 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1485 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1486 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1487 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1491 static unsigned int dec_addi_acr(DisasContext *dc)
1493 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1494 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1495 cris_cc_mask(dc, 0);
1496 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1497 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1499 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1500 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1504 static unsigned int dec_neg_r(DisasContext *dc)
1506 int size = memsize_zz(dc);
1507 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1508 memsize_char(size), dc->op1, dc->op2));
1509 cris_cc_mask(dc, CC_MASK_NZVC);
1510 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1511 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1515 static unsigned int dec_btst_r(DisasContext *dc)
1517 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1519 cris_cc_mask(dc, CC_MASK_NZ);
1520 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1521 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1523 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1524 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1529 static unsigned int dec_sub_r(DisasContext *dc)
1531 int size = memsize_zz(dc);
1532 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1533 memsize_char(size), dc->op1, dc->op2));
1534 cris_cc_mask(dc, CC_MASK_NZVC);
1535 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1536 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1540 /* Zero extension. From size to dword. */
1541 static unsigned int dec_movu_r(DisasContext *dc)
1543 int size = memsize_z(dc);
1544 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1550 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1554 /* Sign extension. From size to dword. */
1555 static unsigned int dec_movs_r(DisasContext *dc)
1557 int size = memsize_z(dc);
1558 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1562 cris_cc_mask(dc, CC_MASK_NZ);
1563 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1564 /* Size can only be qi or hi. */
1565 t_gen_sext(cpu_T[1], cpu_T[0], size);
1566 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1570 /* zero extension. From size to dword. */
1571 static unsigned int dec_addu_r(DisasContext *dc)
1573 int size = memsize_z(dc);
1574 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1578 cris_cc_mask(dc, CC_MASK_NZVC);
1579 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1580 /* Size can only be qi or hi. */
1581 t_gen_zext(cpu_T[1], cpu_T[1], size);
1582 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1583 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1587 /* Sign extension. From size to dword. */
1588 static unsigned int dec_adds_r(DisasContext *dc)
1590 int size = memsize_z(dc);
1591 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1595 cris_cc_mask(dc, CC_MASK_NZVC);
1596 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1597 /* Size can only be qi or hi. */
1598 t_gen_sext(cpu_T[1], cpu_T[1], size);
1599 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1601 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1605 /* Zero extension. From size to dword. */
1606 static unsigned int dec_subu_r(DisasContext *dc)
1608 int size = memsize_z(dc);
1609 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1613 cris_cc_mask(dc, CC_MASK_NZVC);
1614 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1615 /* Size can only be qi or hi. */
1616 t_gen_zext(cpu_T[1], cpu_T[1], size);
1617 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1618 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1622 /* Sign extension. From size to dword. */
1623 static unsigned int dec_subs_r(DisasContext *dc)
1625 int size = memsize_z(dc);
1626 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1630 cris_cc_mask(dc, CC_MASK_NZVC);
1631 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1632 /* Size can only be qi or hi. */
1633 t_gen_sext(cpu_T[1], cpu_T[1], size);
1634 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1635 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1639 static unsigned int dec_setclrf(DisasContext *dc)
1642 int set = (~dc->opcode >> 2) & 1;
1644 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1645 | EXTRACT_FIELD(dc->ir, 0, 3);
1646 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1647 if (set && flags == 0)
1648 DIS(fprintf (logfile, "nop\n"));
1649 else if (!set && (flags & 0x20))
1650 DIS(fprintf (logfile, "di\n"));
1652 DIS(fprintf (logfile, "%sf %x\n",
1653 set ? "set" : "clr",
1656 if (set && (flags & X_FLAG)) {
1661 /* Simply decode the flags. */
1662 cris_evaluate_flags (dc);
1663 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1664 tcg_gen_movi_tl(cc_op, dc->cc_op);
1675 static unsigned int dec_move_rs(DisasContext *dc)
1677 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1678 cris_cc_mask(dc, 0);
1679 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1680 gen_op_movl_sreg_T0(dc->op2);
1682 #if !defined(CONFIG_USER_ONLY)
1684 gen_op_movl_tlb_hi_T0();
1685 else if (dc->op2 == 5) { /* srs is checked at runtime. */
1686 tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
1687 gen_op_movl_tlb_lo_T0();
1692 static unsigned int dec_move_sr(DisasContext *dc)
1694 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1695 cris_cc_mask(dc, 0);
1696 gen_op_movl_T0_sreg(dc->op2);
1697 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1698 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1701 static unsigned int dec_move_rp(DisasContext *dc)
1703 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1704 cris_cc_mask(dc, 0);
1706 if (dc->op2 == PR_CCS) {
1707 cris_evaluate_flags(dc);
1708 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1710 /* User space is not allowed to touch all flags. */
1711 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1712 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1713 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1717 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1719 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1720 if (dc->op2 == PR_CCS) {
1721 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1726 static unsigned int dec_move_pr(DisasContext *dc)
1728 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1729 cris_cc_mask(dc, 0);
1730 /* Support register 0 is hardwired to zero.
1731 Treat it specially. */
1733 tcg_gen_movi_tl(cpu_T[1], 0);
1734 else if (dc->op2 == PR_CCS) {
1735 cris_evaluate_flags(dc);
1736 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1738 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1739 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1743 static unsigned int dec_move_mr(DisasContext *dc)
1745 int memsize = memsize_zz(dc);
1747 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1748 memsize_char(memsize),
1749 dc->op1, dc->postinc ? "+]" : "]",
1752 insn_len = dec_prep_alu_m(dc, 0, memsize);
1753 cris_cc_mask(dc, CC_MASK_NZ);
1754 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1755 do_postinc(dc, memsize);
1759 static unsigned int dec_movs_m(DisasContext *dc)
1761 int memsize = memsize_z(dc);
1763 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1764 memsize_char(memsize),
1765 dc->op1, dc->postinc ? "+]" : "]",
1769 insn_len = dec_prep_alu_m(dc, 1, memsize);
1770 cris_cc_mask(dc, CC_MASK_NZ);
1771 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1772 do_postinc(dc, memsize);
1776 static unsigned int dec_addu_m(DisasContext *dc)
1778 int memsize = memsize_z(dc);
1780 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
1781 memsize_char(memsize),
1782 dc->op1, dc->postinc ? "+]" : "]",
1786 insn_len = dec_prep_alu_m(dc, 0, memsize);
1787 cris_cc_mask(dc, CC_MASK_NZVC);
1788 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1789 do_postinc(dc, memsize);
1793 static unsigned int dec_adds_m(DisasContext *dc)
1795 int memsize = memsize_z(dc);
1797 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
1798 memsize_char(memsize),
1799 dc->op1, dc->postinc ? "+]" : "]",
1803 insn_len = dec_prep_alu_m(dc, 1, memsize);
1804 cris_cc_mask(dc, CC_MASK_NZVC);
1805 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1806 do_postinc(dc, memsize);
1810 static unsigned int dec_subu_m(DisasContext *dc)
1812 int memsize = memsize_z(dc);
1814 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
1815 memsize_char(memsize),
1816 dc->op1, dc->postinc ? "+]" : "]",
1820 insn_len = dec_prep_alu_m(dc, 0, memsize);
1821 cris_cc_mask(dc, CC_MASK_NZVC);
1822 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1823 do_postinc(dc, memsize);
1827 static unsigned int dec_subs_m(DisasContext *dc)
1829 int memsize = memsize_z(dc);
1831 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
1832 memsize_char(memsize),
1833 dc->op1, dc->postinc ? "+]" : "]",
1837 insn_len = dec_prep_alu_m(dc, 1, memsize);
1838 cris_cc_mask(dc, CC_MASK_NZVC);
1839 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1840 do_postinc(dc, memsize);
1844 static unsigned int dec_movu_m(DisasContext *dc)
1846 int memsize = memsize_z(dc);
1849 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
1850 memsize_char(memsize),
1851 dc->op1, dc->postinc ? "+]" : "]",
1854 insn_len = dec_prep_alu_m(dc, 0, memsize);
1855 cris_cc_mask(dc, CC_MASK_NZ);
1856 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1857 do_postinc(dc, memsize);
1861 static unsigned int dec_cmpu_m(DisasContext *dc)
1863 int memsize = memsize_z(dc);
1865 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
1866 memsize_char(memsize),
1867 dc->op1, dc->postinc ? "+]" : "]",
1870 insn_len = dec_prep_alu_m(dc, 0, memsize);
1871 cris_cc_mask(dc, CC_MASK_NZVC);
1872 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1873 do_postinc(dc, memsize);
1877 static unsigned int dec_cmps_m(DisasContext *dc)
1879 int memsize = memsize_z(dc);
1881 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
1882 memsize_char(memsize),
1883 dc->op1, dc->postinc ? "+]" : "]",
1886 insn_len = dec_prep_alu_m(dc, 1, memsize);
1887 cris_cc_mask(dc, CC_MASK_NZVC);
1888 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1889 do_postinc(dc, memsize);
1893 static unsigned int dec_cmp_m(DisasContext *dc)
1895 int memsize = memsize_zz(dc);
1897 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
1898 memsize_char(memsize),
1899 dc->op1, dc->postinc ? "+]" : "]",
1902 insn_len = dec_prep_alu_m(dc, 0, memsize);
1903 cris_cc_mask(dc, CC_MASK_NZVC);
1904 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1905 do_postinc(dc, memsize);
1909 static unsigned int dec_test_m(DisasContext *dc)
1911 int memsize = memsize_zz(dc);
1913 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
1914 memsize_char(memsize),
1915 dc->op1, dc->postinc ? "+]" : "]",
1918 insn_len = dec_prep_alu_m(dc, 0, memsize);
1919 cris_cc_mask(dc, CC_MASK_NZ);
1922 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1923 tcg_gen_movi_tl(cpu_T[1], 0);
1924 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1925 do_postinc(dc, memsize);
1929 static unsigned int dec_and_m(DisasContext *dc)
1931 int memsize = memsize_zz(dc);
1933 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
1934 memsize_char(memsize),
1935 dc->op1, dc->postinc ? "+]" : "]",
1938 insn_len = dec_prep_alu_m(dc, 0, memsize);
1939 cris_cc_mask(dc, CC_MASK_NZ);
1940 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
1941 do_postinc(dc, memsize);
1945 static unsigned int dec_add_m(DisasContext *dc)
1947 int memsize = memsize_zz(dc);
1949 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1950 memsize_char(memsize),
1951 dc->op1, dc->postinc ? "+]" : "]",
1954 insn_len = dec_prep_alu_m(dc, 0, memsize);
1955 cris_cc_mask(dc, CC_MASK_NZVC);
1956 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
1957 do_postinc(dc, memsize);
1961 static unsigned int dec_addo_m(DisasContext *dc)
1963 int memsize = memsize_zz(dc);
1965 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1966 memsize_char(memsize),
1967 dc->op1, dc->postinc ? "+]" : "]",
1970 insn_len = dec_prep_alu_m(dc, 1, memsize);
1971 cris_cc_mask(dc, 0);
1972 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
1973 do_postinc(dc, memsize);
1977 static unsigned int dec_bound_m(DisasContext *dc)
1979 int memsize = memsize_zz(dc);
1981 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
1982 memsize_char(memsize),
1983 dc->op1, dc->postinc ? "+]" : "]",
1986 insn_len = dec_prep_alu_m(dc, 0, memsize);
1987 cris_cc_mask(dc, CC_MASK_NZ);
1988 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1989 do_postinc(dc, memsize);
1993 static unsigned int dec_addc_mr(DisasContext *dc)
1996 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
1997 dc->op1, dc->postinc ? "+]" : "]",
2000 cris_evaluate_flags(dc);
2001 insn_len = dec_prep_alu_m(dc, 0, 4);
2002 cris_cc_mask(dc, CC_MASK_NZVC);
2003 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2008 static unsigned int dec_sub_m(DisasContext *dc)
2010 int memsize = memsize_zz(dc);
2012 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2013 memsize_char(memsize),
2014 dc->op1, dc->postinc ? "+]" : "]",
2015 dc->op2, dc->ir, dc->zzsize));
2017 insn_len = dec_prep_alu_m(dc, 0, memsize);
2018 cris_cc_mask(dc, CC_MASK_NZVC);
2019 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2020 do_postinc(dc, memsize);
2024 static unsigned int dec_or_m(DisasContext *dc)
2026 int memsize = memsize_zz(dc);
2028 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2029 memsize_char(memsize),
2030 dc->op1, dc->postinc ? "+]" : "]",
2033 insn_len = dec_prep_alu_m(dc, 0, memsize);
2034 cris_cc_mask(dc, CC_MASK_NZ);
2035 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2036 do_postinc(dc, memsize);
2040 static unsigned int dec_move_mp(DisasContext *dc)
2042 int memsize = memsize_zz(dc);
2045 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2046 memsize_char(memsize),
2048 dc->postinc ? "+]" : "]",
2051 insn_len = dec_prep_alu_m(dc, 0, memsize);
2052 cris_cc_mask(dc, 0);
2053 if (dc->op2 == PR_CCS) {
2054 cris_evaluate_flags(dc);
2056 /* User space is not allowed to touch all flags. */
2057 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2058 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2059 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2063 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2065 do_postinc(dc, memsize);
2069 static unsigned int dec_move_pm(DisasContext *dc)
2073 memsize = preg_sizes[dc->op2];
2075 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2076 memsize_char(memsize),
2077 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2079 /* prepare store. Address in T0, value in T1. */
2080 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2081 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2082 gen_store_T0_T1(dc, memsize);
2083 cris_cc_mask(dc, 0);
2086 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2087 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2092 static unsigned int dec_movem_mr(DisasContext *dc)
2096 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2097 dc->postinc ? "+]" : "]", dc->op2));
2099 /* fetch the address into T0 and T1. */
2100 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
2101 for (i = 0; i <= dc->op2; i++) {
2102 /* Perform the load onto regnum i. Always dword wide. */
2103 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2104 gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
2105 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
2107 /* writeback the updated pointer value. */
2109 t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
2111 /* gen_load might want to evaluate the previous insns flags. */
2112 cris_cc_mask(dc, 0);
2116 static unsigned int dec_movem_rm(DisasContext *dc)
2120 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2121 dc->postinc ? "+]" : "]"));
2123 for (i = 0; i <= dc->op2; i++) {
2124 /* Fetch register i into T1. */
2125 t_gen_mov_TN_reg(cpu_T[1], i);
2126 /* Fetch the address into T0. */
2127 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2129 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
2130 /* Perform the store. */
2131 gen_store_T0_T1(dc, 4);
2134 /* T0 should point to the last written addr, advance one more
2136 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
2137 /* writeback the updated pointer value. */
2138 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2140 cris_cc_mask(dc, 0);
2144 static unsigned int dec_move_rm(DisasContext *dc)
2148 memsize = memsize_zz(dc);
2150 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2151 memsize, dc->op2, dc->op1));
2153 /* prepare store. */
2154 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2155 t_gen_mov_TN_reg(cpu_T[1], dc->op2);
2156 gen_store_T0_T1(dc, memsize);
2159 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2160 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2162 cris_cc_mask(dc, 0);
2166 static unsigned int dec_lapcq(DisasContext *dc)
2168 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2169 dc->pc + dc->op1*2, dc->op2));
2170 cris_cc_mask(dc, 0);
2171 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2172 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2176 static unsigned int dec_lapc_im(DisasContext *dc)
2184 cris_cc_mask(dc, 0);
2185 imm = ldl_code(dc->pc + 2);
2186 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2190 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2194 /* Jump to special reg. */
2195 static unsigned int dec_jump_p(DisasContext *dc)
2197 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2198 cris_cc_mask(dc, 0);
2200 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2201 /* rete will often have low bit set to indicate delayslot. */
2202 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2203 cris_prepare_dyn_jmp(dc);
2207 /* Jump and save. */
2208 static unsigned int dec_jas_r(DisasContext *dc)
2210 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2211 cris_cc_mask(dc, 0);
2212 /* Store the return address in Pd. */
2213 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2216 tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
2218 cris_prepare_dyn_jmp(dc);
2222 static unsigned int dec_jas_im(DisasContext *dc)
2226 imm = ldl_code(dc->pc + 2);
2228 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2229 cris_cc_mask(dc, 0);
2230 /* Stor the return address in Pd. */
2231 tcg_gen_movi_tl(env_btarget, imm);
2232 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2233 cris_prepare_dyn_jmp(dc);
2237 static unsigned int dec_jasc_im(DisasContext *dc)
2241 imm = ldl_code(dc->pc + 2);
2243 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2244 cris_cc_mask(dc, 0);
2245 /* Stor the return address in Pd. */
2246 tcg_gen_movi_tl(cpu_T[0], imm);
2247 t_gen_mov_env_TN(btarget, cpu_T[0]);
2248 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2249 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2250 cris_prepare_dyn_jmp(dc);
2254 static unsigned int dec_jasc_r(DisasContext *dc)
2256 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2257 cris_cc_mask(dc, 0);
2258 /* Stor the return address in Pd. */
2259 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2260 t_gen_mov_env_TN(btarget, cpu_T[0]);
2261 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2262 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2263 cris_prepare_dyn_jmp(dc);
2267 static unsigned int dec_bcc_im(DisasContext *dc)
2270 uint32_t cond = dc->op2;
2272 offset = ldl_code(dc->pc + 2);
2273 offset = sign_extend(offset, 15);
2275 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2276 cc_name(cond), offset,
2277 dc->pc, dc->pc + offset));
2279 cris_cc_mask(dc, 0);
2280 /* op2 holds the condition-code. */
2281 cris_prepare_cc_branch (dc, offset, cond);
2285 static unsigned int dec_bas_im(DisasContext *dc)
2290 simm = ldl_code(dc->pc + 2);
2292 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2293 cris_cc_mask(dc, 0);
2294 /* Stor the return address in Pd. */
2295 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2296 t_gen_mov_env_TN(btarget, cpu_T[0]);
2297 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2298 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2299 cris_prepare_dyn_jmp(dc);
2303 static unsigned int dec_basc_im(DisasContext *dc)
2306 simm = ldl_code(dc->pc + 2);
2308 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2309 cris_cc_mask(dc, 0);
2310 /* Stor the return address in Pd. */
2311 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2312 t_gen_mov_env_TN(btarget, cpu_T[0]);
2313 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2314 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2315 cris_prepare_dyn_jmp(dc);
2319 static unsigned int dec_rfe_etc(DisasContext *dc)
2321 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2322 dc->opcode, dc->pc, dc->op1, dc->op2));
2324 cris_cc_mask(dc, 0);
2326 if (dc->op2 == 15) /* ignore halt. */
2329 switch (dc->op2 & 7) {
2332 cris_evaluate_flags(dc);
2333 gen_op_ccs_rshift();
2334 /* FIXME: don't set the P-FLAG if R is set. */
2335 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
2337 tcg_gen_helper_0_0(helper_rfe);
2338 dc->is_jmp = DISAS_UPDATE;
2346 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2347 t_gen_mov_env_TN(pc, cpu_T[0]);
2348 /* Breaks start at 16 in the exception vector. */
2349 gen_op_break_im(dc->op1 + 16);
2350 dc->is_jmp = DISAS_UPDATE;
2353 printf ("op2=%x\n", dc->op2);
2361 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2363 /* Ignore D-cache flushes. */
2367 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2369 /* Ignore I-cache flushes. */
2373 static unsigned int dec_null(DisasContext *dc)
2375 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2376 dc->pc, dc->opcode, dc->op1, dc->op2);
2382 struct decoder_info {
2387 unsigned int (*dec)(DisasContext *dc);
2389 /* Order matters here. */
2390 {DEC_MOVEQ, dec_moveq},
2391 {DEC_BTSTQ, dec_btstq},
2392 {DEC_CMPQ, dec_cmpq},
2393 {DEC_ADDOQ, dec_addoq},
2394 {DEC_ADDQ, dec_addq},
2395 {DEC_SUBQ, dec_subq},
2396 {DEC_ANDQ, dec_andq},
2398 {DEC_ASRQ, dec_asrq},
2399 {DEC_LSLQ, dec_lslq},
2400 {DEC_LSRQ, dec_lsrq},
2401 {DEC_BCCQ, dec_bccq},
2403 {DEC_BCC_IM, dec_bcc_im},
2404 {DEC_JAS_IM, dec_jas_im},
2405 {DEC_JAS_R, dec_jas_r},
2406 {DEC_JASC_IM, dec_jasc_im},
2407 {DEC_JASC_R, dec_jasc_r},
2408 {DEC_BAS_IM, dec_bas_im},
2409 {DEC_BASC_IM, dec_basc_im},
2410 {DEC_JUMP_P, dec_jump_p},
2411 {DEC_LAPC_IM, dec_lapc_im},
2412 {DEC_LAPCQ, dec_lapcq},
2414 {DEC_RFE_ETC, dec_rfe_etc},
2415 {DEC_ADDC_MR, dec_addc_mr},
2417 {DEC_MOVE_MP, dec_move_mp},
2418 {DEC_MOVE_PM, dec_move_pm},
2419 {DEC_MOVEM_MR, dec_movem_mr},
2420 {DEC_MOVEM_RM, dec_movem_rm},
2421 {DEC_MOVE_PR, dec_move_pr},
2422 {DEC_SCC_R, dec_scc_r},
2423 {DEC_SETF, dec_setclrf},
2424 {DEC_CLEARF, dec_setclrf},
2426 {DEC_MOVE_SR, dec_move_sr},
2427 {DEC_MOVE_RP, dec_move_rp},
2428 {DEC_SWAP_R, dec_swap_r},
2429 {DEC_ABS_R, dec_abs_r},
2430 {DEC_LZ_R, dec_lz_r},
2431 {DEC_MOVE_RS, dec_move_rs},
2432 {DEC_BTST_R, dec_btst_r},
2433 {DEC_ADDC_R, dec_addc_r},
2435 {DEC_DSTEP_R, dec_dstep_r},
2436 {DEC_XOR_R, dec_xor_r},
2437 {DEC_MCP_R, dec_mcp_r},
2438 {DEC_CMP_R, dec_cmp_r},
2440 {DEC_ADDI_R, dec_addi_r},
2441 {DEC_ADDI_ACR, dec_addi_acr},
2443 {DEC_ADD_R, dec_add_r},
2444 {DEC_SUB_R, dec_sub_r},
2446 {DEC_ADDU_R, dec_addu_r},
2447 {DEC_ADDS_R, dec_adds_r},
2448 {DEC_SUBU_R, dec_subu_r},
2449 {DEC_SUBS_R, dec_subs_r},
2450 {DEC_LSL_R, dec_lsl_r},
2452 {DEC_AND_R, dec_and_r},
2453 {DEC_OR_R, dec_or_r},
2454 {DEC_BOUND_R, dec_bound_r},
2455 {DEC_ASR_R, dec_asr_r},
2456 {DEC_LSR_R, dec_lsr_r},
2458 {DEC_MOVU_R, dec_movu_r},
2459 {DEC_MOVS_R, dec_movs_r},
2460 {DEC_NEG_R, dec_neg_r},
2461 {DEC_MOVE_R, dec_move_r},
2463 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2464 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2466 {DEC_MULS_R, dec_muls_r},
2467 {DEC_MULU_R, dec_mulu_r},
2469 {DEC_ADDU_M, dec_addu_m},
2470 {DEC_ADDS_M, dec_adds_m},
2471 {DEC_SUBU_M, dec_subu_m},
2472 {DEC_SUBS_M, dec_subs_m},
2474 {DEC_CMPU_M, dec_cmpu_m},
2475 {DEC_CMPS_M, dec_cmps_m},
2476 {DEC_MOVU_M, dec_movu_m},
2477 {DEC_MOVS_M, dec_movs_m},
2479 {DEC_CMP_M, dec_cmp_m},
2480 {DEC_ADDO_M, dec_addo_m},
2481 {DEC_BOUND_M, dec_bound_m},
2482 {DEC_ADD_M, dec_add_m},
2483 {DEC_SUB_M, dec_sub_m},
2484 {DEC_AND_M, dec_and_m},
2485 {DEC_OR_M, dec_or_m},
2486 {DEC_MOVE_RM, dec_move_rm},
2487 {DEC_TEST_M, dec_test_m},
2488 {DEC_MOVE_MR, dec_move_mr},
2493 static inline unsigned int
2494 cris_decoder(DisasContext *dc)
2496 unsigned int insn_len = 2;
2500 /* Load a halfword onto the instruction register. */
2501 tmp = ldl_code(dc->pc);
2502 dc->ir = tmp & 0xffff;
2504 /* Now decode it. */
2505 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2506 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2507 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2508 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2509 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2510 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2512 /* Large switch for all insns. */
2513 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2514 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2516 insn_len = decinfo[i].dec(dc);
2524 static void check_breakpoint(CPUState *env, DisasContext *dc)
2527 if (env->nb_breakpoints > 0) {
2528 for(j = 0; j < env->nb_breakpoints; j++) {
2529 if (env->breakpoints[j] == dc->pc) {
2530 cris_evaluate_flags (dc);
2531 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2532 t_gen_mov_env_TN(pc, cpu_T[0]);
2534 dc->is_jmp = DISAS_UPDATE;
2540 /* generate intermediate code for basic block 'tb'. */
2541 struct DisasContext ctx;
2543 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2546 uint16_t *gen_opc_end;
2548 unsigned int insn_len;
2550 struct DisasContext *dc = &ctx;
2551 uint32_t next_page_start;
2557 cpu_abort(env, "unaligned pc=%x erp=%x\n",
2558 env->pc, env->pregs[PR_ERP]);
2563 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2565 dc->is_jmp = DISAS_NEXT;
2568 dc->singlestep_enabled = env->singlestep_enabled;
2573 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2575 dc->user = env->pregs[PR_CCS] & U_FLAG;
2576 dc->delayed_branch = 0;
2578 if (loglevel & CPU_LOG_TB_IN_ASM) {
2580 "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
2585 search_pc, env->pc, env->pregs[PR_CCS],
2586 env->pregs[PR_PID], env->pregs[PR_USP],
2587 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2588 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2589 env->regs[8], env->regs[9],
2590 env->regs[10], env->regs[11],
2591 env->regs[12], env->regs[13],
2592 env->regs[14], env->regs[15]);
2596 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2600 check_breakpoint(env, dc);
2601 if (dc->is_jmp == DISAS_JUMP
2602 || dc->is_jmp == DISAS_SWI)
2606 j = gen_opc_ptr - gen_opc_buf;
2610 gen_opc_instr_start[lj++] = 0;
2612 if (dc->delayed_branch == 1) {
2613 gen_opc_pc[lj] = dc->ppc | 1;
2614 gen_opc_instr_start[lj] = 0;
2617 gen_opc_pc[lj] = dc->pc;
2618 gen_opc_instr_start[lj] = 1;
2623 insn_len = cris_decoder(dc);
2624 STATS(gen_op_exec_insn());
2628 cris_clear_x_flag(dc);
2630 /* Check for delayed branches here. If we do it before
2631 actually genereating any host code, the simulator will just
2632 loop doing nothing for on this program location. */
2633 if (dc->delayed_branch) {
2634 dc->delayed_branch--;
2635 if (dc->delayed_branch == 0)
2637 if (dc->bcc == CC_A) {
2639 dc->is_jmp = DISAS_JUMP;
2642 /* Conditional jmp. */
2643 gen_op_cc_jmp (dc->delayed_pc, dc->pc);
2644 dc->is_jmp = DISAS_JUMP;
2649 if (env->singlestep_enabled)
2651 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2652 && ((dc->pc < next_page_start) || dc->delayed_branch));
2654 if (dc->delayed_branch == 1) {
2655 /* Reexecute the last insn. */
2660 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2661 dc->is_jmp, dc->delayed_branch));
2662 /* T0 and env_pc should hold the new pc. */
2663 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2664 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2667 cris_evaluate_flags (dc);
2669 if (__builtin_expect(env->singlestep_enabled, 0)) {
2672 switch(dc->is_jmp) {
2674 gen_goto_tb(dc, 1, dc->pc);
2679 /* indicate that the hash table must be used
2680 to find the next TB */
2685 /* nothing more to generate */
2689 *gen_opc_ptr = INDEX_op_end;
2691 j = gen_opc_ptr - gen_opc_buf;
2694 gen_opc_instr_start[lj++] = 0;
2696 tb->size = dc->pc - pc_start;
2700 if (loglevel & CPU_LOG_TB_IN_ASM) {
2701 fprintf(logfile, "--------------\n");
2702 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2703 target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
2704 fprintf(logfile, "\nisize=%d osize=%d\n",
2705 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2711 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2713 return gen_intermediate_code_internal(env, tb, 0);
2716 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2718 return gen_intermediate_code_internal(env, tb, 1);
2721 void cpu_dump_state (CPUState *env, FILE *f,
2722 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2731 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2732 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2734 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2736 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2737 env->debug1, env->debug2, env->debug3);
2739 for (i = 0; i < 16; i++) {
2740 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2741 if ((i + 1) % 4 == 0)
2742 cpu_fprintf(f, "\n");
2744 cpu_fprintf(f, "\nspecial regs:\n");
2745 for (i = 0; i < 16; i++) {
2746 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2747 if ((i + 1) % 4 == 0)
2748 cpu_fprintf(f, "\n");
2750 srs = env->pregs[PR_SRS];
2751 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
2753 for (i = 0; i < 16; i++) {
2754 cpu_fprintf(f, "s%2.2d=%8.8x ",
2755 i, env->sregs[srs][i]);
2756 if ((i + 1) % 4 == 0)
2757 cpu_fprintf(f, "\n");
2760 cpu_fprintf(f, "\n\n");
2764 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
2768 CPUCRISState *cpu_cris_init (const char *cpu_model)
2773 env = qemu_mallocz(sizeof(CPUCRISState));
2778 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
2779 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
2780 #if TARGET_LONG_BITS > HOST_LONG_BITS
2781 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
2782 TCG_AREG0, offsetof(CPUState, t0), "T0");
2783 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
2784 TCG_AREG0, offsetof(CPUState, t1), "T1");
2786 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
2787 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
2790 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2791 offsetof(CPUState, cc_src), "cc_src");
2792 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2793 offsetof(CPUState, cc_dest),
2795 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2796 offsetof(CPUState, cc_result),
2798 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2799 offsetof(CPUState, cc_op), "cc_op");
2800 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2801 offsetof(CPUState, cc_size),
2803 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2804 offsetof(CPUState, cc_mask),
2807 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2808 offsetof(CPUState, pc),
2810 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2811 offsetof(CPUState, btarget),
2814 for (i = 0; i < 16; i++) {
2815 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2816 offsetof(CPUState, regs[i]),
2819 for (i = 0; i < 16; i++) {
2820 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2821 offsetof(CPUState, pregs[i]),
2825 TCG_HELPER(helper_tlb_update);
2826 TCG_HELPER(helper_tlb_flush);
2827 TCG_HELPER(helper_rfe);
2828 TCG_HELPER(helper_store);
2829 TCG_HELPER(helper_dump);
2830 TCG_HELPER(helper_dummy);
2832 TCG_HELPER(helper_evaluate_flags_muls);
2833 TCG_HELPER(helper_evaluate_flags_mulu);
2834 TCG_HELPER(helper_evaluate_flags_mcp);
2835 TCG_HELPER(helper_evaluate_flags_alu_4);
2836 TCG_HELPER(helper_evaluate_flags_move_4);
2837 TCG_HELPER(helper_evaluate_flags_move_2);
2838 TCG_HELPER(helper_evaluate_flags);
2844 void cpu_reset (CPUCRISState *env)
2846 memset(env, 0, offsetof(CPUCRISState, breakpoints));
2849 #if defined(CONFIG_USER_ONLY)
2850 /* start in user mode with interrupts enabled. */
2851 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
2853 env->pregs[PR_CCS] = 0;
2857 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
2858 unsigned long searched_pc, int pc_pos, void *puc)
2860 env->pc = gen_opc_pc[pc_pos];