2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
44 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
66 static TCGv cpu_R[16];
67 static TCGv cpu_PR[16];
71 static TCGv cc_result;
76 static TCGv env_btaken;
77 static TCGv env_btarget;
80 #include "gen-icount.h"
82 /* This is the state at translation time. */
83 typedef struct DisasContext {
92 unsigned int zsize, zzsize;
101 int cc_size_uptodate; /* -1 invalid or last written value. */
103 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
104 int flags_uptodate; /* Wether or not $ccs is uptodate. */
105 int flagx_known; /* Wether or not flags_x has the x flag known at
109 int clear_x; /* Clear x after this insn? */
110 int cpustate_changed;
111 unsigned int tb_flags; /* tb dependent flags. */
116 #define JMP_INDIRECT 2
117 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
122 struct TranslationBlock *tb;
123 int singlestep_enabled;
126 static void gen_BUG(DisasContext *dc, const char *file, int line)
128 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
129 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
130 cpu_abort(dc->env, "%s:%d\n", file, line);
133 static const char *regnames[] =
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
140 static const char *pregnames[] =
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
148 /* We need this table to handle preg-moves with implicit width. */
149 static int preg_sizes[] = {
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EDA) {
200 printf("read from EDA!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
209 fprintf(stderr, "wrong register write $p%d\n", r);
210 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
212 else if (r == PR_SRS)
213 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
216 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
217 if (dc->tb_flags & S_FLAG && r == PR_SPC)
218 tcg_gen_helper_0_1(helper_spc_write, tn);
219 else if (r == PR_CCS)
220 dc->cpustate_changed = 1;
221 tcg_gen_mov_tl(cpu_PR[r], tn);
225 static inline void t_gen_raise_exception(uint32_t index)
227 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
230 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
234 l1 = gen_new_label();
235 /* Speculative shift. */
236 tcg_gen_shl_tl(d, a, b);
237 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
238 /* Clear dst if shift operands were to large. */
239 tcg_gen_movi_tl(d, 0);
243 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
247 l1 = gen_new_label();
248 /* Speculative shift. */
249 tcg_gen_shr_tl(d, a, b);
250 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
251 /* Clear dst if shift operands were to large. */
252 tcg_gen_movi_tl(d, 0);
256 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
260 l1 = gen_new_label();
261 /* Speculative shift. */
262 tcg_gen_sar_tl(d, a, b);
263 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
264 /* Clear dst if shift operands were to large. */
265 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
269 /* 64-bit signed mul, lower result in d and upper in d2. */
270 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
274 t0 = tcg_temp_new(TCG_TYPE_I64);
275 t1 = tcg_temp_new(TCG_TYPE_I64);
277 tcg_gen_ext32s_i64(t0, a);
278 tcg_gen_ext32s_i64(t1, b);
279 tcg_gen_mul_i64(t0, t0, t1);
281 tcg_gen_trunc_i64_i32(d, t0);
282 tcg_gen_shri_i64(t0, t0, 32);
283 tcg_gen_trunc_i64_i32(d2, t0);
289 /* 64-bit unsigned muls, lower result in d and upper in d2. */
290 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
294 t0 = tcg_temp_new(TCG_TYPE_I64);
295 t1 = tcg_temp_new(TCG_TYPE_I64);
297 tcg_gen_extu_i32_i64(t0, a);
298 tcg_gen_extu_i32_i64(t1, b);
299 tcg_gen_mul_i64(t0, t0, t1);
301 tcg_gen_trunc_i64_i32(d, t0);
302 tcg_gen_shri_i64(t0, t0, 32);
303 tcg_gen_trunc_i64_i32(d2, t0);
309 /* 32bit branch-free binary search for counting leading zeros. */
310 static void t_gen_lz_i32(TCGv d, TCGv x)
314 y = tcg_temp_new(TCG_TYPE_I32);
315 m = tcg_temp_new(TCG_TYPE_I32);
316 n = tcg_temp_new(TCG_TYPE_I32);
319 tcg_gen_shri_i32(y, x, 16);
320 tcg_gen_neg_i32(y, y);
322 /* m = (y >> 16) & 16 */
323 tcg_gen_sari_i32(m, y, 16);
324 tcg_gen_andi_i32(m, m, 16);
327 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
329 tcg_gen_shr_i32(x, x, m);
332 tcg_gen_subi_i32(y, x, 0x100);
333 /* m = (y >> 16) & 8 */
334 tcg_gen_sari_i32(m, y, 16);
335 tcg_gen_andi_i32(m, m, 8);
337 tcg_gen_add_i32(n, n, m);
339 tcg_gen_shl_i32(x, x, m);
342 tcg_gen_subi_i32(y, x, 0x1000);
343 /* m = (y >> 16) & 4 */
344 tcg_gen_sari_i32(m, y, 16);
345 tcg_gen_andi_i32(m, m, 4);
347 tcg_gen_add_i32(n, n, m);
349 tcg_gen_shl_i32(x, x, m);
352 tcg_gen_subi_i32(y, x, 0x4000);
353 /* m = (y >> 16) & 2 */
354 tcg_gen_sari_i32(m, y, 16);
355 tcg_gen_andi_i32(m, m, 2);
357 tcg_gen_add_i32(n, n, m);
359 tcg_gen_shl_i32(x, x, m);
362 tcg_gen_shri_i32(y, x, 14);
363 /* m = y & ~(y >> 1) */
364 tcg_gen_sari_i32(m, y, 1);
365 tcg_gen_not_i32(m, m);
366 tcg_gen_and_i32(m, m, y);
369 tcg_gen_addi_i32(d, n, 2);
370 tcg_gen_sub_i32(d, d, m);
377 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
392 unsigned int fz, sbit, bset, mask, masked_t0;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
409 t0 = tcg_temp_new(TCG_TYPE_TL);
411 /* Compute bset and sbit. */
412 tcg_gen_andi_tl(sbit, b, 31);
413 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
414 tcg_gen_and_tl(bset, a, t0);
415 tcg_gen_shr_tl(bset, bset, sbit);
416 /* Displace to N_FLAG. */
417 tcg_gen_shli_tl(bset, bset, 3);
419 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
420 tcg_gen_subi_tl(sbit, sbit, 1);
421 tcg_gen_and_tl(sbit, a, sbit);
423 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
424 /* or in the N_FLAG. */
425 tcg_gen_or_tl(d, d, bset);
426 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
427 /* or in the Z_FLAG. */
428 tcg_gen_ori_tl(d, d, Z_FLAG);
435 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
439 l1 = gen_new_label();
446 tcg_gen_shli_tl(d, a, 1);
447 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
448 tcg_gen_sub_tl(d, d, b);
452 /* Extended arithmetics on CRIS. */
453 static inline void t_gen_add_flag(TCGv d, int flag)
457 c = tcg_temp_new(TCG_TYPE_TL);
458 t_gen_mov_TN_preg(c, PR_CCS);
459 /* Propagate carry into d. */
460 tcg_gen_andi_tl(c, c, 1 << flag);
462 tcg_gen_shri_tl(c, c, flag);
463 tcg_gen_add_tl(d, d, c);
467 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
469 if (dc->flagx_known) {
473 c = tcg_temp_new(TCG_TYPE_TL);
474 t_gen_mov_TN_preg(c, PR_CCS);
475 /* C flag is already at bit 0. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_add_tl(d, d, c);
483 x = tcg_temp_new(TCG_TYPE_TL);
484 c = tcg_temp_new(TCG_TYPE_TL);
485 t_gen_mov_TN_preg(x, PR_CCS);
486 tcg_gen_mov_tl(c, x);
488 /* Propagate carry into d if X is set. Branch free. */
489 tcg_gen_andi_tl(c, c, C_FLAG);
490 tcg_gen_andi_tl(x, x, X_FLAG);
491 tcg_gen_shri_tl(x, x, 4);
493 tcg_gen_and_tl(x, x, c);
494 tcg_gen_add_tl(d, d, x);
500 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
502 if (dc->flagx_known) {
506 c = tcg_temp_new(TCG_TYPE_TL);
507 t_gen_mov_TN_preg(c, PR_CCS);
508 /* C flag is already at bit 0. */
509 tcg_gen_andi_tl(c, c, C_FLAG);
510 tcg_gen_sub_tl(d, d, c);
516 x = tcg_temp_new(TCG_TYPE_TL);
517 c = tcg_temp_new(TCG_TYPE_TL);
518 t_gen_mov_TN_preg(x, PR_CCS);
519 tcg_gen_mov_tl(c, x);
521 /* Propagate carry into d if X is set. Branch free. */
522 tcg_gen_andi_tl(c, c, C_FLAG);
523 tcg_gen_andi_tl(x, x, X_FLAG);
524 tcg_gen_shri_tl(x, x, 4);
526 tcg_gen_and_tl(x, x, c);
527 tcg_gen_sub_tl(d, d, x);
533 /* Swap the two bytes within each half word of the s operand.
534 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
535 static inline void t_gen_swapb(TCGv d, TCGv s)
539 t = tcg_temp_new(TCG_TYPE_TL);
540 org_s = tcg_temp_new(TCG_TYPE_TL);
542 /* d and s may refer to the same object. */
543 tcg_gen_mov_tl(org_s, s);
544 tcg_gen_shli_tl(t, org_s, 8);
545 tcg_gen_andi_tl(d, t, 0xff00ff00);
546 tcg_gen_shri_tl(t, org_s, 8);
547 tcg_gen_andi_tl(t, t, 0x00ff00ff);
548 tcg_gen_or_tl(d, d, t);
550 tcg_temp_free(org_s);
553 /* Swap the halfwords of the s operand. */
554 static inline void t_gen_swapw(TCGv d, TCGv s)
557 /* d and s refer the same object. */
558 t = tcg_temp_new(TCG_TYPE_TL);
559 tcg_gen_mov_tl(t, s);
560 tcg_gen_shli_tl(d, t, 16);
561 tcg_gen_shri_tl(t, t, 16);
562 tcg_gen_or_tl(d, d, t);
566 /* Reverse the within each byte.
567 T0 = (((T0 << 7) & 0x80808080) |
568 ((T0 << 5) & 0x40404040) |
569 ((T0 << 3) & 0x20202020) |
570 ((T0 << 1) & 0x10101010) |
571 ((T0 >> 1) & 0x08080808) |
572 ((T0 >> 3) & 0x04040404) |
573 ((T0 >> 5) & 0x02020202) |
574 ((T0 >> 7) & 0x01010101));
576 static inline void t_gen_swapr(TCGv d, TCGv s)
579 int shift; /* LSL when positive, LSR when negative. */
594 /* d and s refer the same object. */
595 t = tcg_temp_new(TCG_TYPE_TL);
596 org_s = tcg_temp_new(TCG_TYPE_TL);
597 tcg_gen_mov_tl(org_s, s);
599 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
600 tcg_gen_andi_tl(d, t, bitrev[0].mask);
601 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
602 if (bitrev[i].shift >= 0) {
603 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
605 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
607 tcg_gen_andi_tl(t, t, bitrev[i].mask);
608 tcg_gen_or_tl(d, d, t);
611 tcg_temp_free(org_s);
614 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
619 l1 = gen_new_label();
620 btaken = tcg_temp_new(TCG_TYPE_TL);
622 /* Conditional jmp. */
623 tcg_gen_mov_tl(btaken, env_btaken);
624 tcg_gen_mov_tl(env_pc, pc_false);
625 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
626 tcg_gen_mov_tl(env_pc, pc_true);
629 tcg_temp_free(btaken);
632 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
634 TranslationBlock *tb;
636 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
638 tcg_gen_movi_tl(env_pc, dest);
639 tcg_gen_exit_tb((long)tb + n);
641 tcg_gen_movi_tl(env_pc, dest);
646 /* Sign extend at translation time. */
647 static int sign_extend(unsigned int val, unsigned int width)
659 static inline void cris_clear_x_flag(DisasContext *dc)
661 if (dc->flagx_known && dc->flags_x)
662 dc->flags_uptodate = 0;
668 static void cris_flush_cc_state(DisasContext *dc)
670 if (dc->cc_size_uptodate != dc->cc_size) {
671 tcg_gen_movi_tl(cc_size, dc->cc_size);
672 dc->cc_size_uptodate = dc->cc_size;
674 tcg_gen_movi_tl(cc_op, dc->cc_op);
675 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
678 static void cris_evaluate_flags(DisasContext *dc)
680 if (!dc->flags_uptodate) {
681 cris_flush_cc_state(dc);
686 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
689 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
692 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
704 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
707 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
710 tcg_gen_helper_0_0(helper_evaluate_flags);
722 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
725 tcg_gen_helper_0_0(helper_evaluate_flags);
731 if (dc->flagx_known) {
733 tcg_gen_ori_tl(cpu_PR[PR_CCS],
734 cpu_PR[PR_CCS], X_FLAG);
736 tcg_gen_andi_tl(cpu_PR[PR_CCS],
737 cpu_PR[PR_CCS], ~X_FLAG);
740 dc->flags_uptodate = 1;
744 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
753 /* Check if we need to evaluate the condition codes due to
755 ovl = (dc->cc_mask ^ mask) & ~mask;
757 /* TODO: optimize this case. It trigs all the time. */
758 cris_evaluate_flags (dc);
764 static void cris_update_cc_op(DisasContext *dc, int op, int size)
768 dc->flags_uptodate = 0;
771 static inline void cris_update_cc_x(DisasContext *dc)
773 /* Save the x flag state at the time of the cc snapshot. */
774 if (dc->flagx_known) {
775 if (dc->cc_x_uptodate == (2 | dc->flags_x))
777 tcg_gen_movi_tl(cc_x, dc->flags_x);
778 dc->cc_x_uptodate = 2 | dc->flags_x;
781 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
782 dc->cc_x_uptodate = 1;
786 /* Update cc prior to executing ALU op. Needs source operands untouched. */
787 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
788 TCGv dst, TCGv src, int size)
791 cris_update_cc_op(dc, op, size);
792 tcg_gen_mov_tl(cc_src, src);
801 tcg_gen_mov_tl(cc_dest, dst);
803 cris_update_cc_x(dc);
807 /* Update cc after executing ALU op. needs the result. */
808 static inline void cris_update_result(DisasContext *dc, TCGv res)
811 if (dc->cc_size == 4 &&
812 (dc->cc_op == CC_OP_SUB
813 || dc->cc_op == CC_OP_ADD))
815 tcg_gen_mov_tl(cc_result, res);
819 /* Returns one if the write back stage should execute. */
820 static void cris_alu_op_exec(DisasContext *dc, int op,
821 TCGv dst, TCGv a, TCGv b, int size)
823 /* Emit the ALU insns. */
827 tcg_gen_add_tl(dst, a, b);
828 /* Extended arithmetics. */
829 t_gen_addx_carry(dc, dst);
832 tcg_gen_add_tl(dst, a, b);
833 t_gen_add_flag(dst, 0); /* C_FLAG. */
836 tcg_gen_add_tl(dst, a, b);
837 t_gen_add_flag(dst, 8); /* R_FLAG. */
840 tcg_gen_sub_tl(dst, a, b);
841 /* Extended arithmetics. */
842 t_gen_subx_carry(dc, dst);
845 tcg_gen_mov_tl(dst, b);
848 tcg_gen_or_tl(dst, a, b);
851 tcg_gen_and_tl(dst, a, b);
854 tcg_gen_xor_tl(dst, a, b);
857 t_gen_lsl(dst, a, b);
860 t_gen_lsr(dst, a, b);
863 t_gen_asr(dst, a, b);
866 tcg_gen_neg_tl(dst, b);
867 /* Extended arithmetics. */
868 t_gen_subx_carry(dc, dst);
871 t_gen_lz_i32(dst, b);
874 t_gen_btst(dst, a, b);
877 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
880 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
883 t_gen_cris_dstep(dst, a, b);
888 l1 = gen_new_label();
889 tcg_gen_mov_tl(dst, a);
890 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
891 tcg_gen_mov_tl(dst, b);
896 tcg_gen_sub_tl(dst, a, b);
897 /* Extended arithmetics. */
898 t_gen_subx_carry(dc, dst);
901 fprintf (logfile, "illegal ALU op.\n");
907 tcg_gen_andi_tl(dst, dst, 0xff);
909 tcg_gen_andi_tl(dst, dst, 0xffff);
912 static void cris_alu(DisasContext *dc, int op,
913 TCGv d, TCGv op_a, TCGv op_b, int size)
922 else if (size == 4) {
927 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
928 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
929 cris_update_result(dc, tmp);
934 tcg_gen_andi_tl(d, d, ~0xff);
936 tcg_gen_andi_tl(d, d, ~0xffff);
937 tcg_gen_or_tl(d, d, tmp);
941 static int arith_cc(DisasContext *dc)
945 case CC_OP_ADDC: return 1;
946 case CC_OP_ADD: return 1;
947 case CC_OP_SUB: return 1;
948 case CC_OP_DSTEP: return 1;
949 case CC_OP_LSL: return 1;
950 case CC_OP_LSR: return 1;
951 case CC_OP_ASR: return 1;
952 case CC_OP_CMP: return 1;
953 case CC_OP_NEG: return 1;
954 case CC_OP_OR: return 1;
955 case CC_OP_XOR: return 1;
956 case CC_OP_MULU: return 1;
957 case CC_OP_MULS: return 1;
965 static void gen_tst_cc (DisasContext *dc, int cond)
967 int arith_opt, move_opt;
969 /* TODO: optimize more condition codes. */
972 * If the flags are live, we've gotta look into the bits of CCS.
973 * Otherwise, if we just did an arithmetic operation we try to
974 * evaluate the condition code faster.
976 * When this function is done, T0 should be non-zero if the condition
979 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
980 move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
983 if (arith_opt || move_opt) {
984 /* If cc_result is zero, T0 should be
985 non-zero otherwise T0 should be zero. */
987 l1 = gen_new_label();
988 tcg_gen_movi_tl(cpu_T[0], 0);
989 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
991 tcg_gen_movi_tl(cpu_T[0], 1);
995 cris_evaluate_flags(dc);
996 tcg_gen_andi_tl(cpu_T[0],
997 cpu_PR[PR_CCS], Z_FLAG);
1001 if (arith_opt || move_opt)
1002 tcg_gen_mov_tl(cpu_T[0], cc_result);
1004 cris_evaluate_flags(dc);
1005 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1007 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1011 cris_evaluate_flags(dc);
1012 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1015 cris_evaluate_flags(dc);
1016 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1017 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
1020 cris_evaluate_flags(dc);
1021 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
1024 cris_evaluate_flags(dc);
1025 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1027 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
1030 if (arith_opt || move_opt) {
1033 if (dc->cc_size == 1)
1035 else if (dc->cc_size == 2)
1038 tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
1039 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1041 cris_evaluate_flags(dc);
1042 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1044 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1048 if (arith_opt || move_opt) {
1051 if (dc->cc_size == 1)
1053 else if (dc->cc_size == 2)
1056 tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
1059 cris_evaluate_flags(dc);
1060 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1065 cris_evaluate_flags(dc);
1066 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1070 cris_evaluate_flags(dc);
1074 tmp = tcg_temp_new(TCG_TYPE_TL);
1075 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1077 /* Overlay the C flag on top of the Z. */
1078 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
1079 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
1080 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1086 cris_evaluate_flags(dc);
1087 /* Overlay the V flag on top of the N. */
1088 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1089 tcg_gen_xor_tl(cpu_T[0],
1090 cpu_PR[PR_CCS], cpu_T[0]);
1091 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1092 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
1095 cris_evaluate_flags(dc);
1096 /* Overlay the V flag on top of the N. */
1097 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1098 tcg_gen_xor_tl(cpu_T[0],
1099 cpu_PR[PR_CCS], cpu_T[0]);
1100 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1103 cris_evaluate_flags(dc);
1107 n = tcg_temp_new(TCG_TYPE_TL);
1108 z = tcg_temp_new(TCG_TYPE_TL);
1110 /* To avoid a shift we overlay everything on
1112 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1113 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1115 tcg_gen_xori_tl(z, z, 2);
1117 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1118 tcg_gen_xori_tl(n, n, 2);
1119 tcg_gen_and_tl(cpu_T[0], z, n);
1120 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1127 cris_evaluate_flags(dc);
1131 n = tcg_temp_new(TCG_TYPE_TL);
1132 z = tcg_temp_new(TCG_TYPE_TL);
1134 /* To avoid a shift we overlay everything on
1136 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1137 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1139 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1140 tcg_gen_or_tl(cpu_T[0], z, n);
1141 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1148 cris_evaluate_flags(dc);
1149 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
1152 tcg_gen_movi_tl(cpu_T[0], 1);
1160 static void cris_store_direct_jmp(DisasContext *dc)
1162 /* Store the direct jmp state into the cpu-state. */
1163 if (dc->jmp == JMP_DIRECT) {
1164 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1165 tcg_gen_movi_tl(env_btaken, 1);
1169 static void cris_prepare_cc_branch (DisasContext *dc,
1170 int offset, int cond)
1172 /* This helps us re-schedule the micro-code to insns in delay-slots
1173 before the actual jump. */
1174 dc->delayed_branch = 2;
1175 dc->jmp_pc = dc->pc + offset;
1179 dc->jmp = JMP_INDIRECT;
1180 gen_tst_cc (dc, cond);
1181 tcg_gen_mov_tl(env_btaken, cpu_T[0]);
1182 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1184 /* Allow chaining. */
1185 dc->jmp = JMP_DIRECT;
1190 /* jumps, when the dest is in a live reg for example. Direct should be set
1191 when the dest addr is constant to allow tb chaining. */
1192 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1194 /* This helps us re-schedule the micro-code to insns in delay-slots
1195 before the actual jump. */
1196 dc->delayed_branch = 2;
1198 if (type == JMP_INDIRECT)
1199 tcg_gen_movi_tl(env_btaken, 1);
1202 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1203 unsigned int size, int sign)
1205 int mem_index = cpu_mmu_index(dc->env);
1207 /* If we get a fault on a delayslot we must keep the jmp state in
1208 the cpu-state to be able to re-execute the jmp. */
1209 if (dc->delayed_branch == 1)
1210 cris_store_direct_jmp(dc);
1214 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1216 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1218 else if (size == 2) {
1220 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1222 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1224 else if (size == 4) {
1225 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1227 else if (size == 8) {
1228 tcg_gen_qemu_ld64(dst, addr, mem_index);
1232 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1235 int mem_index = cpu_mmu_index(dc->env);
1237 /* If we get a fault on a delayslot we must keep the jmp state in
1238 the cpu-state to be able to re-execute the jmp. */
1239 if (dc->delayed_branch == 1)
1240 cris_store_direct_jmp(dc);
1243 /* Conditional writes. We only support the kind were X and P are known
1244 at translation time. */
1245 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1247 cris_evaluate_flags(dc);
1248 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1253 tcg_gen_qemu_st8(val, addr, mem_index);
1255 tcg_gen_qemu_st16(val, addr, mem_index);
1257 tcg_gen_qemu_st32(val, addr, mem_index);
1259 if (dc->flagx_known && dc->flags_x) {
1260 cris_evaluate_flags(dc);
1261 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1265 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1268 tcg_gen_ext8s_i32(d, s);
1270 tcg_gen_ext16s_i32(d, s);
1271 else if(GET_TCGV(d) != GET_TCGV(s))
1272 tcg_gen_mov_tl(d, s);
1275 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1278 tcg_gen_ext8u_i32(d, s);
1280 tcg_gen_ext16u_i32(d, s);
1281 else if (GET_TCGV(d) != GET_TCGV(s))
1282 tcg_gen_mov_tl(d, s);
1286 static char memsize_char(int size)
1290 case 1: return 'b'; break;
1291 case 2: return 'w'; break;
1292 case 4: return 'd'; break;
1300 static inline unsigned int memsize_z(DisasContext *dc)
1302 return dc->zsize + 1;
1305 static inline unsigned int memsize_zz(DisasContext *dc)
1316 static inline void do_postinc (DisasContext *dc, int size)
1319 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1322 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1323 int size, int s_ext, TCGv dst)
1326 t_gen_sext(dst, cpu_R[rs], size);
1328 t_gen_zext(dst, cpu_R[rs], size);
1331 /* Prepare T0 and T1 for a register alu operation.
1332 s_ext decides if the operand1 should be sign-extended or zero-extended when
1334 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1335 int size, int s_ext)
1337 dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
1340 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1342 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1345 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1348 unsigned int rs, rd;
1355 is_imm = rs == 15 && dc->postinc;
1357 /* Load [$rs] onto T1. */
1359 insn_len = 2 + memsize;
1366 imm = ldsb_code(dc->pc + 2);
1368 imm = ldsw_code(dc->pc + 2);
1371 imm = ldub_code(dc->pc + 2);
1373 imm = lduw_code(dc->pc + 2);
1376 imm = ldl_code(dc->pc + 2);
1378 tcg_gen_movi_tl(dst, imm);
1381 cris_flush_cc_state(dc);
1382 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1384 t_gen_sext(dst, dst, memsize);
1386 t_gen_zext(dst, dst, memsize);
1391 /* Prepare T0 and T1 for a memory + alu operation.
1392 s_ext decides if the operand1 should be sign-extended or zero-extended when
1394 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1398 insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
1400 /* put dest in T0. */
1401 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1406 static const char *cc_name(int cc)
1408 static const char *cc_names[16] = {
1409 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1410 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1413 return cc_names[cc];
1417 /* Start of insn decoders. */
1419 static unsigned int dec_bccq(DisasContext *dc)
1423 uint32_t cond = dc->op2;
1426 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1427 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1430 offset |= sign << 8;
1432 offset = sign_extend(offset, 8);
1434 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1436 /* op2 holds the condition-code. */
1437 cris_cc_mask(dc, 0);
1438 cris_prepare_cc_branch (dc, offset, cond);
1441 static unsigned int dec_addoq(DisasContext *dc)
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1446 imm = sign_extend(dc->op1, 7);
1448 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1449 cris_cc_mask(dc, 0);
1450 /* Fetch register operand, */
1451 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1454 static unsigned int dec_addq(DisasContext *dc)
1456 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1458 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1460 cris_cc_mask(dc, CC_MASK_NZVC);
1462 cris_alu(dc, CC_OP_ADD,
1463 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1466 static unsigned int dec_moveq(DisasContext *dc)
1470 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1471 imm = sign_extend(dc->op1, 5);
1472 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1474 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1477 static unsigned int dec_subq(DisasContext *dc)
1479 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1481 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1483 cris_cc_mask(dc, CC_MASK_NZVC);
1484 cris_alu(dc, CC_OP_SUB,
1485 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1488 static unsigned int dec_cmpq(DisasContext *dc)
1491 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1492 imm = sign_extend(dc->op1, 5);
1494 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1495 cris_cc_mask(dc, CC_MASK_NZVC);
1497 cris_alu(dc, CC_OP_CMP,
1498 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1501 static unsigned int dec_andq(DisasContext *dc)
1504 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1505 imm = sign_extend(dc->op1, 5);
1507 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1508 cris_cc_mask(dc, CC_MASK_NZ);
1510 cris_alu(dc, CC_OP_AND,
1511 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1514 static unsigned int dec_orq(DisasContext *dc)
1517 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1518 imm = sign_extend(dc->op1, 5);
1519 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1520 cris_cc_mask(dc, CC_MASK_NZ);
1522 cris_alu(dc, CC_OP_OR,
1523 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1526 static unsigned int dec_btstq(DisasContext *dc)
1528 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1529 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1531 cris_cc_mask(dc, CC_MASK_NZ);
1533 cris_alu(dc, CC_OP_BTST,
1534 cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1535 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1536 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1537 dc->flags_uptodate = 1;
1540 static unsigned int dec_asrq(DisasContext *dc)
1542 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1543 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1544 cris_cc_mask(dc, CC_MASK_NZ);
1546 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1547 cris_alu(dc, CC_OP_MOVE,
1549 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1552 static unsigned int dec_lslq(DisasContext *dc)
1554 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1555 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1557 cris_cc_mask(dc, CC_MASK_NZ);
1559 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1561 cris_alu(dc, CC_OP_MOVE,
1563 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1566 static unsigned int dec_lsrq(DisasContext *dc)
1568 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1569 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1571 cris_cc_mask(dc, CC_MASK_NZ);
1573 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1574 cris_alu(dc, CC_OP_MOVE,
1576 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1580 static unsigned int dec_move_r(DisasContext *dc)
1582 int size = memsize_zz(dc);
1584 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1585 memsize_char(size), dc->op1, dc->op2));
1587 cris_cc_mask(dc, CC_MASK_NZ);
1589 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1590 cris_cc_mask(dc, CC_MASK_NZ);
1591 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1592 cris_update_cc_x(dc);
1593 cris_update_result(dc, cpu_R[dc->op2]);
1596 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1597 cris_alu(dc, CC_OP_MOVE,
1599 cpu_R[dc->op2], cpu_T[1], size);
1604 static unsigned int dec_scc_r(DisasContext *dc)
1608 DIS(fprintf (logfile, "s%s $r%u\n",
1609 cc_name(cond), dc->op1));
1615 gen_tst_cc (dc, cond);
1617 l1 = gen_new_label();
1618 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1619 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
1620 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1624 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1626 cris_cc_mask(dc, 0);
1630 static unsigned int dec_and_r(DisasContext *dc)
1632 int size = memsize_zz(dc);
1634 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1635 memsize_char(size), dc->op1, dc->op2));
1636 cris_cc_mask(dc, CC_MASK_NZ);
1637 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1639 cris_alu(dc, CC_OP_AND,
1641 cpu_R[dc->op2], cpu_T[1], size);
1645 static unsigned int dec_lz_r(DisasContext *dc)
1647 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1649 cris_cc_mask(dc, CC_MASK_NZ);
1650 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1651 cris_alu(dc, CC_OP_LZ,
1652 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1656 static unsigned int dec_lsl_r(DisasContext *dc)
1658 int size = memsize_zz(dc);
1660 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1661 memsize_char(size), dc->op1, dc->op2));
1662 cris_cc_mask(dc, CC_MASK_NZ);
1663 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1664 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1666 cris_alu(dc, CC_OP_LSL,
1667 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1671 static unsigned int dec_lsr_r(DisasContext *dc)
1673 int size = memsize_zz(dc);
1675 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2));
1677 cris_cc_mask(dc, CC_MASK_NZ);
1678 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1679 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1681 cris_alu(dc, CC_OP_LSR,
1682 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1686 static unsigned int dec_asr_r(DisasContext *dc)
1688 int size = memsize_zz(dc);
1690 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1691 memsize_char(size), dc->op1, dc->op2));
1692 cris_cc_mask(dc, CC_MASK_NZ);
1693 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1694 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1696 cris_alu(dc, CC_OP_ASR,
1697 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1701 static unsigned int dec_muls_r(DisasContext *dc)
1703 int size = memsize_zz(dc);
1705 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1706 memsize_char(size), dc->op1, dc->op2));
1707 cris_cc_mask(dc, CC_MASK_NZV);
1708 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1710 cris_alu(dc, CC_OP_MULS,
1711 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1715 static unsigned int dec_mulu_r(DisasContext *dc)
1717 int size = memsize_zz(dc);
1719 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1720 memsize_char(size), dc->op1, dc->op2));
1721 cris_cc_mask(dc, CC_MASK_NZV);
1722 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1724 cris_alu(dc, CC_OP_MULU,
1725 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1730 static unsigned int dec_dstep_r(DisasContext *dc)
1732 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1733 cris_cc_mask(dc, CC_MASK_NZ);
1734 cris_alu(dc, CC_OP_DSTEP,
1735 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1739 static unsigned int dec_xor_r(DisasContext *dc)
1741 int size = memsize_zz(dc);
1742 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1743 memsize_char(size), dc->op1, dc->op2));
1744 BUG_ON(size != 4); /* xor is dword. */
1745 cris_cc_mask(dc, CC_MASK_NZ);
1746 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1748 cris_alu(dc, CC_OP_XOR,
1749 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1753 static unsigned int dec_bound_r(DisasContext *dc)
1755 int size = memsize_zz(dc);
1756 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1757 memsize_char(size), dc->op1, dc->op2));
1758 cris_cc_mask(dc, CC_MASK_NZ);
1759 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1760 cris_alu(dc, CC_OP_BOUND,
1761 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1765 static unsigned int dec_cmp_r(DisasContext *dc)
1767 int size = memsize_zz(dc);
1768 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1769 memsize_char(size), dc->op1, dc->op2));
1770 cris_cc_mask(dc, CC_MASK_NZVC);
1771 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1773 cris_alu(dc, CC_OP_CMP,
1774 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1778 static unsigned int dec_abs_r(DisasContext *dc)
1782 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1784 cris_cc_mask(dc, CC_MASK_NZ);
1785 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
1787 /* TODO: consider a branch free approach. */
1788 l1 = gen_new_label();
1789 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
1790 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
1792 cris_alu(dc, CC_OP_MOVE,
1793 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1797 static unsigned int dec_add_r(DisasContext *dc)
1799 int size = memsize_zz(dc);
1800 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1801 memsize_char(size), dc->op1, dc->op2));
1802 cris_cc_mask(dc, CC_MASK_NZVC);
1803 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1805 cris_alu(dc, CC_OP_ADD,
1806 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1810 static unsigned int dec_addc_r(DisasContext *dc)
1812 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1814 cris_evaluate_flags(dc);
1815 cris_cc_mask(dc, CC_MASK_NZVC);
1816 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1817 cris_alu(dc, CC_OP_ADDC,
1818 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1822 static unsigned int dec_mcp_r(DisasContext *dc)
1824 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1826 cris_evaluate_flags(dc);
1827 cris_cc_mask(dc, CC_MASK_RNZV);
1828 cris_alu(dc, CC_OP_MCP,
1829 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1834 static char * swapmode_name(int mode, char *modename) {
1837 modename[i++] = 'n';
1839 modename[i++] = 'w';
1841 modename[i++] = 'b';
1843 modename[i++] = 'r';
1849 static unsigned int dec_swap_r(DisasContext *dc)
1854 DIS(fprintf (logfile, "swap%s $r%u\n",
1855 swapmode_name(dc->op2, modename), dc->op1));
1857 cris_cc_mask(dc, CC_MASK_NZ);
1858 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1860 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
1862 t_gen_swapw(cpu_T[0], cpu_T[0]);
1864 t_gen_swapb(cpu_T[0], cpu_T[0]);
1866 t_gen_swapr(cpu_T[0], cpu_T[0]);
1867 cris_alu(dc, CC_OP_MOVE,
1868 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
1873 static unsigned int dec_or_r(DisasContext *dc)
1875 int size = memsize_zz(dc);
1876 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1877 memsize_char(size), dc->op1, dc->op2));
1878 cris_cc_mask(dc, CC_MASK_NZ);
1879 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1881 cris_alu(dc, CC_OP_OR,
1882 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1886 static unsigned int dec_addi_r(DisasContext *dc)
1888 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1889 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1890 cris_cc_mask(dc, 0);
1891 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1892 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
1896 static unsigned int dec_addi_acr(DisasContext *dc)
1898 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1899 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1900 cris_cc_mask(dc, 0);
1901 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1902 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
1906 static unsigned int dec_neg_r(DisasContext *dc)
1908 int size = memsize_zz(dc);
1909 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1910 memsize_char(size), dc->op1, dc->op2));
1911 cris_cc_mask(dc, CC_MASK_NZVC);
1912 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1914 cris_alu(dc, CC_OP_NEG,
1915 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1919 static unsigned int dec_btst_r(DisasContext *dc)
1921 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1923 cris_cc_mask(dc, CC_MASK_NZ);
1924 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1926 cris_alu(dc, CC_OP_BTST,
1927 cpu_T[0], cpu_T[0], cpu_T[1], 4);
1928 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1929 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1930 dc->flags_uptodate = 1;
1934 static unsigned int dec_sub_r(DisasContext *dc)
1936 int size = memsize_zz(dc);
1937 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1938 memsize_char(size), dc->op1, dc->op2));
1939 cris_cc_mask(dc, CC_MASK_NZVC);
1940 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1941 cris_alu(dc, CC_OP_SUB,
1942 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1946 /* Zero extension. From size to dword. */
1947 static unsigned int dec_movu_r(DisasContext *dc)
1949 int size = memsize_z(dc);
1950 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1954 cris_cc_mask(dc, CC_MASK_NZ);
1955 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1956 cris_alu(dc, CC_OP_MOVE,
1957 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1961 /* Sign extension. From size to dword. */
1962 static unsigned int dec_movs_r(DisasContext *dc)
1964 int size = memsize_z(dc);
1965 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1969 cris_cc_mask(dc, CC_MASK_NZ);
1970 /* Size can only be qi or hi. */
1971 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
1972 cris_alu(dc, CC_OP_MOVE,
1973 cpu_R[dc->op2], cpu_R[dc->op1], cpu_T[1], 4);
1977 /* zero extension. From size to dword. */
1978 static unsigned int dec_addu_r(DisasContext *dc)
1980 int size = memsize_z(dc);
1981 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1985 cris_cc_mask(dc, CC_MASK_NZVC);
1986 /* Size can only be qi or hi. */
1987 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
1988 cris_alu(dc, CC_OP_ADD,
1989 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1993 /* Sign extension. From size to dword. */
1994 static unsigned int dec_adds_r(DisasContext *dc)
1996 int size = memsize_z(dc);
1997 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2001 cris_cc_mask(dc, CC_MASK_NZVC);
2002 /* Size can only be qi or hi. */
2003 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2004 cris_alu(dc, CC_OP_ADD,
2005 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2009 /* Zero extension. From size to dword. */
2010 static unsigned int dec_subu_r(DisasContext *dc)
2012 int size = memsize_z(dc);
2013 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2017 cris_cc_mask(dc, CC_MASK_NZVC);
2018 /* Size can only be qi or hi. */
2019 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
2020 cris_alu(dc, CC_OP_SUB,
2021 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2025 /* Sign extension. From size to dword. */
2026 static unsigned int dec_subs_r(DisasContext *dc)
2028 int size = memsize_z(dc);
2029 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2033 cris_cc_mask(dc, CC_MASK_NZVC);
2034 /* Size can only be qi or hi. */
2035 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2036 cris_alu(dc, CC_OP_SUB,
2037 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2041 static unsigned int dec_setclrf(DisasContext *dc)
2044 int set = (~dc->opcode >> 2) & 1;
2046 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2047 | EXTRACT_FIELD(dc->ir, 0, 3);
2048 if (set && flags == 0) {
2049 DIS(fprintf (logfile, "nop\n"));
2051 } else if (!set && (flags & 0x20)) {
2052 DIS(fprintf (logfile, "di\n"));
2055 DIS(fprintf (logfile, "%sf %x\n",
2056 set ? "set" : "clr",
2060 /* User space is not allowed to touch these. Silently ignore. */
2061 if (dc->tb_flags & U_FLAG) {
2062 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2065 if (flags & X_FLAG) {
2066 dc->flagx_known = 1;
2068 dc->flags_x = X_FLAG;
2073 /* Break the TB if the P flag changes. */
2074 if (flags & P_FLAG) {
2075 if ((set && !(dc->tb_flags & P_FLAG))
2076 || (!set && (dc->tb_flags & P_FLAG))) {
2077 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2078 dc->is_jmp = DISAS_UPDATE;
2079 dc->cpustate_changed = 1;
2082 if (flags & S_FLAG) {
2083 dc->cpustate_changed = 1;
2087 /* Simply decode the flags. */
2088 cris_evaluate_flags (dc);
2089 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2090 cris_update_cc_x(dc);
2091 tcg_gen_movi_tl(cc_op, dc->cc_op);
2094 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2095 /* Enter user mode. */
2096 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2097 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2098 dc->cpustate_changed = 1;
2100 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2103 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2105 dc->flags_uptodate = 1;
2110 static unsigned int dec_move_rs(DisasContext *dc)
2112 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2113 cris_cc_mask(dc, 0);
2114 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2115 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2118 static unsigned int dec_move_sr(DisasContext *dc)
2120 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2121 cris_cc_mask(dc, 0);
2122 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2123 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2127 static unsigned int dec_move_rp(DisasContext *dc)
2129 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2130 cris_cc_mask(dc, 0);
2132 if (dc->op2 == PR_CCS) {
2133 cris_evaluate_flags(dc);
2134 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2135 if (dc->tb_flags & U_FLAG) {
2136 /* User space is not allowed to touch all flags. */
2137 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
2138 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
2139 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
2143 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2145 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
2146 if (dc->op2 == PR_CCS) {
2147 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2148 dc->flags_uptodate = 1;
2152 static unsigned int dec_move_pr(DisasContext *dc)
2154 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2155 cris_cc_mask(dc, 0);
2157 if (dc->op2 == PR_CCS)
2158 cris_evaluate_flags(dc);
2160 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2161 cris_alu(dc, CC_OP_MOVE,
2162 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
2163 preg_sizes[dc->op2]);
2167 static unsigned int dec_move_mr(DisasContext *dc)
2169 int memsize = memsize_zz(dc);
2171 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2172 memsize_char(memsize),
2173 dc->op1, dc->postinc ? "+]" : "]",
2177 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2178 cris_cc_mask(dc, CC_MASK_NZ);
2179 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2180 cris_update_cc_x(dc);
2181 cris_update_result(dc, cpu_R[dc->op2]);
2184 insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
2185 cris_cc_mask(dc, CC_MASK_NZ);
2186 cris_alu(dc, CC_OP_MOVE,
2187 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
2189 do_postinc(dc, memsize);
2193 static unsigned int dec_movs_m(DisasContext *dc)
2195 int memsize = memsize_z(dc);
2197 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2198 memsize_char(memsize),
2199 dc->op1, dc->postinc ? "+]" : "]",
2203 insn_len = dec_prep_alu_m(dc, 1, memsize);
2204 cris_cc_mask(dc, CC_MASK_NZ);
2205 cris_alu(dc, CC_OP_MOVE,
2206 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2207 do_postinc(dc, memsize);
2211 static unsigned int dec_addu_m(DisasContext *dc)
2213 int memsize = memsize_z(dc);
2215 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2216 memsize_char(memsize),
2217 dc->op1, dc->postinc ? "+]" : "]",
2221 insn_len = dec_prep_alu_m(dc, 0, memsize);
2222 cris_cc_mask(dc, CC_MASK_NZVC);
2223 cris_alu(dc, CC_OP_ADD,
2224 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2225 do_postinc(dc, memsize);
2229 static unsigned int dec_adds_m(DisasContext *dc)
2231 int memsize = memsize_z(dc);
2233 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2234 memsize_char(memsize),
2235 dc->op1, dc->postinc ? "+]" : "]",
2239 insn_len = dec_prep_alu_m(dc, 1, memsize);
2240 cris_cc_mask(dc, CC_MASK_NZVC);
2241 cris_alu(dc, CC_OP_ADD,
2242 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2243 do_postinc(dc, memsize);
2247 static unsigned int dec_subu_m(DisasContext *dc)
2249 int memsize = memsize_z(dc);
2251 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2252 memsize_char(memsize),
2253 dc->op1, dc->postinc ? "+]" : "]",
2257 insn_len = dec_prep_alu_m(dc, 0, memsize);
2258 cris_cc_mask(dc, CC_MASK_NZVC);
2259 cris_alu(dc, CC_OP_SUB,
2260 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2261 do_postinc(dc, memsize);
2265 static unsigned int dec_subs_m(DisasContext *dc)
2267 int memsize = memsize_z(dc);
2269 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2270 memsize_char(memsize),
2271 dc->op1, dc->postinc ? "+]" : "]",
2275 insn_len = dec_prep_alu_m(dc, 1, memsize);
2276 cris_cc_mask(dc, CC_MASK_NZVC);
2277 cris_alu(dc, CC_OP_SUB,
2278 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2279 do_postinc(dc, memsize);
2283 static unsigned int dec_movu_m(DisasContext *dc)
2285 int memsize = memsize_z(dc);
2288 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2289 memsize_char(memsize),
2290 dc->op1, dc->postinc ? "+]" : "]",
2293 insn_len = dec_prep_alu_m(dc, 0, memsize);
2294 cris_cc_mask(dc, CC_MASK_NZ);
2295 cris_alu(dc, CC_OP_MOVE,
2296 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2297 do_postinc(dc, memsize);
2301 static unsigned int dec_cmpu_m(DisasContext *dc)
2303 int memsize = memsize_z(dc);
2305 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2306 memsize_char(memsize),
2307 dc->op1, dc->postinc ? "+]" : "]",
2310 insn_len = dec_prep_alu_m(dc, 0, memsize);
2311 cris_cc_mask(dc, CC_MASK_NZVC);
2312 cris_alu(dc, CC_OP_CMP,
2313 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2314 do_postinc(dc, memsize);
2318 static unsigned int dec_cmps_m(DisasContext *dc)
2320 int memsize = memsize_z(dc);
2322 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2323 memsize_char(memsize),
2324 dc->op1, dc->postinc ? "+]" : "]",
2327 insn_len = dec_prep_alu_m(dc, 1, memsize);
2328 cris_cc_mask(dc, CC_MASK_NZVC);
2329 cris_alu(dc, CC_OP_CMP,
2330 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2332 do_postinc(dc, memsize);
2336 static unsigned int dec_cmp_m(DisasContext *dc)
2338 int memsize = memsize_zz(dc);
2340 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2341 memsize_char(memsize),
2342 dc->op1, dc->postinc ? "+]" : "]",
2345 insn_len = dec_prep_alu_m(dc, 0, memsize);
2346 cris_cc_mask(dc, CC_MASK_NZVC);
2347 cris_alu(dc, CC_OP_CMP,
2348 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2350 do_postinc(dc, memsize);
2354 static unsigned int dec_test_m(DisasContext *dc)
2356 int memsize = memsize_zz(dc);
2358 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2359 memsize_char(memsize),
2360 dc->op1, dc->postinc ? "+]" : "]",
2363 cris_evaluate_flags(dc);
2365 insn_len = dec_prep_alu_m(dc, 0, memsize);
2366 cris_cc_mask(dc, CC_MASK_NZ);
2367 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2369 cris_alu(dc, CC_OP_CMP,
2370 cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
2372 do_postinc(dc, memsize);
2376 static unsigned int dec_and_m(DisasContext *dc)
2378 int memsize = memsize_zz(dc);
2380 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2381 memsize_char(memsize),
2382 dc->op1, dc->postinc ? "+]" : "]",
2385 insn_len = dec_prep_alu_m(dc, 0, memsize);
2386 cris_cc_mask(dc, CC_MASK_NZ);
2387 cris_alu(dc, CC_OP_AND,
2388 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2390 do_postinc(dc, memsize);
2394 static unsigned int dec_add_m(DisasContext *dc)
2396 int memsize = memsize_zz(dc);
2398 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2399 memsize_char(memsize),
2400 dc->op1, dc->postinc ? "+]" : "]",
2403 insn_len = dec_prep_alu_m(dc, 0, memsize);
2404 cris_cc_mask(dc, CC_MASK_NZVC);
2405 cris_alu(dc, CC_OP_ADD,
2406 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2408 do_postinc(dc, memsize);
2412 static unsigned int dec_addo_m(DisasContext *dc)
2414 int memsize = memsize_zz(dc);
2416 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2417 memsize_char(memsize),
2418 dc->op1, dc->postinc ? "+]" : "]",
2421 insn_len = dec_prep_alu_m(dc, 1, memsize);
2422 cris_cc_mask(dc, 0);
2423 cris_alu(dc, CC_OP_ADD,
2424 cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
2425 do_postinc(dc, memsize);
2429 static unsigned int dec_bound_m(DisasContext *dc)
2431 int memsize = memsize_zz(dc);
2433 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2434 memsize_char(memsize),
2435 dc->op1, dc->postinc ? "+]" : "]",
2438 insn_len = dec_prep_alu_m(dc, 0, memsize);
2439 cris_cc_mask(dc, CC_MASK_NZ);
2440 cris_alu(dc, CC_OP_BOUND,
2441 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2442 do_postinc(dc, memsize);
2446 static unsigned int dec_addc_mr(DisasContext *dc)
2449 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2450 dc->op1, dc->postinc ? "+]" : "]",
2453 cris_evaluate_flags(dc);
2454 insn_len = dec_prep_alu_m(dc, 0, 4);
2455 cris_cc_mask(dc, CC_MASK_NZVC);
2456 cris_alu(dc, CC_OP_ADDC,
2457 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2462 static unsigned int dec_sub_m(DisasContext *dc)
2464 int memsize = memsize_zz(dc);
2466 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2467 memsize_char(memsize),
2468 dc->op1, dc->postinc ? "+]" : "]",
2469 dc->op2, dc->ir, dc->zzsize));
2471 insn_len = dec_prep_alu_m(dc, 0, memsize);
2472 cris_cc_mask(dc, CC_MASK_NZVC);
2473 cris_alu(dc, CC_OP_SUB,
2474 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
2475 do_postinc(dc, memsize);
2479 static unsigned int dec_or_m(DisasContext *dc)
2481 int memsize = memsize_zz(dc);
2483 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2484 memsize_char(memsize),
2485 dc->op1, dc->postinc ? "+]" : "]",
2488 insn_len = dec_prep_alu_m(dc, 0, memsize);
2489 cris_cc_mask(dc, CC_MASK_NZ);
2490 cris_alu(dc, CC_OP_OR,
2491 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
2492 do_postinc(dc, memsize);
2496 static unsigned int dec_move_mp(DisasContext *dc)
2498 int memsize = memsize_zz(dc);
2501 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2502 memsize_char(memsize),
2504 dc->postinc ? "+]" : "]",
2507 insn_len = dec_prep_alu_m(dc, 0, memsize);
2508 cris_cc_mask(dc, 0);
2509 if (dc->op2 == PR_CCS) {
2510 cris_evaluate_flags(dc);
2511 if (dc->tb_flags & U_FLAG) {
2512 /* User space is not allowed to touch all flags. */
2513 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2514 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2515 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2519 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
2521 do_postinc(dc, memsize);
2525 static unsigned int dec_move_pm(DisasContext *dc)
2529 memsize = preg_sizes[dc->op2];
2531 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2532 memsize_char(memsize),
2533 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2535 /* prepare store. Address in T0, value in T1. */
2536 if (dc->op2 == PR_CCS)
2537 cris_evaluate_flags(dc);
2538 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2539 cris_flush_cc_state(dc);
2540 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2542 cris_cc_mask(dc, 0);
2544 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2548 static unsigned int dec_movem_mr(DisasContext *dc)
2552 int nr = dc->op2 + 1;
2554 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2555 dc->postinc ? "+]" : "]", dc->op2));
2557 /* There are probably better ways of doing this. */
2558 cris_flush_cc_state(dc);
2559 for (i = 0; i < (nr >> 1); i++) {
2560 tmp[i] = tcg_temp_new(TCG_TYPE_I64);
2561 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2562 gen_load(dc, tmp[i], cpu_T[0], 8, 0);
2565 tmp[i] = tcg_temp_new(TCG_TYPE_I32);
2566 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2567 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2570 for (i = 0; i < (nr >> 1); i++) {
2571 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2572 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2573 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2574 tcg_temp_free(tmp[i]);
2577 tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]);
2578 tcg_temp_free(tmp[i]);
2581 /* writeback the updated pointer value. */
2583 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2585 /* gen_load might want to evaluate the previous insns flags. */
2586 cris_cc_mask(dc, 0);
2590 static unsigned int dec_movem_rm(DisasContext *dc)
2595 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2596 dc->postinc ? "+]" : "]"));
2598 cris_flush_cc_state(dc);
2600 tmp = tcg_temp_new(TCG_TYPE_TL);
2601 tcg_gen_movi_tl(tmp, 4);
2602 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
2603 for (i = 0; i <= dc->op2; i++) {
2604 /* Displace addr. */
2605 /* Perform the store. */
2606 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2607 tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
2610 tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
2611 cris_cc_mask(dc, 0);
2616 static unsigned int dec_move_rm(DisasContext *dc)
2620 memsize = memsize_zz(dc);
2622 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2623 memsize, dc->op2, dc->op1));
2625 /* prepare store. */
2626 cris_flush_cc_state(dc);
2627 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2630 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2631 cris_cc_mask(dc, 0);
2635 static unsigned int dec_lapcq(DisasContext *dc)
2637 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2638 dc->pc + dc->op1*2, dc->op2));
2639 cris_cc_mask(dc, 0);
2640 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2644 static unsigned int dec_lapc_im(DisasContext *dc)
2652 cris_cc_mask(dc, 0);
2653 imm = ldl_code(dc->pc + 2);
2654 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2658 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2662 /* Jump to special reg. */
2663 static unsigned int dec_jump_p(DisasContext *dc)
2665 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2667 if (dc->op2 == PR_CCS)
2668 cris_evaluate_flags(dc);
2669 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2670 /* rete will often have low bit set to indicate delayslot. */
2671 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2672 cris_cc_mask(dc, 0);
2673 cris_prepare_jmp(dc, JMP_INDIRECT);
2677 /* Jump and save. */
2678 static unsigned int dec_jas_r(DisasContext *dc)
2680 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2681 cris_cc_mask(dc, 0);
2682 /* Store the return address in Pd. */
2683 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2686 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2688 cris_prepare_jmp(dc, JMP_INDIRECT);
2692 static unsigned int dec_jas_im(DisasContext *dc)
2696 imm = ldl_code(dc->pc + 2);
2698 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2699 cris_cc_mask(dc, 0);
2700 /* Store the return address in Pd. */
2701 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2704 cris_prepare_jmp(dc, JMP_DIRECT);
2708 static unsigned int dec_jasc_im(DisasContext *dc)
2712 imm = ldl_code(dc->pc + 2);
2714 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2715 cris_cc_mask(dc, 0);
2716 /* Store the return address in Pd. */
2717 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2720 cris_prepare_jmp(dc, JMP_DIRECT);
2724 static unsigned int dec_jasc_r(DisasContext *dc)
2726 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2727 cris_cc_mask(dc, 0);
2728 /* Store the return address in Pd. */
2729 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2730 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2731 cris_prepare_jmp(dc, JMP_INDIRECT);
2735 static unsigned int dec_bcc_im(DisasContext *dc)
2738 uint32_t cond = dc->op2;
2740 offset = ldsw_code(dc->pc + 2);
2742 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2743 cc_name(cond), offset,
2744 dc->pc, dc->pc + offset));
2746 cris_cc_mask(dc, 0);
2747 /* op2 holds the condition-code. */
2748 cris_prepare_cc_branch (dc, offset, cond);
2752 static unsigned int dec_bas_im(DisasContext *dc)
2757 simm = ldl_code(dc->pc + 2);
2759 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2760 cris_cc_mask(dc, 0);
2761 /* Store the return address in Pd. */
2762 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2764 dc->jmp_pc = dc->pc + simm;
2765 cris_prepare_jmp(dc, JMP_DIRECT);
2769 static unsigned int dec_basc_im(DisasContext *dc)
2772 simm = ldl_code(dc->pc + 2);
2774 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2775 cris_cc_mask(dc, 0);
2776 /* Store the return address in Pd. */
2777 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2779 dc->jmp_pc = dc->pc + simm;
2780 cris_prepare_jmp(dc, JMP_DIRECT);
2784 static unsigned int dec_rfe_etc(DisasContext *dc)
2786 cris_cc_mask(dc, 0);
2788 if (dc->op2 == 15) /* ignore halt. */
2791 switch (dc->op2 & 7) {
2794 DIS(fprintf(logfile, "rfe\n"));
2795 cris_evaluate_flags(dc);
2796 tcg_gen_helper_0_0(helper_rfe);
2797 dc->is_jmp = DISAS_UPDATE;
2801 DIS(fprintf(logfile, "rfn\n"));
2802 cris_evaluate_flags(dc);
2803 tcg_gen_helper_0_0(helper_rfn);
2804 dc->is_jmp = DISAS_UPDATE;
2807 DIS(fprintf(logfile, "break %d\n", dc->op1));
2808 cris_evaluate_flags (dc);
2810 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2812 /* Breaks start at 16 in the exception vector. */
2813 t_gen_mov_env_TN(trap_vector,
2814 tcg_const_tl(dc->op1 + 16));
2815 t_gen_raise_exception(EXCP_BREAK);
2816 dc->is_jmp = DISAS_UPDATE;
2819 printf ("op2=%x\n", dc->op2);
2827 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2829 /* Ignore D-cache flushes. */
2833 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2835 /* Ignore I-cache flushes. */
2839 static unsigned int dec_null(DisasContext *dc)
2841 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2842 dc->pc, dc->opcode, dc->op1, dc->op2);
2848 static struct decoder_info {
2853 unsigned int (*dec)(DisasContext *dc);
2855 /* Order matters here. */
2856 {DEC_MOVEQ, dec_moveq},
2857 {DEC_BTSTQ, dec_btstq},
2858 {DEC_CMPQ, dec_cmpq},
2859 {DEC_ADDOQ, dec_addoq},
2860 {DEC_ADDQ, dec_addq},
2861 {DEC_SUBQ, dec_subq},
2862 {DEC_ANDQ, dec_andq},
2864 {DEC_ASRQ, dec_asrq},
2865 {DEC_LSLQ, dec_lslq},
2866 {DEC_LSRQ, dec_lsrq},
2867 {DEC_BCCQ, dec_bccq},
2869 {DEC_BCC_IM, dec_bcc_im},
2870 {DEC_JAS_IM, dec_jas_im},
2871 {DEC_JAS_R, dec_jas_r},
2872 {DEC_JASC_IM, dec_jasc_im},
2873 {DEC_JASC_R, dec_jasc_r},
2874 {DEC_BAS_IM, dec_bas_im},
2875 {DEC_BASC_IM, dec_basc_im},
2876 {DEC_JUMP_P, dec_jump_p},
2877 {DEC_LAPC_IM, dec_lapc_im},
2878 {DEC_LAPCQ, dec_lapcq},
2880 {DEC_RFE_ETC, dec_rfe_etc},
2881 {DEC_ADDC_MR, dec_addc_mr},
2883 {DEC_MOVE_MP, dec_move_mp},
2884 {DEC_MOVE_PM, dec_move_pm},
2885 {DEC_MOVEM_MR, dec_movem_mr},
2886 {DEC_MOVEM_RM, dec_movem_rm},
2887 {DEC_MOVE_PR, dec_move_pr},
2888 {DEC_SCC_R, dec_scc_r},
2889 {DEC_SETF, dec_setclrf},
2890 {DEC_CLEARF, dec_setclrf},
2892 {DEC_MOVE_SR, dec_move_sr},
2893 {DEC_MOVE_RP, dec_move_rp},
2894 {DEC_SWAP_R, dec_swap_r},
2895 {DEC_ABS_R, dec_abs_r},
2896 {DEC_LZ_R, dec_lz_r},
2897 {DEC_MOVE_RS, dec_move_rs},
2898 {DEC_BTST_R, dec_btst_r},
2899 {DEC_ADDC_R, dec_addc_r},
2901 {DEC_DSTEP_R, dec_dstep_r},
2902 {DEC_XOR_R, dec_xor_r},
2903 {DEC_MCP_R, dec_mcp_r},
2904 {DEC_CMP_R, dec_cmp_r},
2906 {DEC_ADDI_R, dec_addi_r},
2907 {DEC_ADDI_ACR, dec_addi_acr},
2909 {DEC_ADD_R, dec_add_r},
2910 {DEC_SUB_R, dec_sub_r},
2912 {DEC_ADDU_R, dec_addu_r},
2913 {DEC_ADDS_R, dec_adds_r},
2914 {DEC_SUBU_R, dec_subu_r},
2915 {DEC_SUBS_R, dec_subs_r},
2916 {DEC_LSL_R, dec_lsl_r},
2918 {DEC_AND_R, dec_and_r},
2919 {DEC_OR_R, dec_or_r},
2920 {DEC_BOUND_R, dec_bound_r},
2921 {DEC_ASR_R, dec_asr_r},
2922 {DEC_LSR_R, dec_lsr_r},
2924 {DEC_MOVU_R, dec_movu_r},
2925 {DEC_MOVS_R, dec_movs_r},
2926 {DEC_NEG_R, dec_neg_r},
2927 {DEC_MOVE_R, dec_move_r},
2929 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2930 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2932 {DEC_MULS_R, dec_muls_r},
2933 {DEC_MULU_R, dec_mulu_r},
2935 {DEC_ADDU_M, dec_addu_m},
2936 {DEC_ADDS_M, dec_adds_m},
2937 {DEC_SUBU_M, dec_subu_m},
2938 {DEC_SUBS_M, dec_subs_m},
2940 {DEC_CMPU_M, dec_cmpu_m},
2941 {DEC_CMPS_M, dec_cmps_m},
2942 {DEC_MOVU_M, dec_movu_m},
2943 {DEC_MOVS_M, dec_movs_m},
2945 {DEC_CMP_M, dec_cmp_m},
2946 {DEC_ADDO_M, dec_addo_m},
2947 {DEC_BOUND_M, dec_bound_m},
2948 {DEC_ADD_M, dec_add_m},
2949 {DEC_SUB_M, dec_sub_m},
2950 {DEC_AND_M, dec_and_m},
2951 {DEC_OR_M, dec_or_m},
2952 {DEC_MOVE_RM, dec_move_rm},
2953 {DEC_TEST_M, dec_test_m},
2954 {DEC_MOVE_MR, dec_move_mr},
2959 static inline unsigned int
2960 cris_decoder(DisasContext *dc)
2962 unsigned int insn_len = 2;
2965 if (unlikely(loglevel & CPU_LOG_TB_OP))
2966 tcg_gen_debug_insn_start(dc->pc);
2968 /* Load a halfword onto the instruction register. */
2969 dc->ir = lduw_code(dc->pc);
2971 /* Now decode it. */
2972 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2973 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2974 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2975 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2976 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2977 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2979 /* Large switch for all insns. */
2980 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2981 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2983 insn_len = decinfo[i].dec(dc);
2988 #if !defined(CONFIG_USER_ONLY)
2989 /* Single-stepping ? */
2990 if (dc->tb_flags & S_FLAG) {
2993 l1 = gen_new_label();
2994 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
2995 /* We treat SPC as a break with an odd trap vector. */
2996 cris_evaluate_flags (dc);
2997 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
2998 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
2999 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3000 t_gen_raise_exception(EXCP_BREAK);
3007 static void check_breakpoint(CPUState *env, DisasContext *dc)
3010 if (env->nb_breakpoints > 0) {
3011 for(j = 0; j < env->nb_breakpoints; j++) {
3012 if (env->breakpoints[j] == dc->pc) {
3013 cris_evaluate_flags (dc);
3014 tcg_gen_movi_tl(env_pc, dc->pc);
3015 t_gen_raise_exception(EXCP_DEBUG);
3016 dc->is_jmp = DISAS_UPDATE;
3024 * Delay slots on QEMU/CRIS.
3026 * If an exception hits on a delayslot, the core will let ERP (the Exception
3027 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3028 * to give SW a hint that the exception actually hit on the dslot.
3030 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3031 * the core and any jmp to an odd addresses will mask off that lsb. It is
3032 * simply there to let sw know there was an exception on a dslot.
3034 * When the software returns from an exception, the branch will re-execute.
3035 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3036 * and the branch and delayslot dont share pages.
3038 * The TB contaning the branch insn will set up env->btarget and evaluate
3039 * env->btaken. When the translation loop exits we will note that the branch
3040 * sequence is broken and let env->dslot be the size of the branch insn (those
3043 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3044 * set). It will also expect to have env->dslot setup with the size of the
3045 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3046 * will execute the dslot and take the branch, either to btarget or just one
3049 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3050 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3051 * branch and set lsb). Then env->dslot gets cleared so that the exception
3052 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3053 * masked off and we will reexecute the branch insn.
3057 /* generate intermediate code for basic block 'tb'. */
3059 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3062 uint16_t *gen_opc_end;
3064 unsigned int insn_len;
3066 struct DisasContext ctx;
3067 struct DisasContext *dc = &ctx;
3068 uint32_t next_page_start;
3076 /* Odd PC indicates that branch is rexecuting due to exception in the
3077 * delayslot, like in real hw.
3079 pc_start = tb->pc & ~1;
3083 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3085 dc->is_jmp = DISAS_NEXT;
3088 dc->singlestep_enabled = env->singlestep_enabled;
3089 dc->flags_uptodate = 1;
3090 dc->flagx_known = 1;
3091 dc->flags_x = tb->flags & X_FLAG;
3092 dc->cc_x_uptodate = 0;
3096 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3097 dc->cc_size_uptodate = -1;
3099 /* Decode TB flags. */
3100 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3101 dc->delayed_branch = !!(tb->flags & 7);
3102 if (dc->delayed_branch)
3103 dc->jmp = JMP_INDIRECT;
3105 dc->jmp = JMP_NOJMP;
3107 dc->cpustate_changed = 0;
3109 if (loglevel & CPU_LOG_TB_IN_ASM) {
3111 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3117 search_pc, dc->pc, dc->ppc,
3118 (unsigned long long)tb->flags,
3119 env->btarget, (unsigned)tb->flags & 7,
3121 env->pregs[PR_PID], env->pregs[PR_USP],
3122 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3123 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3124 env->regs[8], env->regs[9],
3125 env->regs[10], env->regs[11],
3126 env->regs[12], env->regs[13],
3127 env->regs[14], env->regs[15]);
3128 fprintf(logfile, "--------------\n");
3129 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3132 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3135 max_insns = tb->cflags & CF_COUNT_MASK;
3137 max_insns = CF_COUNT_MASK;
3142 check_breakpoint(env, dc);
3145 j = gen_opc_ptr - gen_opc_buf;
3149 gen_opc_instr_start[lj++] = 0;
3151 if (dc->delayed_branch == 1)
3152 gen_opc_pc[lj] = dc->ppc | 1;
3154 gen_opc_pc[lj] = dc->pc;
3155 gen_opc_instr_start[lj] = 1;
3156 gen_opc_icount[lj] = num_insns;
3160 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3162 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3166 insn_len = cris_decoder(dc);
3170 cris_clear_x_flag(dc);
3173 /* Check for delayed branches here. If we do it before
3174 actually generating any host code, the simulator will just
3175 loop doing nothing for on this program location. */
3176 if (dc->delayed_branch) {
3177 dc->delayed_branch--;
3178 if (dc->delayed_branch == 0)
3181 t_gen_mov_env_TN(dslot,
3183 if (dc->jmp == JMP_DIRECT) {
3184 dc->is_jmp = DISAS_NEXT;
3186 t_gen_cc_jmp(env_btarget,
3187 tcg_const_tl(dc->pc));
3188 dc->is_jmp = DISAS_JUMP;
3194 /* If we are rexecuting a branch due to exceptions on
3195 delay slots dont break. */
3196 if (!(tb->pc & 1) && env->singlestep_enabled)
3198 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
3199 && (dc->pc < next_page_start)
3200 && num_insns < max_insns);
3203 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3206 if (tb->cflags & CF_LAST_IO)
3208 /* Force an update if the per-tb cpu state has changed. */
3209 if (dc->is_jmp == DISAS_NEXT
3210 && (dc->cpustate_changed || !dc->flagx_known
3211 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3212 dc->is_jmp = DISAS_UPDATE;
3213 tcg_gen_movi_tl(env_pc, npc);
3215 /* Broken branch+delayslot sequence. */
3216 if (dc->delayed_branch == 1) {
3217 /* Set env->dslot to the size of the branch insn. */
3218 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3219 cris_store_direct_jmp(dc);
3222 cris_evaluate_flags (dc);
3224 if (unlikely(env->singlestep_enabled)) {
3225 if (dc->is_jmp == DISAS_NEXT)
3226 tcg_gen_movi_tl(env_pc, npc);
3227 t_gen_raise_exception(EXCP_DEBUG);
3229 switch(dc->is_jmp) {
3231 gen_goto_tb(dc, 1, npc);
3236 /* indicate that the hash table must be used
3237 to find the next TB */
3242 /* nothing more to generate */
3246 gen_icount_end(tb, num_insns);
3247 *gen_opc_ptr = INDEX_op_end;
3249 j = gen_opc_ptr - gen_opc_buf;
3252 gen_opc_instr_start[lj++] = 0;
3254 tb->size = dc->pc - pc_start;
3255 tb->icount = num_insns;
3260 if (loglevel & CPU_LOG_TB_IN_ASM) {
3261 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3262 fprintf(logfile, "\nisize=%d osize=%zd\n",
3263 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3269 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3271 gen_intermediate_code_internal(env, tb, 0);
3274 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3276 gen_intermediate_code_internal(env, tb, 1);
3279 void cpu_dump_state (CPUState *env, FILE *f,
3280 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3289 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3290 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3291 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3293 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3296 for (i = 0; i < 16; i++) {
3297 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3298 if ((i + 1) % 4 == 0)
3299 cpu_fprintf(f, "\n");
3301 cpu_fprintf(f, "\nspecial regs:\n");
3302 for (i = 0; i < 16; i++) {
3303 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3304 if ((i + 1) % 4 == 0)
3305 cpu_fprintf(f, "\n");
3307 srs = env->pregs[PR_SRS];
3308 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3310 for (i = 0; i < 16; i++) {
3311 cpu_fprintf(f, "s%2.2d=%8.8x ",
3312 i, env->sregs[srs][i]);
3313 if ((i + 1) % 4 == 0)
3314 cpu_fprintf(f, "\n");
3317 cpu_fprintf(f, "\n\n");
3321 CPUCRISState *cpu_cris_init (const char *cpu_model)
3324 static int tcg_initialized = 0;
3327 env = qemu_mallocz(sizeof(CPUCRISState));
3334 if (tcg_initialized)
3337 tcg_initialized = 1;
3339 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3340 #if TARGET_LONG_BITS > HOST_LONG_BITS
3341 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3342 TCG_AREG0, offsetof(CPUState, t0), "T0");
3343 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3344 TCG_AREG0, offsetof(CPUState, t1), "T1");
3346 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3347 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3350 cc_x = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3351 offsetof(CPUState, cc_x), "cc_x");
3352 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3353 offsetof(CPUState, cc_src), "cc_src");
3354 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3355 offsetof(CPUState, cc_dest),
3357 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3358 offsetof(CPUState, cc_result),
3360 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3361 offsetof(CPUState, cc_op), "cc_op");
3362 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3363 offsetof(CPUState, cc_size),
3365 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3366 offsetof(CPUState, cc_mask),
3369 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3370 offsetof(CPUState, pc),
3372 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3373 offsetof(CPUState, btarget),
3375 env_btaken = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3376 offsetof(CPUState, btaken),
3378 for (i = 0; i < 16; i++) {
3379 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3380 offsetof(CPUState, regs[i]),
3383 for (i = 0; i < 16; i++) {
3384 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3385 offsetof(CPUState, pregs[i]),
3389 TCG_HELPER(helper_raise_exception);
3390 TCG_HELPER(helper_dump);
3392 TCG_HELPER(helper_tlb_flush_pid);
3393 TCG_HELPER(helper_movl_sreg_reg);
3394 TCG_HELPER(helper_movl_reg_sreg);
3395 TCG_HELPER(helper_rfe);
3396 TCG_HELPER(helper_rfn);
3398 TCG_HELPER(helper_evaluate_flags_muls);
3399 TCG_HELPER(helper_evaluate_flags_mulu);
3400 TCG_HELPER(helper_evaluate_flags_mcp);
3401 TCG_HELPER(helper_evaluate_flags_alu_4);
3402 TCG_HELPER(helper_evaluate_flags_move_4);
3403 TCG_HELPER(helper_evaluate_flags_move_2);
3404 TCG_HELPER(helper_evaluate_flags);
3405 TCG_HELPER(helper_top_evaluate_flags);
3409 void cpu_reset (CPUCRISState *env)
3411 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3414 env->pregs[PR_VR] = 32;
3415 #if defined(CONFIG_USER_ONLY)
3416 /* start in user mode with interrupts enabled. */
3417 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3419 env->pregs[PR_CCS] = 0;
3423 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3424 unsigned long searched_pc, int pc_pos, void *puc)
3426 env->pc = gen_opc_pc[pc_pos];