2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
44 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
66 static TCGv cpu_R[16];
67 static TCGv cpu_PR[16];
71 static TCGv cc_result;
76 static TCGv env_btaken;
77 static TCGv env_btarget;
80 #include "gen-icount.h"
82 /* This is the state at translation time. */
83 typedef struct DisasContext {
92 unsigned int zsize, zzsize;
101 int cc_size_uptodate; /* -1 invalid or last written value. */
103 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
104 int flags_uptodate; /* Wether or not $ccs is uptodate. */
105 int flagx_known; /* Wether or not flags_x has the x flag known at
109 int clear_x; /* Clear x after this insn? */
110 int cpustate_changed;
111 unsigned int tb_flags; /* tb dependent flags. */
116 #define JMP_INDIRECT 2
117 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
122 struct TranslationBlock *tb;
123 int singlestep_enabled;
126 static void gen_BUG(DisasContext *dc, const char *file, int line)
128 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
129 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
130 cpu_abort(dc->env, "%s:%d\n", file, line);
133 static const char *regnames[] =
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
140 static const char *pregnames[] =
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
148 /* We need this table to handle preg-moves with implicit width. */
149 static int preg_sizes[] = {
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EDA) {
200 printf("read from EDA!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
209 fprintf(stderr, "wrong register write $p%d\n", r);
210 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
212 else if (r == PR_SRS)
213 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
216 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
217 if (dc->tb_flags & S_FLAG && r == PR_SPC)
218 tcg_gen_helper_0_1(helper_spc_write, tn);
219 else if (r == PR_CCS)
220 dc->cpustate_changed = 1;
221 tcg_gen_mov_tl(cpu_PR[r], tn);
225 static inline void t_gen_raise_exception(uint32_t index)
227 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
230 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
234 t0 = tcg_temp_new(TCG_TYPE_TL);
235 t_31 = tcg_temp_new(TCG_TYPE_TL);
236 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_movi_tl(t_31, 31);
239 tcg_gen_sub_tl(t0, t_31, b);
240 tcg_gen_sar_tl(t0, t0, t_31);
241 tcg_gen_and_tl(t0, t0, d);
242 tcg_gen_xor_tl(d, d, t0);
247 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
251 t0 = tcg_temp_new(TCG_TYPE_TL);
252 t_31 = tcg_temp_new(TCG_TYPE_TL);
253 tcg_gen_shr_tl(d, a, b);
255 tcg_gen_movi_tl(t_31, 31);
256 tcg_gen_sub_tl(t0, t_31, b);
257 tcg_gen_sar_tl(t0, t0, t_31);
258 tcg_gen_and_tl(t0, t0, d);
259 tcg_gen_xor_tl(d, d, t0);
264 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
268 t0 = tcg_temp_new(TCG_TYPE_TL);
269 t_31 = tcg_temp_new(TCG_TYPE_TL);
270 tcg_gen_sar_tl(d, a, b);
272 tcg_gen_movi_tl(t_31, 31);
273 tcg_gen_sub_tl(t0, t_31, b);
274 tcg_gen_sar_tl(t0, t0, t_31);
275 tcg_gen_or_tl(d, d, t0);
280 /* 64-bit signed mul, lower result in d and upper in d2. */
281 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
285 t0 = tcg_temp_new(TCG_TYPE_I64);
286 t1 = tcg_temp_new(TCG_TYPE_I64);
288 tcg_gen_ext32s_i64(t0, a);
289 tcg_gen_ext32s_i64(t1, b);
290 tcg_gen_mul_i64(t0, t0, t1);
292 tcg_gen_trunc_i64_i32(d, t0);
293 tcg_gen_shri_i64(t0, t0, 32);
294 tcg_gen_trunc_i64_i32(d2, t0);
300 /* 64-bit unsigned muls, lower result in d and upper in d2. */
301 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
305 t0 = tcg_temp_new(TCG_TYPE_I64);
306 t1 = tcg_temp_new(TCG_TYPE_I64);
308 tcg_gen_extu_i32_i64(t0, a);
309 tcg_gen_extu_i32_i64(t1, b);
310 tcg_gen_mul_i64(t0, t0, t1);
312 tcg_gen_trunc_i64_i32(d, t0);
313 tcg_gen_shri_i64(t0, t0, 32);
314 tcg_gen_trunc_i64_i32(d2, t0);
320 /* 32bit branch-free binary search for counting leading zeros. */
321 static void t_gen_lz_i32(TCGv d, TCGv x)
325 y = tcg_temp_new(TCG_TYPE_I32);
326 m = tcg_temp_new(TCG_TYPE_I32);
327 n = tcg_temp_new(TCG_TYPE_I32);
330 tcg_gen_shri_i32(y, x, 16);
331 tcg_gen_neg_i32(y, y);
333 /* m = (y >> 16) & 16 */
334 tcg_gen_sari_i32(m, y, 16);
335 tcg_gen_andi_i32(m, m, 16);
338 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
340 tcg_gen_shr_i32(x, x, m);
343 tcg_gen_subi_i32(y, x, 0x100);
344 /* m = (y >> 16) & 8 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 8);
348 tcg_gen_add_i32(n, n, m);
350 tcg_gen_shl_i32(x, x, m);
353 tcg_gen_subi_i32(y, x, 0x1000);
354 /* m = (y >> 16) & 4 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 4);
358 tcg_gen_add_i32(n, n, m);
360 tcg_gen_shl_i32(x, x, m);
363 tcg_gen_subi_i32(y, x, 0x4000);
364 /* m = (y >> 16) & 2 */
365 tcg_gen_sari_i32(m, y, 16);
366 tcg_gen_andi_i32(m, m, 2);
368 tcg_gen_add_i32(n, n, m);
370 tcg_gen_shl_i32(x, x, m);
373 tcg_gen_shri_i32(y, x, 14);
374 /* m = y & ~(y >> 1) */
375 tcg_gen_sari_i32(m, y, 1);
376 tcg_gen_not_i32(m, m);
377 tcg_gen_and_i32(m, m, y);
380 tcg_gen_addi_i32(d, n, 2);
381 tcg_gen_sub_i32(d, d, m);
388 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
396 The N flag is set according to the selected bit in the dest reg.
397 The Z flag is set if the selected bit and all bits to the right are
399 The X flag is cleared.
400 Other flags are left untouched.
401 The destination reg is not affected.
403 unsigned int fz, sbit, bset, mask, masked_t0;
406 bset = !!(T0 & (1 << sbit));
407 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
408 masked_t0 = T0 & mask;
409 fz = !(masked_t0 | bset);
411 // Clear the X, N and Z flags.
412 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
413 // Set the N and Z flags accordingly.
414 T0 |= (bset << 3) | (fz << 2);
417 l1 = gen_new_label();
418 sbit = tcg_temp_new(TCG_TYPE_TL);
419 bset = tcg_temp_new(TCG_TYPE_TL);
420 t0 = tcg_temp_new(TCG_TYPE_TL);
422 /* Compute bset and sbit. */
423 tcg_gen_andi_tl(sbit, b, 31);
424 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
425 tcg_gen_and_tl(bset, a, t0);
426 tcg_gen_shr_tl(bset, bset, sbit);
427 /* Displace to N_FLAG. */
428 tcg_gen_shli_tl(bset, bset, 3);
430 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
431 tcg_gen_subi_tl(sbit, sbit, 1);
432 tcg_gen_and_tl(sbit, a, sbit);
434 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
435 /* or in the N_FLAG. */
436 tcg_gen_or_tl(d, d, bset);
437 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
438 /* or in the Z_FLAG. */
439 tcg_gen_ori_tl(d, d, Z_FLAG);
446 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
450 l1 = gen_new_label();
457 tcg_gen_shli_tl(d, a, 1);
458 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
459 tcg_gen_sub_tl(d, d, b);
463 /* Extended arithmetics on CRIS. */
464 static inline void t_gen_add_flag(TCGv d, int flag)
468 c = tcg_temp_new(TCG_TYPE_TL);
469 t_gen_mov_TN_preg(c, PR_CCS);
470 /* Propagate carry into d. */
471 tcg_gen_andi_tl(c, c, 1 << flag);
473 tcg_gen_shri_tl(c, c, flag);
474 tcg_gen_add_tl(d, d, c);
478 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
480 if (dc->flagx_known) {
484 c = tcg_temp_new(TCG_TYPE_TL);
485 t_gen_mov_TN_preg(c, PR_CCS);
486 /* C flag is already at bit 0. */
487 tcg_gen_andi_tl(c, c, C_FLAG);
488 tcg_gen_add_tl(d, d, c);
494 x = tcg_temp_new(TCG_TYPE_TL);
495 c = tcg_temp_new(TCG_TYPE_TL);
496 t_gen_mov_TN_preg(x, PR_CCS);
497 tcg_gen_mov_tl(c, x);
499 /* Propagate carry into d if X is set. Branch free. */
500 tcg_gen_andi_tl(c, c, C_FLAG);
501 tcg_gen_andi_tl(x, x, X_FLAG);
502 tcg_gen_shri_tl(x, x, 4);
504 tcg_gen_and_tl(x, x, c);
505 tcg_gen_add_tl(d, d, x);
511 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
513 if (dc->flagx_known) {
517 c = tcg_temp_new(TCG_TYPE_TL);
518 t_gen_mov_TN_preg(c, PR_CCS);
519 /* C flag is already at bit 0. */
520 tcg_gen_andi_tl(c, c, C_FLAG);
521 tcg_gen_sub_tl(d, d, c);
527 x = tcg_temp_new(TCG_TYPE_TL);
528 c = tcg_temp_new(TCG_TYPE_TL);
529 t_gen_mov_TN_preg(x, PR_CCS);
530 tcg_gen_mov_tl(c, x);
532 /* Propagate carry into d if X is set. Branch free. */
533 tcg_gen_andi_tl(c, c, C_FLAG);
534 tcg_gen_andi_tl(x, x, X_FLAG);
535 tcg_gen_shri_tl(x, x, 4);
537 tcg_gen_and_tl(x, x, c);
538 tcg_gen_sub_tl(d, d, x);
544 /* Swap the two bytes within each half word of the s operand.
545 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
546 static inline void t_gen_swapb(TCGv d, TCGv s)
550 t = tcg_temp_new(TCG_TYPE_TL);
551 org_s = tcg_temp_new(TCG_TYPE_TL);
553 /* d and s may refer to the same object. */
554 tcg_gen_mov_tl(org_s, s);
555 tcg_gen_shli_tl(t, org_s, 8);
556 tcg_gen_andi_tl(d, t, 0xff00ff00);
557 tcg_gen_shri_tl(t, org_s, 8);
558 tcg_gen_andi_tl(t, t, 0x00ff00ff);
559 tcg_gen_or_tl(d, d, t);
561 tcg_temp_free(org_s);
564 /* Swap the halfwords of the s operand. */
565 static inline void t_gen_swapw(TCGv d, TCGv s)
568 /* d and s refer the same object. */
569 t = tcg_temp_new(TCG_TYPE_TL);
570 tcg_gen_mov_tl(t, s);
571 tcg_gen_shli_tl(d, t, 16);
572 tcg_gen_shri_tl(t, t, 16);
573 tcg_gen_or_tl(d, d, t);
577 /* Reverse the within each byte.
578 T0 = (((T0 << 7) & 0x80808080) |
579 ((T0 << 5) & 0x40404040) |
580 ((T0 << 3) & 0x20202020) |
581 ((T0 << 1) & 0x10101010) |
582 ((T0 >> 1) & 0x08080808) |
583 ((T0 >> 3) & 0x04040404) |
584 ((T0 >> 5) & 0x02020202) |
585 ((T0 >> 7) & 0x01010101));
587 static inline void t_gen_swapr(TCGv d, TCGv s)
590 int shift; /* LSL when positive, LSR when negative. */
605 /* d and s refer the same object. */
606 t = tcg_temp_new(TCG_TYPE_TL);
607 org_s = tcg_temp_new(TCG_TYPE_TL);
608 tcg_gen_mov_tl(org_s, s);
610 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
611 tcg_gen_andi_tl(d, t, bitrev[0].mask);
612 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
613 if (bitrev[i].shift >= 0) {
614 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
616 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
618 tcg_gen_andi_tl(t, t, bitrev[i].mask);
619 tcg_gen_or_tl(d, d, t);
622 tcg_temp_free(org_s);
625 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
630 l1 = gen_new_label();
631 btaken = tcg_temp_new(TCG_TYPE_TL);
633 /* Conditional jmp. */
634 tcg_gen_mov_tl(btaken, env_btaken);
635 tcg_gen_mov_tl(env_pc, pc_false);
636 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
637 tcg_gen_mov_tl(env_pc, pc_true);
640 tcg_temp_free(btaken);
643 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
645 TranslationBlock *tb;
647 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
649 tcg_gen_movi_tl(env_pc, dest);
650 tcg_gen_exit_tb((long)tb + n);
652 tcg_gen_movi_tl(env_pc, dest);
657 /* Sign extend at translation time. */
658 static int sign_extend(unsigned int val, unsigned int width)
670 static inline void cris_clear_x_flag(DisasContext *dc)
672 if (dc->flagx_known && dc->flags_x)
673 dc->flags_uptodate = 0;
679 static void cris_flush_cc_state(DisasContext *dc)
681 if (dc->cc_size_uptodate != dc->cc_size) {
682 tcg_gen_movi_tl(cc_size, dc->cc_size);
683 dc->cc_size_uptodate = dc->cc_size;
685 tcg_gen_movi_tl(cc_op, dc->cc_op);
686 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
689 static void cris_evaluate_flags(DisasContext *dc)
691 if (!dc->flags_uptodate) {
692 cris_flush_cc_state(dc);
697 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
700 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
703 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
715 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
718 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
721 tcg_gen_helper_0_0(helper_evaluate_flags);
733 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
736 tcg_gen_helper_0_0(helper_evaluate_flags);
742 if (dc->flagx_known) {
744 tcg_gen_ori_tl(cpu_PR[PR_CCS],
745 cpu_PR[PR_CCS], X_FLAG);
747 tcg_gen_andi_tl(cpu_PR[PR_CCS],
748 cpu_PR[PR_CCS], ~X_FLAG);
751 dc->flags_uptodate = 1;
755 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
764 /* Check if we need to evaluate the condition codes due to
766 ovl = (dc->cc_mask ^ mask) & ~mask;
768 /* TODO: optimize this case. It trigs all the time. */
769 cris_evaluate_flags (dc);
775 static void cris_update_cc_op(DisasContext *dc, int op, int size)
779 dc->flags_uptodate = 0;
782 static inline void cris_update_cc_x(DisasContext *dc)
784 /* Save the x flag state at the time of the cc snapshot. */
785 if (dc->flagx_known) {
786 if (dc->cc_x_uptodate == (2 | dc->flags_x))
788 tcg_gen_movi_tl(cc_x, dc->flags_x);
789 dc->cc_x_uptodate = 2 | dc->flags_x;
792 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
793 dc->cc_x_uptodate = 1;
797 /* Update cc prior to executing ALU op. Needs source operands untouched. */
798 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
799 TCGv dst, TCGv src, int size)
802 cris_update_cc_op(dc, op, size);
803 tcg_gen_mov_tl(cc_src, src);
812 tcg_gen_mov_tl(cc_dest, dst);
814 cris_update_cc_x(dc);
818 /* Update cc after executing ALU op. needs the result. */
819 static inline void cris_update_result(DisasContext *dc, TCGv res)
822 if (dc->cc_size == 4 &&
823 (dc->cc_op == CC_OP_SUB
824 || dc->cc_op == CC_OP_ADD))
826 tcg_gen_mov_tl(cc_result, res);
830 /* Returns one if the write back stage should execute. */
831 static void cris_alu_op_exec(DisasContext *dc, int op,
832 TCGv dst, TCGv a, TCGv b, int size)
834 /* Emit the ALU insns. */
838 tcg_gen_add_tl(dst, a, b);
839 /* Extended arithmetics. */
840 t_gen_addx_carry(dc, dst);
843 tcg_gen_add_tl(dst, a, b);
844 t_gen_add_flag(dst, 0); /* C_FLAG. */
847 tcg_gen_add_tl(dst, a, b);
848 t_gen_add_flag(dst, 8); /* R_FLAG. */
851 tcg_gen_sub_tl(dst, a, b);
852 /* Extended arithmetics. */
853 t_gen_subx_carry(dc, dst);
856 tcg_gen_mov_tl(dst, b);
859 tcg_gen_or_tl(dst, a, b);
862 tcg_gen_and_tl(dst, a, b);
865 tcg_gen_xor_tl(dst, a, b);
868 t_gen_lsl(dst, a, b);
871 t_gen_lsr(dst, a, b);
874 t_gen_asr(dst, a, b);
877 tcg_gen_neg_tl(dst, b);
878 /* Extended arithmetics. */
879 t_gen_subx_carry(dc, dst);
882 t_gen_lz_i32(dst, b);
885 t_gen_btst(dst, a, b);
888 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
891 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
894 t_gen_cris_dstep(dst, a, b);
899 l1 = gen_new_label();
900 tcg_gen_mov_tl(dst, a);
901 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
902 tcg_gen_mov_tl(dst, b);
907 tcg_gen_sub_tl(dst, a, b);
908 /* Extended arithmetics. */
909 t_gen_subx_carry(dc, dst);
912 fprintf (logfile, "illegal ALU op.\n");
918 tcg_gen_andi_tl(dst, dst, 0xff);
920 tcg_gen_andi_tl(dst, dst, 0xffff);
923 static void cris_alu(DisasContext *dc, int op,
924 TCGv d, TCGv op_a, TCGv op_b, int size)
933 else if (size == 4) {
938 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
939 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
940 cris_update_result(dc, tmp);
945 tcg_gen_andi_tl(d, d, ~0xff);
947 tcg_gen_andi_tl(d, d, ~0xffff);
948 tcg_gen_or_tl(d, d, tmp);
952 static int arith_cc(DisasContext *dc)
956 case CC_OP_ADDC: return 1;
957 case CC_OP_ADD: return 1;
958 case CC_OP_SUB: return 1;
959 case CC_OP_DSTEP: return 1;
960 case CC_OP_LSL: return 1;
961 case CC_OP_LSR: return 1;
962 case CC_OP_ASR: return 1;
963 case CC_OP_CMP: return 1;
964 case CC_OP_NEG: return 1;
965 case CC_OP_OR: return 1;
966 case CC_OP_XOR: return 1;
967 case CC_OP_MULU: return 1;
968 case CC_OP_MULS: return 1;
976 static void gen_tst_cc (DisasContext *dc, int cond)
978 int arith_opt, move_opt;
980 /* TODO: optimize more condition codes. */
983 * If the flags are live, we've gotta look into the bits of CCS.
984 * Otherwise, if we just did an arithmetic operation we try to
985 * evaluate the condition code faster.
987 * When this function is done, T0 should be non-zero if the condition
990 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
991 move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
994 if (arith_opt || move_opt) {
995 /* If cc_result is zero, T0 should be
996 non-zero otherwise T0 should be zero. */
998 l1 = gen_new_label();
999 tcg_gen_movi_tl(cpu_T[0], 0);
1000 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
1002 tcg_gen_movi_tl(cpu_T[0], 1);
1006 cris_evaluate_flags(dc);
1007 tcg_gen_andi_tl(cpu_T[0],
1008 cpu_PR[PR_CCS], Z_FLAG);
1012 if (arith_opt || move_opt)
1013 tcg_gen_mov_tl(cpu_T[0], cc_result);
1015 cris_evaluate_flags(dc);
1016 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1018 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1022 cris_evaluate_flags(dc);
1023 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1026 cris_evaluate_flags(dc);
1027 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1028 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
1031 cris_evaluate_flags(dc);
1032 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
1035 cris_evaluate_flags(dc);
1036 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1038 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
1041 if (arith_opt || move_opt) {
1044 if (dc->cc_size == 1)
1046 else if (dc->cc_size == 2)
1049 tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
1050 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1052 cris_evaluate_flags(dc);
1053 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1055 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1059 if (arith_opt || move_opt) {
1062 if (dc->cc_size == 1)
1064 else if (dc->cc_size == 2)
1067 tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
1070 cris_evaluate_flags(dc);
1071 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1076 cris_evaluate_flags(dc);
1077 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1081 cris_evaluate_flags(dc);
1085 tmp = tcg_temp_new(TCG_TYPE_TL);
1086 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1088 /* Overlay the C flag on top of the Z. */
1089 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
1090 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
1091 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1097 cris_evaluate_flags(dc);
1098 /* Overlay the V flag on top of the N. */
1099 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1100 tcg_gen_xor_tl(cpu_T[0],
1101 cpu_PR[PR_CCS], cpu_T[0]);
1102 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1103 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
1106 cris_evaluate_flags(dc);
1107 /* Overlay the V flag on top of the N. */
1108 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1109 tcg_gen_xor_tl(cpu_T[0],
1110 cpu_PR[PR_CCS], cpu_T[0]);
1111 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1114 cris_evaluate_flags(dc);
1118 n = tcg_temp_new(TCG_TYPE_TL);
1119 z = tcg_temp_new(TCG_TYPE_TL);
1121 /* To avoid a shift we overlay everything on
1123 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1124 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1126 tcg_gen_xori_tl(z, z, 2);
1128 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1129 tcg_gen_xori_tl(n, n, 2);
1130 tcg_gen_and_tl(cpu_T[0], z, n);
1131 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1138 cris_evaluate_flags(dc);
1142 n = tcg_temp_new(TCG_TYPE_TL);
1143 z = tcg_temp_new(TCG_TYPE_TL);
1145 /* To avoid a shift we overlay everything on
1147 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1148 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1150 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1151 tcg_gen_or_tl(cpu_T[0], z, n);
1152 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1159 cris_evaluate_flags(dc);
1160 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
1163 tcg_gen_movi_tl(cpu_T[0], 1);
1171 static void cris_store_direct_jmp(DisasContext *dc)
1173 /* Store the direct jmp state into the cpu-state. */
1174 if (dc->jmp == JMP_DIRECT) {
1175 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1176 tcg_gen_movi_tl(env_btaken, 1);
1180 static void cris_prepare_cc_branch (DisasContext *dc,
1181 int offset, int cond)
1183 /* This helps us re-schedule the micro-code to insns in delay-slots
1184 before the actual jump. */
1185 dc->delayed_branch = 2;
1186 dc->jmp_pc = dc->pc + offset;
1190 dc->jmp = JMP_INDIRECT;
1191 gen_tst_cc (dc, cond);
1192 tcg_gen_mov_tl(env_btaken, cpu_T[0]);
1193 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1195 /* Allow chaining. */
1196 dc->jmp = JMP_DIRECT;
1201 /* jumps, when the dest is in a live reg for example. Direct should be set
1202 when the dest addr is constant to allow tb chaining. */
1203 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1205 /* This helps us re-schedule the micro-code to insns in delay-slots
1206 before the actual jump. */
1207 dc->delayed_branch = 2;
1209 if (type == JMP_INDIRECT)
1210 tcg_gen_movi_tl(env_btaken, 1);
1213 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1214 unsigned int size, int sign)
1216 int mem_index = cpu_mmu_index(dc->env);
1218 /* If we get a fault on a delayslot we must keep the jmp state in
1219 the cpu-state to be able to re-execute the jmp. */
1220 if (dc->delayed_branch == 1)
1221 cris_store_direct_jmp(dc);
1225 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1227 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1229 else if (size == 2) {
1231 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1233 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1235 else if (size == 4) {
1236 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1238 else if (size == 8) {
1239 tcg_gen_qemu_ld64(dst, addr, mem_index);
1243 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1246 int mem_index = cpu_mmu_index(dc->env);
1248 /* If we get a fault on a delayslot we must keep the jmp state in
1249 the cpu-state to be able to re-execute the jmp. */
1250 if (dc->delayed_branch == 1)
1251 cris_store_direct_jmp(dc);
1254 /* Conditional writes. We only support the kind were X and P are known
1255 at translation time. */
1256 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1258 cris_evaluate_flags(dc);
1259 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1264 tcg_gen_qemu_st8(val, addr, mem_index);
1266 tcg_gen_qemu_st16(val, addr, mem_index);
1268 tcg_gen_qemu_st32(val, addr, mem_index);
1270 if (dc->flagx_known && dc->flags_x) {
1271 cris_evaluate_flags(dc);
1272 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1276 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1279 tcg_gen_ext8s_i32(d, s);
1281 tcg_gen_ext16s_i32(d, s);
1282 else if(GET_TCGV(d) != GET_TCGV(s))
1283 tcg_gen_mov_tl(d, s);
1286 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1289 tcg_gen_ext8u_i32(d, s);
1291 tcg_gen_ext16u_i32(d, s);
1292 else if (GET_TCGV(d) != GET_TCGV(s))
1293 tcg_gen_mov_tl(d, s);
1297 static char memsize_char(int size)
1301 case 1: return 'b'; break;
1302 case 2: return 'w'; break;
1303 case 4: return 'd'; break;
1311 static inline unsigned int memsize_z(DisasContext *dc)
1313 return dc->zsize + 1;
1316 static inline unsigned int memsize_zz(DisasContext *dc)
1327 static inline void do_postinc (DisasContext *dc, int size)
1330 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1333 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1334 int size, int s_ext, TCGv dst)
1337 t_gen_sext(dst, cpu_R[rs], size);
1339 t_gen_zext(dst, cpu_R[rs], size);
1342 /* Prepare T0 and T1 for a register alu operation.
1343 s_ext decides if the operand1 should be sign-extended or zero-extended when
1345 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1346 int size, int s_ext)
1348 dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
1351 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1353 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1356 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1359 unsigned int rs, rd;
1366 is_imm = rs == 15 && dc->postinc;
1368 /* Load [$rs] onto T1. */
1370 insn_len = 2 + memsize;
1377 imm = ldsb_code(dc->pc + 2);
1379 imm = ldsw_code(dc->pc + 2);
1382 imm = ldub_code(dc->pc + 2);
1384 imm = lduw_code(dc->pc + 2);
1387 imm = ldl_code(dc->pc + 2);
1389 tcg_gen_movi_tl(dst, imm);
1392 cris_flush_cc_state(dc);
1393 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1395 t_gen_sext(dst, dst, memsize);
1397 t_gen_zext(dst, dst, memsize);
1402 /* Prepare T0 and T1 for a memory + alu operation.
1403 s_ext decides if the operand1 should be sign-extended or zero-extended when
1405 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1409 insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
1411 /* put dest in T0. */
1412 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1417 static const char *cc_name(int cc)
1419 static const char *cc_names[16] = {
1420 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1421 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1424 return cc_names[cc];
1428 /* Start of insn decoders. */
1430 static unsigned int dec_bccq(DisasContext *dc)
1434 uint32_t cond = dc->op2;
1437 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1438 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1441 offset |= sign << 8;
1443 offset = sign_extend(offset, 8);
1445 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1447 /* op2 holds the condition-code. */
1448 cris_cc_mask(dc, 0);
1449 cris_prepare_cc_branch (dc, offset, cond);
1452 static unsigned int dec_addoq(DisasContext *dc)
1456 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1457 imm = sign_extend(dc->op1, 7);
1459 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1460 cris_cc_mask(dc, 0);
1461 /* Fetch register operand, */
1462 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1465 static unsigned int dec_addq(DisasContext *dc)
1467 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1469 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1471 cris_cc_mask(dc, CC_MASK_NZVC);
1473 cris_alu(dc, CC_OP_ADD,
1474 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1477 static unsigned int dec_moveq(DisasContext *dc)
1481 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1482 imm = sign_extend(dc->op1, 5);
1483 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1485 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1488 static unsigned int dec_subq(DisasContext *dc)
1490 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1492 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1494 cris_cc_mask(dc, CC_MASK_NZVC);
1495 cris_alu(dc, CC_OP_SUB,
1496 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1499 static unsigned int dec_cmpq(DisasContext *dc)
1502 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1503 imm = sign_extend(dc->op1, 5);
1505 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1506 cris_cc_mask(dc, CC_MASK_NZVC);
1508 cris_alu(dc, CC_OP_CMP,
1509 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1512 static unsigned int dec_andq(DisasContext *dc)
1515 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1516 imm = sign_extend(dc->op1, 5);
1518 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1519 cris_cc_mask(dc, CC_MASK_NZ);
1521 cris_alu(dc, CC_OP_AND,
1522 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1525 static unsigned int dec_orq(DisasContext *dc)
1528 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1529 imm = sign_extend(dc->op1, 5);
1530 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1531 cris_cc_mask(dc, CC_MASK_NZ);
1533 cris_alu(dc, CC_OP_OR,
1534 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1537 static unsigned int dec_btstq(DisasContext *dc)
1539 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1540 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1542 cris_cc_mask(dc, CC_MASK_NZ);
1544 cris_alu(dc, CC_OP_BTST,
1545 cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1546 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1547 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1548 dc->flags_uptodate = 1;
1551 static unsigned int dec_asrq(DisasContext *dc)
1553 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1554 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1555 cris_cc_mask(dc, CC_MASK_NZ);
1557 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1558 cris_alu(dc, CC_OP_MOVE,
1560 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1563 static unsigned int dec_lslq(DisasContext *dc)
1565 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1566 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1568 cris_cc_mask(dc, CC_MASK_NZ);
1570 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1572 cris_alu(dc, CC_OP_MOVE,
1574 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1577 static unsigned int dec_lsrq(DisasContext *dc)
1579 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1580 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1582 cris_cc_mask(dc, CC_MASK_NZ);
1584 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1585 cris_alu(dc, CC_OP_MOVE,
1587 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1591 static unsigned int dec_move_r(DisasContext *dc)
1593 int size = memsize_zz(dc);
1595 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1596 memsize_char(size), dc->op1, dc->op2));
1598 cris_cc_mask(dc, CC_MASK_NZ);
1600 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1601 cris_cc_mask(dc, CC_MASK_NZ);
1602 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1603 cris_update_cc_x(dc);
1604 cris_update_result(dc, cpu_R[dc->op2]);
1607 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1608 cris_alu(dc, CC_OP_MOVE,
1610 cpu_R[dc->op2], cpu_T[1], size);
1615 static unsigned int dec_scc_r(DisasContext *dc)
1619 DIS(fprintf (logfile, "s%s $r%u\n",
1620 cc_name(cond), dc->op1));
1626 gen_tst_cc (dc, cond);
1628 l1 = gen_new_label();
1629 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1630 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
1631 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1635 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1637 cris_cc_mask(dc, 0);
1641 static unsigned int dec_and_r(DisasContext *dc)
1643 int size = memsize_zz(dc);
1645 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1646 memsize_char(size), dc->op1, dc->op2));
1647 cris_cc_mask(dc, CC_MASK_NZ);
1648 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1650 cris_alu(dc, CC_OP_AND,
1652 cpu_R[dc->op2], cpu_T[1], size);
1656 static unsigned int dec_lz_r(DisasContext *dc)
1658 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1660 cris_cc_mask(dc, CC_MASK_NZ);
1661 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1662 cris_alu(dc, CC_OP_LZ,
1663 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1667 static unsigned int dec_lsl_r(DisasContext *dc)
1669 int size = memsize_zz(dc);
1671 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1672 memsize_char(size), dc->op1, dc->op2));
1673 cris_cc_mask(dc, CC_MASK_NZ);
1674 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1675 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1677 cris_alu(dc, CC_OP_LSL,
1678 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1682 static unsigned int dec_lsr_r(DisasContext *dc)
1684 int size = memsize_zz(dc);
1686 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1687 memsize_char(size), dc->op1, dc->op2));
1688 cris_cc_mask(dc, CC_MASK_NZ);
1689 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1690 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1692 cris_alu(dc, CC_OP_LSR,
1693 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1697 static unsigned int dec_asr_r(DisasContext *dc)
1699 int size = memsize_zz(dc);
1701 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1702 memsize_char(size), dc->op1, dc->op2));
1703 cris_cc_mask(dc, CC_MASK_NZ);
1704 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1705 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1707 cris_alu(dc, CC_OP_ASR,
1708 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1712 static unsigned int dec_muls_r(DisasContext *dc)
1714 int size = memsize_zz(dc);
1716 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1717 memsize_char(size), dc->op1, dc->op2));
1718 cris_cc_mask(dc, CC_MASK_NZV);
1719 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1721 cris_alu(dc, CC_OP_MULS,
1722 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1726 static unsigned int dec_mulu_r(DisasContext *dc)
1728 int size = memsize_zz(dc);
1730 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1731 memsize_char(size), dc->op1, dc->op2));
1732 cris_cc_mask(dc, CC_MASK_NZV);
1733 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1735 cris_alu(dc, CC_OP_MULU,
1736 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1741 static unsigned int dec_dstep_r(DisasContext *dc)
1743 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1744 cris_cc_mask(dc, CC_MASK_NZ);
1745 cris_alu(dc, CC_OP_DSTEP,
1746 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1750 static unsigned int dec_xor_r(DisasContext *dc)
1752 int size = memsize_zz(dc);
1753 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1754 memsize_char(size), dc->op1, dc->op2));
1755 BUG_ON(size != 4); /* xor is dword. */
1756 cris_cc_mask(dc, CC_MASK_NZ);
1757 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1759 cris_alu(dc, CC_OP_XOR,
1760 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1764 static unsigned int dec_bound_r(DisasContext *dc)
1766 int size = memsize_zz(dc);
1767 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1768 memsize_char(size), dc->op1, dc->op2));
1769 cris_cc_mask(dc, CC_MASK_NZ);
1770 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1771 cris_alu(dc, CC_OP_BOUND,
1772 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1776 static unsigned int dec_cmp_r(DisasContext *dc)
1778 int size = memsize_zz(dc);
1779 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1780 memsize_char(size), dc->op1, dc->op2));
1781 cris_cc_mask(dc, CC_MASK_NZVC);
1782 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1784 cris_alu(dc, CC_OP_CMP,
1785 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1789 static unsigned int dec_abs_r(DisasContext *dc)
1793 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1795 cris_cc_mask(dc, CC_MASK_NZ);
1797 t0 = tcg_temp_new(TCG_TYPE_TL);
1798 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1799 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1800 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1803 cris_alu(dc, CC_OP_MOVE,
1804 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1808 static unsigned int dec_add_r(DisasContext *dc)
1810 int size = memsize_zz(dc);
1811 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1812 memsize_char(size), dc->op1, dc->op2));
1813 cris_cc_mask(dc, CC_MASK_NZVC);
1814 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1816 cris_alu(dc, CC_OP_ADD,
1817 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1821 static unsigned int dec_addc_r(DisasContext *dc)
1823 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1825 cris_evaluate_flags(dc);
1826 cris_cc_mask(dc, CC_MASK_NZVC);
1827 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1828 cris_alu(dc, CC_OP_ADDC,
1829 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1833 static unsigned int dec_mcp_r(DisasContext *dc)
1835 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1837 cris_evaluate_flags(dc);
1838 cris_cc_mask(dc, CC_MASK_RNZV);
1839 cris_alu(dc, CC_OP_MCP,
1840 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1845 static char * swapmode_name(int mode, char *modename) {
1848 modename[i++] = 'n';
1850 modename[i++] = 'w';
1852 modename[i++] = 'b';
1854 modename[i++] = 'r';
1860 static unsigned int dec_swap_r(DisasContext *dc)
1865 DIS(fprintf (logfile, "swap%s $r%u\n",
1866 swapmode_name(dc->op2, modename), dc->op1));
1868 cris_cc_mask(dc, CC_MASK_NZ);
1869 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1871 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
1873 t_gen_swapw(cpu_T[0], cpu_T[0]);
1875 t_gen_swapb(cpu_T[0], cpu_T[0]);
1877 t_gen_swapr(cpu_T[0], cpu_T[0]);
1878 cris_alu(dc, CC_OP_MOVE,
1879 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
1884 static unsigned int dec_or_r(DisasContext *dc)
1886 int size = memsize_zz(dc);
1887 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1888 memsize_char(size), dc->op1, dc->op2));
1889 cris_cc_mask(dc, CC_MASK_NZ);
1890 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1892 cris_alu(dc, CC_OP_OR,
1893 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1897 static unsigned int dec_addi_r(DisasContext *dc)
1899 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1900 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1901 cris_cc_mask(dc, 0);
1902 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1903 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
1907 static unsigned int dec_addi_acr(DisasContext *dc)
1909 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1910 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1911 cris_cc_mask(dc, 0);
1912 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1913 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
1917 static unsigned int dec_neg_r(DisasContext *dc)
1919 int size = memsize_zz(dc);
1920 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1921 memsize_char(size), dc->op1, dc->op2));
1922 cris_cc_mask(dc, CC_MASK_NZVC);
1923 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1925 cris_alu(dc, CC_OP_NEG,
1926 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1930 static unsigned int dec_btst_r(DisasContext *dc)
1932 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1934 cris_cc_mask(dc, CC_MASK_NZ);
1935 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1937 cris_alu(dc, CC_OP_BTST,
1938 cpu_T[0], cpu_T[0], cpu_T[1], 4);
1939 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1940 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1941 dc->flags_uptodate = 1;
1945 static unsigned int dec_sub_r(DisasContext *dc)
1947 int size = memsize_zz(dc);
1948 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1949 memsize_char(size), dc->op1, dc->op2));
1950 cris_cc_mask(dc, CC_MASK_NZVC);
1951 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1952 cris_alu(dc, CC_OP_SUB,
1953 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1957 /* Zero extension. From size to dword. */
1958 static unsigned int dec_movu_r(DisasContext *dc)
1960 int size = memsize_z(dc);
1961 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1965 cris_cc_mask(dc, CC_MASK_NZ);
1966 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1967 cris_alu(dc, CC_OP_MOVE,
1968 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1972 /* Sign extension. From size to dword. */
1973 static unsigned int dec_movs_r(DisasContext *dc)
1975 int size = memsize_z(dc);
1976 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1980 cris_cc_mask(dc, CC_MASK_NZ);
1981 /* Size can only be qi or hi. */
1982 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
1983 cris_alu(dc, CC_OP_MOVE,
1984 cpu_R[dc->op2], cpu_R[dc->op1], cpu_T[1], 4);
1988 /* zero extension. From size to dword. */
1989 static unsigned int dec_addu_r(DisasContext *dc)
1991 int size = memsize_z(dc);
1992 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1996 cris_cc_mask(dc, CC_MASK_NZVC);
1997 /* Size can only be qi or hi. */
1998 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
1999 cris_alu(dc, CC_OP_ADD,
2000 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2004 /* Sign extension. From size to dword. */
2005 static unsigned int dec_adds_r(DisasContext *dc)
2007 int size = memsize_z(dc);
2008 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2012 cris_cc_mask(dc, CC_MASK_NZVC);
2013 /* Size can only be qi or hi. */
2014 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2015 cris_alu(dc, CC_OP_ADD,
2016 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2020 /* Zero extension. From size to dword. */
2021 static unsigned int dec_subu_r(DisasContext *dc)
2023 int size = memsize_z(dc);
2024 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2028 cris_cc_mask(dc, CC_MASK_NZVC);
2029 /* Size can only be qi or hi. */
2030 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
2031 cris_alu(dc, CC_OP_SUB,
2032 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2036 /* Sign extension. From size to dword. */
2037 static unsigned int dec_subs_r(DisasContext *dc)
2039 int size = memsize_z(dc);
2040 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2044 cris_cc_mask(dc, CC_MASK_NZVC);
2045 /* Size can only be qi or hi. */
2046 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2047 cris_alu(dc, CC_OP_SUB,
2048 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2052 static unsigned int dec_setclrf(DisasContext *dc)
2055 int set = (~dc->opcode >> 2) & 1;
2057 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2058 | EXTRACT_FIELD(dc->ir, 0, 3);
2059 if (set && flags == 0) {
2060 DIS(fprintf (logfile, "nop\n"));
2062 } else if (!set && (flags & 0x20)) {
2063 DIS(fprintf (logfile, "di\n"));
2066 DIS(fprintf (logfile, "%sf %x\n",
2067 set ? "set" : "clr",
2071 /* User space is not allowed to touch these. Silently ignore. */
2072 if (dc->tb_flags & U_FLAG) {
2073 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2076 if (flags & X_FLAG) {
2077 dc->flagx_known = 1;
2079 dc->flags_x = X_FLAG;
2084 /* Break the TB if the P flag changes. */
2085 if (flags & P_FLAG) {
2086 if ((set && !(dc->tb_flags & P_FLAG))
2087 || (!set && (dc->tb_flags & P_FLAG))) {
2088 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2089 dc->is_jmp = DISAS_UPDATE;
2090 dc->cpustate_changed = 1;
2093 if (flags & S_FLAG) {
2094 dc->cpustate_changed = 1;
2098 /* Simply decode the flags. */
2099 cris_evaluate_flags (dc);
2100 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2101 cris_update_cc_x(dc);
2102 tcg_gen_movi_tl(cc_op, dc->cc_op);
2105 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2106 /* Enter user mode. */
2107 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2108 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2109 dc->cpustate_changed = 1;
2111 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2114 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2116 dc->flags_uptodate = 1;
2121 static unsigned int dec_move_rs(DisasContext *dc)
2123 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2124 cris_cc_mask(dc, 0);
2125 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2126 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2129 static unsigned int dec_move_sr(DisasContext *dc)
2131 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2132 cris_cc_mask(dc, 0);
2133 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2134 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2138 static unsigned int dec_move_rp(DisasContext *dc)
2140 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2141 cris_cc_mask(dc, 0);
2143 if (dc->op2 == PR_CCS) {
2144 cris_evaluate_flags(dc);
2145 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2146 if (dc->tb_flags & U_FLAG) {
2147 /* User space is not allowed to touch all flags. */
2148 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
2149 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
2150 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
2154 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2156 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
2157 if (dc->op2 == PR_CCS) {
2158 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2159 dc->flags_uptodate = 1;
2163 static unsigned int dec_move_pr(DisasContext *dc)
2165 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2166 cris_cc_mask(dc, 0);
2168 if (dc->op2 == PR_CCS)
2169 cris_evaluate_flags(dc);
2171 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2172 cris_alu(dc, CC_OP_MOVE,
2173 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
2174 preg_sizes[dc->op2]);
2178 static unsigned int dec_move_mr(DisasContext *dc)
2180 int memsize = memsize_zz(dc);
2182 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2183 memsize_char(memsize),
2184 dc->op1, dc->postinc ? "+]" : "]",
2188 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2189 cris_cc_mask(dc, CC_MASK_NZ);
2190 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2191 cris_update_cc_x(dc);
2192 cris_update_result(dc, cpu_R[dc->op2]);
2195 insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
2196 cris_cc_mask(dc, CC_MASK_NZ);
2197 cris_alu(dc, CC_OP_MOVE,
2198 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
2200 do_postinc(dc, memsize);
2204 static unsigned int dec_movs_m(DisasContext *dc)
2206 int memsize = memsize_z(dc);
2208 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2209 memsize_char(memsize),
2210 dc->op1, dc->postinc ? "+]" : "]",
2214 insn_len = dec_prep_alu_m(dc, 1, memsize);
2215 cris_cc_mask(dc, CC_MASK_NZ);
2216 cris_alu(dc, CC_OP_MOVE,
2217 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2218 do_postinc(dc, memsize);
2222 static unsigned int dec_addu_m(DisasContext *dc)
2224 int memsize = memsize_z(dc);
2226 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2227 memsize_char(memsize),
2228 dc->op1, dc->postinc ? "+]" : "]",
2232 insn_len = dec_prep_alu_m(dc, 0, memsize);
2233 cris_cc_mask(dc, CC_MASK_NZVC);
2234 cris_alu(dc, CC_OP_ADD,
2235 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2236 do_postinc(dc, memsize);
2240 static unsigned int dec_adds_m(DisasContext *dc)
2242 int memsize = memsize_z(dc);
2244 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2245 memsize_char(memsize),
2246 dc->op1, dc->postinc ? "+]" : "]",
2250 insn_len = dec_prep_alu_m(dc, 1, memsize);
2251 cris_cc_mask(dc, CC_MASK_NZVC);
2252 cris_alu(dc, CC_OP_ADD,
2253 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2254 do_postinc(dc, memsize);
2258 static unsigned int dec_subu_m(DisasContext *dc)
2260 int memsize = memsize_z(dc);
2262 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2263 memsize_char(memsize),
2264 dc->op1, dc->postinc ? "+]" : "]",
2268 insn_len = dec_prep_alu_m(dc, 0, memsize);
2269 cris_cc_mask(dc, CC_MASK_NZVC);
2270 cris_alu(dc, CC_OP_SUB,
2271 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2272 do_postinc(dc, memsize);
2276 static unsigned int dec_subs_m(DisasContext *dc)
2278 int memsize = memsize_z(dc);
2280 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2281 memsize_char(memsize),
2282 dc->op1, dc->postinc ? "+]" : "]",
2286 insn_len = dec_prep_alu_m(dc, 1, memsize);
2287 cris_cc_mask(dc, CC_MASK_NZVC);
2288 cris_alu(dc, CC_OP_SUB,
2289 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2290 do_postinc(dc, memsize);
2294 static unsigned int dec_movu_m(DisasContext *dc)
2296 int memsize = memsize_z(dc);
2299 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2300 memsize_char(memsize),
2301 dc->op1, dc->postinc ? "+]" : "]",
2304 insn_len = dec_prep_alu_m(dc, 0, memsize);
2305 cris_cc_mask(dc, CC_MASK_NZ);
2306 cris_alu(dc, CC_OP_MOVE,
2307 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2308 do_postinc(dc, memsize);
2312 static unsigned int dec_cmpu_m(DisasContext *dc)
2314 int memsize = memsize_z(dc);
2316 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2317 memsize_char(memsize),
2318 dc->op1, dc->postinc ? "+]" : "]",
2321 insn_len = dec_prep_alu_m(dc, 0, memsize);
2322 cris_cc_mask(dc, CC_MASK_NZVC);
2323 cris_alu(dc, CC_OP_CMP,
2324 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2325 do_postinc(dc, memsize);
2329 static unsigned int dec_cmps_m(DisasContext *dc)
2331 int memsize = memsize_z(dc);
2333 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2334 memsize_char(memsize),
2335 dc->op1, dc->postinc ? "+]" : "]",
2338 insn_len = dec_prep_alu_m(dc, 1, memsize);
2339 cris_cc_mask(dc, CC_MASK_NZVC);
2340 cris_alu(dc, CC_OP_CMP,
2341 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2343 do_postinc(dc, memsize);
2347 static unsigned int dec_cmp_m(DisasContext *dc)
2349 int memsize = memsize_zz(dc);
2351 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2352 memsize_char(memsize),
2353 dc->op1, dc->postinc ? "+]" : "]",
2356 insn_len = dec_prep_alu_m(dc, 0, memsize);
2357 cris_cc_mask(dc, CC_MASK_NZVC);
2358 cris_alu(dc, CC_OP_CMP,
2359 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2361 do_postinc(dc, memsize);
2365 static unsigned int dec_test_m(DisasContext *dc)
2367 int memsize = memsize_zz(dc);
2369 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2370 memsize_char(memsize),
2371 dc->op1, dc->postinc ? "+]" : "]",
2374 cris_evaluate_flags(dc);
2376 insn_len = dec_prep_alu_m(dc, 0, memsize);
2377 cris_cc_mask(dc, CC_MASK_NZ);
2378 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2380 cris_alu(dc, CC_OP_CMP,
2381 cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
2383 do_postinc(dc, memsize);
2387 static unsigned int dec_and_m(DisasContext *dc)
2389 int memsize = memsize_zz(dc);
2391 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2392 memsize_char(memsize),
2393 dc->op1, dc->postinc ? "+]" : "]",
2396 insn_len = dec_prep_alu_m(dc, 0, memsize);
2397 cris_cc_mask(dc, CC_MASK_NZ);
2398 cris_alu(dc, CC_OP_AND,
2399 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2401 do_postinc(dc, memsize);
2405 static unsigned int dec_add_m(DisasContext *dc)
2407 int memsize = memsize_zz(dc);
2409 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2410 memsize_char(memsize),
2411 dc->op1, dc->postinc ? "+]" : "]",
2414 insn_len = dec_prep_alu_m(dc, 0, memsize);
2415 cris_cc_mask(dc, CC_MASK_NZVC);
2416 cris_alu(dc, CC_OP_ADD,
2417 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2419 do_postinc(dc, memsize);
2423 static unsigned int dec_addo_m(DisasContext *dc)
2425 int memsize = memsize_zz(dc);
2427 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2428 memsize_char(memsize),
2429 dc->op1, dc->postinc ? "+]" : "]",
2432 insn_len = dec_prep_alu_m(dc, 1, memsize);
2433 cris_cc_mask(dc, 0);
2434 cris_alu(dc, CC_OP_ADD,
2435 cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
2436 do_postinc(dc, memsize);
2440 static unsigned int dec_bound_m(DisasContext *dc)
2442 int memsize = memsize_zz(dc);
2444 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2445 memsize_char(memsize),
2446 dc->op1, dc->postinc ? "+]" : "]",
2449 insn_len = dec_prep_alu_m(dc, 0, memsize);
2450 cris_cc_mask(dc, CC_MASK_NZ);
2451 cris_alu(dc, CC_OP_BOUND,
2452 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2453 do_postinc(dc, memsize);
2457 static unsigned int dec_addc_mr(DisasContext *dc)
2460 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2461 dc->op1, dc->postinc ? "+]" : "]",
2464 cris_evaluate_flags(dc);
2465 insn_len = dec_prep_alu_m(dc, 0, 4);
2466 cris_cc_mask(dc, CC_MASK_NZVC);
2467 cris_alu(dc, CC_OP_ADDC,
2468 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2473 static unsigned int dec_sub_m(DisasContext *dc)
2475 int memsize = memsize_zz(dc);
2477 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2478 memsize_char(memsize),
2479 dc->op1, dc->postinc ? "+]" : "]",
2480 dc->op2, dc->ir, dc->zzsize));
2482 insn_len = dec_prep_alu_m(dc, 0, memsize);
2483 cris_cc_mask(dc, CC_MASK_NZVC);
2484 cris_alu(dc, CC_OP_SUB,
2485 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
2486 do_postinc(dc, memsize);
2490 static unsigned int dec_or_m(DisasContext *dc)
2492 int memsize = memsize_zz(dc);
2494 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2495 memsize_char(memsize),
2496 dc->op1, dc->postinc ? "+]" : "]",
2499 insn_len = dec_prep_alu_m(dc, 0, memsize);
2500 cris_cc_mask(dc, CC_MASK_NZ);
2501 cris_alu(dc, CC_OP_OR,
2502 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
2503 do_postinc(dc, memsize);
2507 static unsigned int dec_move_mp(DisasContext *dc)
2509 int memsize = memsize_zz(dc);
2512 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2513 memsize_char(memsize),
2515 dc->postinc ? "+]" : "]",
2518 insn_len = dec_prep_alu_m(dc, 0, memsize);
2519 cris_cc_mask(dc, 0);
2520 if (dc->op2 == PR_CCS) {
2521 cris_evaluate_flags(dc);
2522 if (dc->tb_flags & U_FLAG) {
2523 /* User space is not allowed to touch all flags. */
2524 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2525 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2526 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2530 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
2532 do_postinc(dc, memsize);
2536 static unsigned int dec_move_pm(DisasContext *dc)
2540 memsize = preg_sizes[dc->op2];
2542 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2543 memsize_char(memsize),
2544 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2546 /* prepare store. Address in T0, value in T1. */
2547 if (dc->op2 == PR_CCS)
2548 cris_evaluate_flags(dc);
2549 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2550 cris_flush_cc_state(dc);
2551 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2553 cris_cc_mask(dc, 0);
2555 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2559 static unsigned int dec_movem_mr(DisasContext *dc)
2563 int nr = dc->op2 + 1;
2565 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2566 dc->postinc ? "+]" : "]", dc->op2));
2568 /* There are probably better ways of doing this. */
2569 cris_flush_cc_state(dc);
2570 for (i = 0; i < (nr >> 1); i++) {
2571 tmp[i] = tcg_temp_new(TCG_TYPE_I64);
2572 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2573 gen_load(dc, tmp[i], cpu_T[0], 8, 0);
2576 tmp[i] = tcg_temp_new(TCG_TYPE_I32);
2577 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2578 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2581 for (i = 0; i < (nr >> 1); i++) {
2582 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2583 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2584 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2585 tcg_temp_free(tmp[i]);
2588 tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]);
2589 tcg_temp_free(tmp[i]);
2592 /* writeback the updated pointer value. */
2594 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2596 /* gen_load might want to evaluate the previous insns flags. */
2597 cris_cc_mask(dc, 0);
2601 static unsigned int dec_movem_rm(DisasContext *dc)
2606 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2607 dc->postinc ? "+]" : "]"));
2609 cris_flush_cc_state(dc);
2611 tmp = tcg_temp_new(TCG_TYPE_TL);
2612 tcg_gen_movi_tl(tmp, 4);
2613 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
2614 for (i = 0; i <= dc->op2; i++) {
2615 /* Displace addr. */
2616 /* Perform the store. */
2617 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2618 tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
2621 tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
2622 cris_cc_mask(dc, 0);
2627 static unsigned int dec_move_rm(DisasContext *dc)
2631 memsize = memsize_zz(dc);
2633 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2634 memsize, dc->op2, dc->op1));
2636 /* prepare store. */
2637 cris_flush_cc_state(dc);
2638 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2641 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2642 cris_cc_mask(dc, 0);
2646 static unsigned int dec_lapcq(DisasContext *dc)
2648 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2649 dc->pc + dc->op1*2, dc->op2));
2650 cris_cc_mask(dc, 0);
2651 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2655 static unsigned int dec_lapc_im(DisasContext *dc)
2663 cris_cc_mask(dc, 0);
2664 imm = ldl_code(dc->pc + 2);
2665 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2669 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2673 /* Jump to special reg. */
2674 static unsigned int dec_jump_p(DisasContext *dc)
2676 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2678 if (dc->op2 == PR_CCS)
2679 cris_evaluate_flags(dc);
2680 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2681 /* rete will often have low bit set to indicate delayslot. */
2682 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2683 cris_cc_mask(dc, 0);
2684 cris_prepare_jmp(dc, JMP_INDIRECT);
2688 /* Jump and save. */
2689 static unsigned int dec_jas_r(DisasContext *dc)
2691 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2692 cris_cc_mask(dc, 0);
2693 /* Store the return address in Pd. */
2694 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2697 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2699 cris_prepare_jmp(dc, JMP_INDIRECT);
2703 static unsigned int dec_jas_im(DisasContext *dc)
2707 imm = ldl_code(dc->pc + 2);
2709 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2710 cris_cc_mask(dc, 0);
2711 /* Store the return address in Pd. */
2712 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2715 cris_prepare_jmp(dc, JMP_DIRECT);
2719 static unsigned int dec_jasc_im(DisasContext *dc)
2723 imm = ldl_code(dc->pc + 2);
2725 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2726 cris_cc_mask(dc, 0);
2727 /* Store the return address in Pd. */
2728 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2731 cris_prepare_jmp(dc, JMP_DIRECT);
2735 static unsigned int dec_jasc_r(DisasContext *dc)
2737 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2738 cris_cc_mask(dc, 0);
2739 /* Store the return address in Pd. */
2740 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2741 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2742 cris_prepare_jmp(dc, JMP_INDIRECT);
2746 static unsigned int dec_bcc_im(DisasContext *dc)
2749 uint32_t cond = dc->op2;
2751 offset = ldsw_code(dc->pc + 2);
2753 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2754 cc_name(cond), offset,
2755 dc->pc, dc->pc + offset));
2757 cris_cc_mask(dc, 0);
2758 /* op2 holds the condition-code. */
2759 cris_prepare_cc_branch (dc, offset, cond);
2763 static unsigned int dec_bas_im(DisasContext *dc)
2768 simm = ldl_code(dc->pc + 2);
2770 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2771 cris_cc_mask(dc, 0);
2772 /* Store the return address in Pd. */
2773 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2775 dc->jmp_pc = dc->pc + simm;
2776 cris_prepare_jmp(dc, JMP_DIRECT);
2780 static unsigned int dec_basc_im(DisasContext *dc)
2783 simm = ldl_code(dc->pc + 2);
2785 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2786 cris_cc_mask(dc, 0);
2787 /* Store the return address in Pd. */
2788 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2790 dc->jmp_pc = dc->pc + simm;
2791 cris_prepare_jmp(dc, JMP_DIRECT);
2795 static unsigned int dec_rfe_etc(DisasContext *dc)
2797 cris_cc_mask(dc, 0);
2799 if (dc->op2 == 15) /* ignore halt. */
2802 switch (dc->op2 & 7) {
2805 DIS(fprintf(logfile, "rfe\n"));
2806 cris_evaluate_flags(dc);
2807 tcg_gen_helper_0_0(helper_rfe);
2808 dc->is_jmp = DISAS_UPDATE;
2812 DIS(fprintf(logfile, "rfn\n"));
2813 cris_evaluate_flags(dc);
2814 tcg_gen_helper_0_0(helper_rfn);
2815 dc->is_jmp = DISAS_UPDATE;
2818 DIS(fprintf(logfile, "break %d\n", dc->op1));
2819 cris_evaluate_flags (dc);
2821 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2823 /* Breaks start at 16 in the exception vector. */
2824 t_gen_mov_env_TN(trap_vector,
2825 tcg_const_tl(dc->op1 + 16));
2826 t_gen_raise_exception(EXCP_BREAK);
2827 dc->is_jmp = DISAS_UPDATE;
2830 printf ("op2=%x\n", dc->op2);
2838 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2840 /* Ignore D-cache flushes. */
2844 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2846 /* Ignore I-cache flushes. */
2850 static unsigned int dec_null(DisasContext *dc)
2852 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2853 dc->pc, dc->opcode, dc->op1, dc->op2);
2859 static struct decoder_info {
2864 unsigned int (*dec)(DisasContext *dc);
2866 /* Order matters here. */
2867 {DEC_MOVEQ, dec_moveq},
2868 {DEC_BTSTQ, dec_btstq},
2869 {DEC_CMPQ, dec_cmpq},
2870 {DEC_ADDOQ, dec_addoq},
2871 {DEC_ADDQ, dec_addq},
2872 {DEC_SUBQ, dec_subq},
2873 {DEC_ANDQ, dec_andq},
2875 {DEC_ASRQ, dec_asrq},
2876 {DEC_LSLQ, dec_lslq},
2877 {DEC_LSRQ, dec_lsrq},
2878 {DEC_BCCQ, dec_bccq},
2880 {DEC_BCC_IM, dec_bcc_im},
2881 {DEC_JAS_IM, dec_jas_im},
2882 {DEC_JAS_R, dec_jas_r},
2883 {DEC_JASC_IM, dec_jasc_im},
2884 {DEC_JASC_R, dec_jasc_r},
2885 {DEC_BAS_IM, dec_bas_im},
2886 {DEC_BASC_IM, dec_basc_im},
2887 {DEC_JUMP_P, dec_jump_p},
2888 {DEC_LAPC_IM, dec_lapc_im},
2889 {DEC_LAPCQ, dec_lapcq},
2891 {DEC_RFE_ETC, dec_rfe_etc},
2892 {DEC_ADDC_MR, dec_addc_mr},
2894 {DEC_MOVE_MP, dec_move_mp},
2895 {DEC_MOVE_PM, dec_move_pm},
2896 {DEC_MOVEM_MR, dec_movem_mr},
2897 {DEC_MOVEM_RM, dec_movem_rm},
2898 {DEC_MOVE_PR, dec_move_pr},
2899 {DEC_SCC_R, dec_scc_r},
2900 {DEC_SETF, dec_setclrf},
2901 {DEC_CLEARF, dec_setclrf},
2903 {DEC_MOVE_SR, dec_move_sr},
2904 {DEC_MOVE_RP, dec_move_rp},
2905 {DEC_SWAP_R, dec_swap_r},
2906 {DEC_ABS_R, dec_abs_r},
2907 {DEC_LZ_R, dec_lz_r},
2908 {DEC_MOVE_RS, dec_move_rs},
2909 {DEC_BTST_R, dec_btst_r},
2910 {DEC_ADDC_R, dec_addc_r},
2912 {DEC_DSTEP_R, dec_dstep_r},
2913 {DEC_XOR_R, dec_xor_r},
2914 {DEC_MCP_R, dec_mcp_r},
2915 {DEC_CMP_R, dec_cmp_r},
2917 {DEC_ADDI_R, dec_addi_r},
2918 {DEC_ADDI_ACR, dec_addi_acr},
2920 {DEC_ADD_R, dec_add_r},
2921 {DEC_SUB_R, dec_sub_r},
2923 {DEC_ADDU_R, dec_addu_r},
2924 {DEC_ADDS_R, dec_adds_r},
2925 {DEC_SUBU_R, dec_subu_r},
2926 {DEC_SUBS_R, dec_subs_r},
2927 {DEC_LSL_R, dec_lsl_r},
2929 {DEC_AND_R, dec_and_r},
2930 {DEC_OR_R, dec_or_r},
2931 {DEC_BOUND_R, dec_bound_r},
2932 {DEC_ASR_R, dec_asr_r},
2933 {DEC_LSR_R, dec_lsr_r},
2935 {DEC_MOVU_R, dec_movu_r},
2936 {DEC_MOVS_R, dec_movs_r},
2937 {DEC_NEG_R, dec_neg_r},
2938 {DEC_MOVE_R, dec_move_r},
2940 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2941 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2943 {DEC_MULS_R, dec_muls_r},
2944 {DEC_MULU_R, dec_mulu_r},
2946 {DEC_ADDU_M, dec_addu_m},
2947 {DEC_ADDS_M, dec_adds_m},
2948 {DEC_SUBU_M, dec_subu_m},
2949 {DEC_SUBS_M, dec_subs_m},
2951 {DEC_CMPU_M, dec_cmpu_m},
2952 {DEC_CMPS_M, dec_cmps_m},
2953 {DEC_MOVU_M, dec_movu_m},
2954 {DEC_MOVS_M, dec_movs_m},
2956 {DEC_CMP_M, dec_cmp_m},
2957 {DEC_ADDO_M, dec_addo_m},
2958 {DEC_BOUND_M, dec_bound_m},
2959 {DEC_ADD_M, dec_add_m},
2960 {DEC_SUB_M, dec_sub_m},
2961 {DEC_AND_M, dec_and_m},
2962 {DEC_OR_M, dec_or_m},
2963 {DEC_MOVE_RM, dec_move_rm},
2964 {DEC_TEST_M, dec_test_m},
2965 {DEC_MOVE_MR, dec_move_mr},
2970 static inline unsigned int
2971 cris_decoder(DisasContext *dc)
2973 unsigned int insn_len = 2;
2976 if (unlikely(loglevel & CPU_LOG_TB_OP))
2977 tcg_gen_debug_insn_start(dc->pc);
2979 /* Load a halfword onto the instruction register. */
2980 dc->ir = lduw_code(dc->pc);
2982 /* Now decode it. */
2983 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2984 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2985 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2986 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2987 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2988 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2990 /* Large switch for all insns. */
2991 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2992 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2994 insn_len = decinfo[i].dec(dc);
2999 #if !defined(CONFIG_USER_ONLY)
3000 /* Single-stepping ? */
3001 if (dc->tb_flags & S_FLAG) {
3004 l1 = gen_new_label();
3005 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3006 /* We treat SPC as a break with an odd trap vector. */
3007 cris_evaluate_flags (dc);
3008 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3009 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3010 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3011 t_gen_raise_exception(EXCP_BREAK);
3018 static void check_breakpoint(CPUState *env, DisasContext *dc)
3021 if (env->nb_breakpoints > 0) {
3022 for(j = 0; j < env->nb_breakpoints; j++) {
3023 if (env->breakpoints[j] == dc->pc) {
3024 cris_evaluate_flags (dc);
3025 tcg_gen_movi_tl(env_pc, dc->pc);
3026 t_gen_raise_exception(EXCP_DEBUG);
3027 dc->is_jmp = DISAS_UPDATE;
3035 * Delay slots on QEMU/CRIS.
3037 * If an exception hits on a delayslot, the core will let ERP (the Exception
3038 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3039 * to give SW a hint that the exception actually hit on the dslot.
3041 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3042 * the core and any jmp to an odd addresses will mask off that lsb. It is
3043 * simply there to let sw know there was an exception on a dslot.
3045 * When the software returns from an exception, the branch will re-execute.
3046 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3047 * and the branch and delayslot dont share pages.
3049 * The TB contaning the branch insn will set up env->btarget and evaluate
3050 * env->btaken. When the translation loop exits we will note that the branch
3051 * sequence is broken and let env->dslot be the size of the branch insn (those
3054 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3055 * set). It will also expect to have env->dslot setup with the size of the
3056 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3057 * will execute the dslot and take the branch, either to btarget or just one
3060 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3061 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3062 * branch and set lsb). Then env->dslot gets cleared so that the exception
3063 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3064 * masked off and we will reexecute the branch insn.
3068 /* generate intermediate code for basic block 'tb'. */
3070 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3073 uint16_t *gen_opc_end;
3075 unsigned int insn_len;
3077 struct DisasContext ctx;
3078 struct DisasContext *dc = &ctx;
3079 uint32_t next_page_start;
3087 /* Odd PC indicates that branch is rexecuting due to exception in the
3088 * delayslot, like in real hw.
3090 pc_start = tb->pc & ~1;
3094 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3096 dc->is_jmp = DISAS_NEXT;
3099 dc->singlestep_enabled = env->singlestep_enabled;
3100 dc->flags_uptodate = 1;
3101 dc->flagx_known = 1;
3102 dc->flags_x = tb->flags & X_FLAG;
3103 dc->cc_x_uptodate = 0;
3107 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3108 dc->cc_size_uptodate = -1;
3110 /* Decode TB flags. */
3111 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3112 dc->delayed_branch = !!(tb->flags & 7);
3113 if (dc->delayed_branch)
3114 dc->jmp = JMP_INDIRECT;
3116 dc->jmp = JMP_NOJMP;
3118 dc->cpustate_changed = 0;
3120 if (loglevel & CPU_LOG_TB_IN_ASM) {
3122 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3128 search_pc, dc->pc, dc->ppc,
3129 (unsigned long long)tb->flags,
3130 env->btarget, (unsigned)tb->flags & 7,
3132 env->pregs[PR_PID], env->pregs[PR_USP],
3133 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3134 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3135 env->regs[8], env->regs[9],
3136 env->regs[10], env->regs[11],
3137 env->regs[12], env->regs[13],
3138 env->regs[14], env->regs[15]);
3139 fprintf(logfile, "--------------\n");
3140 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3143 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3146 max_insns = tb->cflags & CF_COUNT_MASK;
3148 max_insns = CF_COUNT_MASK;
3153 check_breakpoint(env, dc);
3156 j = gen_opc_ptr - gen_opc_buf;
3160 gen_opc_instr_start[lj++] = 0;
3162 if (dc->delayed_branch == 1)
3163 gen_opc_pc[lj] = dc->ppc | 1;
3165 gen_opc_pc[lj] = dc->pc;
3166 gen_opc_instr_start[lj] = 1;
3167 gen_opc_icount[lj] = num_insns;
3171 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3173 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3177 insn_len = cris_decoder(dc);
3181 cris_clear_x_flag(dc);
3184 /* Check for delayed branches here. If we do it before
3185 actually generating any host code, the simulator will just
3186 loop doing nothing for on this program location. */
3187 if (dc->delayed_branch) {
3188 dc->delayed_branch--;
3189 if (dc->delayed_branch == 0)
3192 t_gen_mov_env_TN(dslot,
3194 if (dc->jmp == JMP_DIRECT) {
3195 dc->is_jmp = DISAS_NEXT;
3197 t_gen_cc_jmp(env_btarget,
3198 tcg_const_tl(dc->pc));
3199 dc->is_jmp = DISAS_JUMP;
3205 /* If we are rexecuting a branch due to exceptions on
3206 delay slots dont break. */
3207 if (!(tb->pc & 1) && env->singlestep_enabled)
3209 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
3210 && (dc->pc < next_page_start)
3211 && num_insns < max_insns);
3214 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3217 if (tb->cflags & CF_LAST_IO)
3219 /* Force an update if the per-tb cpu state has changed. */
3220 if (dc->is_jmp == DISAS_NEXT
3221 && (dc->cpustate_changed || !dc->flagx_known
3222 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3223 dc->is_jmp = DISAS_UPDATE;
3224 tcg_gen_movi_tl(env_pc, npc);
3226 /* Broken branch+delayslot sequence. */
3227 if (dc->delayed_branch == 1) {
3228 /* Set env->dslot to the size of the branch insn. */
3229 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3230 cris_store_direct_jmp(dc);
3233 cris_evaluate_flags (dc);
3235 if (unlikely(env->singlestep_enabled)) {
3236 if (dc->is_jmp == DISAS_NEXT)
3237 tcg_gen_movi_tl(env_pc, npc);
3238 t_gen_raise_exception(EXCP_DEBUG);
3240 switch(dc->is_jmp) {
3242 gen_goto_tb(dc, 1, npc);
3247 /* indicate that the hash table must be used
3248 to find the next TB */
3253 /* nothing more to generate */
3257 gen_icount_end(tb, num_insns);
3258 *gen_opc_ptr = INDEX_op_end;
3260 j = gen_opc_ptr - gen_opc_buf;
3263 gen_opc_instr_start[lj++] = 0;
3265 tb->size = dc->pc - pc_start;
3266 tb->icount = num_insns;
3271 if (loglevel & CPU_LOG_TB_IN_ASM) {
3272 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3273 fprintf(logfile, "\nisize=%d osize=%zd\n",
3274 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3280 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3282 gen_intermediate_code_internal(env, tb, 0);
3285 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3287 gen_intermediate_code_internal(env, tb, 1);
3290 void cpu_dump_state (CPUState *env, FILE *f,
3291 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3300 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3301 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3302 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3304 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3307 for (i = 0; i < 16; i++) {
3308 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3309 if ((i + 1) % 4 == 0)
3310 cpu_fprintf(f, "\n");
3312 cpu_fprintf(f, "\nspecial regs:\n");
3313 for (i = 0; i < 16; i++) {
3314 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3315 if ((i + 1) % 4 == 0)
3316 cpu_fprintf(f, "\n");
3318 srs = env->pregs[PR_SRS];
3319 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3321 for (i = 0; i < 16; i++) {
3322 cpu_fprintf(f, "s%2.2d=%8.8x ",
3323 i, env->sregs[srs][i]);
3324 if ((i + 1) % 4 == 0)
3325 cpu_fprintf(f, "\n");
3328 cpu_fprintf(f, "\n\n");
3332 CPUCRISState *cpu_cris_init (const char *cpu_model)
3335 static int tcg_initialized = 0;
3338 env = qemu_mallocz(sizeof(CPUCRISState));
3345 if (tcg_initialized)
3348 tcg_initialized = 1;
3350 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3351 #if TARGET_LONG_BITS > HOST_LONG_BITS
3352 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3353 TCG_AREG0, offsetof(CPUState, t0), "T0");
3354 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3355 TCG_AREG0, offsetof(CPUState, t1), "T1");
3357 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3358 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3361 cc_x = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3362 offsetof(CPUState, cc_x), "cc_x");
3363 cc_src = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3364 offsetof(CPUState, cc_src), "cc_src");
3365 cc_dest = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3366 offsetof(CPUState, cc_dest),
3368 cc_result = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3369 offsetof(CPUState, cc_result),
3371 cc_op = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3372 offsetof(CPUState, cc_op), "cc_op");
3373 cc_size = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3374 offsetof(CPUState, cc_size),
3376 cc_mask = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3377 offsetof(CPUState, cc_mask),
3380 env_pc = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3381 offsetof(CPUState, pc),
3383 env_btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3384 offsetof(CPUState, btarget),
3386 env_btaken = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3387 offsetof(CPUState, btaken),
3389 for (i = 0; i < 16; i++) {
3390 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3391 offsetof(CPUState, regs[i]),
3394 for (i = 0; i < 16; i++) {
3395 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3396 offsetof(CPUState, pregs[i]),
3400 TCG_HELPER(helper_raise_exception);
3401 TCG_HELPER(helper_dump);
3403 TCG_HELPER(helper_tlb_flush_pid);
3404 TCG_HELPER(helper_movl_sreg_reg);
3405 TCG_HELPER(helper_movl_reg_sreg);
3406 TCG_HELPER(helper_rfe);
3407 TCG_HELPER(helper_rfn);
3409 TCG_HELPER(helper_evaluate_flags_muls);
3410 TCG_HELPER(helper_evaluate_flags_mulu);
3411 TCG_HELPER(helper_evaluate_flags_mcp);
3412 TCG_HELPER(helper_evaluate_flags_alu_4);
3413 TCG_HELPER(helper_evaluate_flags_move_4);
3414 TCG_HELPER(helper_evaluate_flags_move_2);
3415 TCG_HELPER(helper_evaluate_flags);
3416 TCG_HELPER(helper_top_evaluate_flags);
3420 void cpu_reset (CPUCRISState *env)
3422 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3425 env->pregs[PR_VR] = 32;
3426 #if defined(CONFIG_USER_ONLY)
3427 /* start in user mode with interrupts enabled. */
3428 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3430 env->pregs[PR_CCS] = 0;
3434 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3435 unsigned long searched_pc, int pc_pos, void *puc)
3437 env->pc = gen_opc_pc[pc_pos];