2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
47 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
53 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
54 #define BUG_ON(x) ({if (x) BUG();})
58 /* Used by the decoder. */
59 #define EXTRACT_FIELD(src, start, end) \
60 (((src) >> start) & ((1 << (end - start + 1)) - 1))
62 #define CC_MASK_NZ 0xc
63 #define CC_MASK_NZV 0xe
64 #define CC_MASK_NZVC 0xf
65 #define CC_MASK_RNZV 0x10e
67 static TCGv_ptr cpu_env;
68 static TCGv cpu_R[16];
69 static TCGv cpu_PR[16];
73 static TCGv cc_result;
78 static TCGv env_btaken;
79 static TCGv env_btarget;
82 #include "gen-icount.h"
84 /* This is the state at translation time. */
85 typedef struct DisasContext {
94 unsigned int zsize, zzsize;
103 int cc_size_uptodate; /* -1 invalid or last written value. */
105 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
106 int flags_uptodate; /* Wether or not $ccs is uptodate. */
107 int flagx_known; /* Wether or not flags_x has the x flag known at
111 int clear_x; /* Clear x after this insn? */
112 int cpustate_changed;
113 unsigned int tb_flags; /* tb dependent flags. */
118 #define JMP_INDIRECT 2
119 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
124 struct TranslationBlock *tb;
125 int singlestep_enabled;
128 static void gen_BUG(DisasContext *dc, const char *file, int line)
130 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
132 cpu_abort(dc->env, "%s:%d\n", file, line);
135 static const char *regnames[] =
137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
142 static const char *pregnames[] =
144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
150 /* We need this table to handle preg-moves with implicit width. */
151 static int preg_sizes[] = {
162 #define t_gen_mov_TN_env(tn, member) \
163 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
164 #define t_gen_mov_env_TN(member, tn) \
165 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
167 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
170 fprintf(stderr, "wrong register read $r%d\n", r);
171 tcg_gen_mov_tl(tn, cpu_R[r]);
173 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
176 fprintf(stderr, "wrong register write $r%d\n", r);
177 tcg_gen_mov_tl(cpu_R[r], tn);
180 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
182 if (offset > sizeof (CPUState))
183 fprintf(stderr, "wrong load from env from off=%d\n", offset);
184 tcg_gen_ld_tl(tn, cpu_env, offset);
186 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
188 if (offset > sizeof (CPUState))
189 fprintf(stderr, "wrong store to env at off=%d\n", offset);
190 tcg_gen_st_tl(tn, cpu_env, offset);
193 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
196 fprintf(stderr, "wrong register read $p%d\n", r);
197 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
198 tcg_gen_mov_tl(tn, tcg_const_tl(0));
200 tcg_gen_mov_tl(tn, tcg_const_tl(32));
201 else if (r == PR_EDA) {
202 printf("read from EDA!\n");
203 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 tcg_gen_mov_tl(tn, cpu_PR[r]);
208 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
211 fprintf(stderr, "wrong register write $p%d\n", r);
212 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
214 else if (r == PR_SRS)
215 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 gen_helper_tlb_flush_pid(tn);
219 if (dc->tb_flags & S_FLAG && r == PR_SPC)
220 gen_helper_spc_write(tn);
221 else if (r == PR_CCS)
222 dc->cpustate_changed = 1;
223 tcg_gen_mov_tl(cpu_PR[r], tn);
227 static inline void t_gen_raise_exception(uint32_t index)
229 TCGv_i32 tmp = tcg_const_i32(index);
230 gen_helper_raise_exception(tmp);
231 tcg_temp_free_i32(tmp);
234 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
239 t_31 = tcg_const_tl(31);
240 tcg_gen_shl_tl(d, a, b);
242 tcg_gen_sub_tl(t0, t_31, b);
243 tcg_gen_sar_tl(t0, t0, t_31);
244 tcg_gen_and_tl(t0, t0, d);
245 tcg_gen_xor_tl(d, d, t0);
250 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
255 t_31 = tcg_temp_new();
256 tcg_gen_shr_tl(d, a, b);
258 tcg_gen_movi_tl(t_31, 31);
259 tcg_gen_sub_tl(t0, t_31, b);
260 tcg_gen_sar_tl(t0, t0, t_31);
261 tcg_gen_and_tl(t0, t0, d);
262 tcg_gen_xor_tl(d, d, t0);
267 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
272 t_31 = tcg_temp_new();
273 tcg_gen_sar_tl(d, a, b);
275 tcg_gen_movi_tl(t_31, 31);
276 tcg_gen_sub_tl(t0, t_31, b);
277 tcg_gen_sar_tl(t0, t0, t_31);
278 tcg_gen_or_tl(d, d, t0);
283 /* 64-bit signed mul, lower result in d and upper in d2. */
284 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
288 t0 = tcg_temp_new_i64();
289 t1 = tcg_temp_new_i64();
291 tcg_gen_ext_i32_i64(t0, a);
292 tcg_gen_ext_i32_i64(t1, b);
293 tcg_gen_mul_i64(t0, t0, t1);
295 tcg_gen_trunc_i64_i32(d, t0);
296 tcg_gen_shri_i64(t0, t0, 32);
297 tcg_gen_trunc_i64_i32(d2, t0);
299 tcg_temp_free_i64(t0);
300 tcg_temp_free_i64(t1);
303 /* 64-bit unsigned muls, lower result in d and upper in d2. */
304 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
308 t0 = tcg_temp_new_i64();
309 t1 = tcg_temp_new_i64();
311 tcg_gen_extu_i32_i64(t0, a);
312 tcg_gen_extu_i32_i64(t1, b);
313 tcg_gen_mul_i64(t0, t0, t1);
315 tcg_gen_trunc_i64_i32(d, t0);
316 tcg_gen_shri_i64(t0, t0, 32);
317 tcg_gen_trunc_i64_i32(d2, t0);
319 tcg_temp_free_i64(t0);
320 tcg_temp_free_i64(t1);
323 /* 32bit branch-free binary search for counting leading zeros. */
324 static void t_gen_lz_i32(TCGv d, TCGv x)
328 y = tcg_temp_new_i32();
329 m = tcg_temp_new_i32();
330 n = tcg_temp_new_i32();
333 tcg_gen_shri_i32(y, x, 16);
334 tcg_gen_neg_i32(y, y);
336 /* m = (y >> 16) & 16 */
337 tcg_gen_sari_i32(m, y, 16);
338 tcg_gen_andi_i32(m, m, 16);
341 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
343 tcg_gen_shr_i32(x, x, m);
346 tcg_gen_subi_i32(y, x, 0x100);
347 /* m = (y >> 16) & 8 */
348 tcg_gen_sari_i32(m, y, 16);
349 tcg_gen_andi_i32(m, m, 8);
351 tcg_gen_add_i32(n, n, m);
353 tcg_gen_shl_i32(x, x, m);
356 tcg_gen_subi_i32(y, x, 0x1000);
357 /* m = (y >> 16) & 4 */
358 tcg_gen_sari_i32(m, y, 16);
359 tcg_gen_andi_i32(m, m, 4);
361 tcg_gen_add_i32(n, n, m);
363 tcg_gen_shl_i32(x, x, m);
366 tcg_gen_subi_i32(y, x, 0x4000);
367 /* m = (y >> 16) & 2 */
368 tcg_gen_sari_i32(m, y, 16);
369 tcg_gen_andi_i32(m, m, 2);
371 tcg_gen_add_i32(n, n, m);
373 tcg_gen_shl_i32(x, x, m);
376 tcg_gen_shri_i32(y, x, 14);
377 /* m = y & ~(y >> 1) */
378 tcg_gen_sari_i32(m, y, 1);
379 tcg_gen_not_i32(m, m);
380 tcg_gen_and_i32(m, m, y);
383 tcg_gen_addi_i32(d, n, 2);
384 tcg_gen_sub_i32(d, d, m);
391 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
399 The N flag is set according to the selected bit in the dest reg.
400 The Z flag is set if the selected bit and all bits to the right are
402 The X flag is cleared.
403 Other flags are left untouched.
404 The destination reg is not affected.
406 unsigned int fz, sbit, bset, mask, masked_t0;
409 bset = !!(T0 & (1 << sbit));
410 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
411 masked_t0 = T0 & mask;
412 fz = !(masked_t0 | bset);
414 // Clear the X, N and Z flags.
415 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
416 // Set the N and Z flags accordingly.
417 T0 |= (bset << 3) | (fz << 2);
420 l1 = gen_new_label();
421 sbit = tcg_temp_new();
422 bset = tcg_temp_new();
425 /* Compute bset and sbit. */
426 tcg_gen_andi_tl(sbit, b, 31);
427 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
428 tcg_gen_and_tl(bset, a, t0);
429 tcg_gen_shr_tl(bset, bset, sbit);
430 /* Displace to N_FLAG. */
431 tcg_gen_shli_tl(bset, bset, 3);
433 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
434 tcg_gen_subi_tl(sbit, sbit, 1);
435 tcg_gen_and_tl(sbit, a, sbit);
437 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
438 /* or in the N_FLAG. */
439 tcg_gen_or_tl(d, d, bset);
440 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
441 /* or in the Z_FLAG. */
442 tcg_gen_ori_tl(d, d, Z_FLAG);
449 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
453 l1 = gen_new_label();
460 tcg_gen_shli_tl(d, a, 1);
461 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
462 tcg_gen_sub_tl(d, d, b);
466 /* Extended arithmetics on CRIS. */
467 static inline void t_gen_add_flag(TCGv d, int flag)
472 t_gen_mov_TN_preg(c, PR_CCS);
473 /* Propagate carry into d. */
474 tcg_gen_andi_tl(c, c, 1 << flag);
476 tcg_gen_shri_tl(c, c, flag);
477 tcg_gen_add_tl(d, d, c);
481 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
483 if (dc->flagx_known) {
488 t_gen_mov_TN_preg(c, PR_CCS);
489 /* C flag is already at bit 0. */
490 tcg_gen_andi_tl(c, c, C_FLAG);
491 tcg_gen_add_tl(d, d, c);
499 t_gen_mov_TN_preg(x, PR_CCS);
500 tcg_gen_mov_tl(c, x);
502 /* Propagate carry into d if X is set. Branch free. */
503 tcg_gen_andi_tl(c, c, C_FLAG);
504 tcg_gen_andi_tl(x, x, X_FLAG);
505 tcg_gen_shri_tl(x, x, 4);
507 tcg_gen_and_tl(x, x, c);
508 tcg_gen_add_tl(d, d, x);
514 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
516 if (dc->flagx_known) {
521 t_gen_mov_TN_preg(c, PR_CCS);
522 /* C flag is already at bit 0. */
523 tcg_gen_andi_tl(c, c, C_FLAG);
524 tcg_gen_sub_tl(d, d, c);
532 t_gen_mov_TN_preg(x, PR_CCS);
533 tcg_gen_mov_tl(c, x);
535 /* Propagate carry into d if X is set. Branch free. */
536 tcg_gen_andi_tl(c, c, C_FLAG);
537 tcg_gen_andi_tl(x, x, X_FLAG);
538 tcg_gen_shri_tl(x, x, 4);
540 tcg_gen_and_tl(x, x, c);
541 tcg_gen_sub_tl(d, d, x);
547 /* Swap the two bytes within each half word of the s operand.
548 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
549 static inline void t_gen_swapb(TCGv d, TCGv s)
554 org_s = tcg_temp_new();
556 /* d and s may refer to the same object. */
557 tcg_gen_mov_tl(org_s, s);
558 tcg_gen_shli_tl(t, org_s, 8);
559 tcg_gen_andi_tl(d, t, 0xff00ff00);
560 tcg_gen_shri_tl(t, org_s, 8);
561 tcg_gen_andi_tl(t, t, 0x00ff00ff);
562 tcg_gen_or_tl(d, d, t);
564 tcg_temp_free(org_s);
567 /* Swap the halfwords of the s operand. */
568 static inline void t_gen_swapw(TCGv d, TCGv s)
571 /* d and s refer the same object. */
573 tcg_gen_mov_tl(t, s);
574 tcg_gen_shli_tl(d, t, 16);
575 tcg_gen_shri_tl(t, t, 16);
576 tcg_gen_or_tl(d, d, t);
580 /* Reverse the within each byte.
581 T0 = (((T0 << 7) & 0x80808080) |
582 ((T0 << 5) & 0x40404040) |
583 ((T0 << 3) & 0x20202020) |
584 ((T0 << 1) & 0x10101010) |
585 ((T0 >> 1) & 0x08080808) |
586 ((T0 >> 3) & 0x04040404) |
587 ((T0 >> 5) & 0x02020202) |
588 ((T0 >> 7) & 0x01010101));
590 static inline void t_gen_swapr(TCGv d, TCGv s)
593 int shift; /* LSL when positive, LSR when negative. */
608 /* d and s refer the same object. */
610 org_s = tcg_temp_new();
611 tcg_gen_mov_tl(org_s, s);
613 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
614 tcg_gen_andi_tl(d, t, bitrev[0].mask);
615 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
616 if (bitrev[i].shift >= 0) {
617 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
619 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
621 tcg_gen_andi_tl(t, t, bitrev[i].mask);
622 tcg_gen_or_tl(d, d, t);
625 tcg_temp_free(org_s);
628 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
633 l1 = gen_new_label();
634 btaken = tcg_temp_new();
636 /* Conditional jmp. */
637 tcg_gen_mov_tl(btaken, env_btaken);
638 tcg_gen_mov_tl(env_pc, pc_false);
639 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
640 tcg_gen_mov_tl(env_pc, pc_true);
643 tcg_temp_free(btaken);
646 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
648 TranslationBlock *tb;
650 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
652 tcg_gen_movi_tl(env_pc, dest);
653 tcg_gen_exit_tb((long)tb + n);
655 tcg_gen_movi_tl(env_pc, dest);
660 /* Sign extend at translation time. */
661 static int sign_extend(unsigned int val, unsigned int width)
673 static inline void cris_clear_x_flag(DisasContext *dc)
675 if (dc->flagx_known && dc->flags_x)
676 dc->flags_uptodate = 0;
682 static void cris_flush_cc_state(DisasContext *dc)
684 if (dc->cc_size_uptodate != dc->cc_size) {
685 tcg_gen_movi_tl(cc_size, dc->cc_size);
686 dc->cc_size_uptodate = dc->cc_size;
688 tcg_gen_movi_tl(cc_op, dc->cc_op);
689 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
692 static void cris_evaluate_flags(DisasContext *dc)
694 if (!dc->flags_uptodate) {
695 cris_flush_cc_state(dc);
700 gen_helper_evaluate_flags_mcp();
703 gen_helper_evaluate_flags_muls();
706 gen_helper_evaluate_flags_mulu();
718 gen_helper_evaluate_flags_move_4();
721 gen_helper_evaluate_flags_move_2();
724 gen_helper_evaluate_flags();
733 if (dc->cc_size == 4)
734 gen_helper_evaluate_flags_sub_4();
736 gen_helper_evaluate_flags();
743 gen_helper_evaluate_flags_alu_4();
746 gen_helper_evaluate_flags();
751 if (dc->flagx_known) {
753 tcg_gen_ori_tl(cpu_PR[PR_CCS],
754 cpu_PR[PR_CCS], X_FLAG);
756 tcg_gen_andi_tl(cpu_PR[PR_CCS],
757 cpu_PR[PR_CCS], ~X_FLAG);
760 dc->flags_uptodate = 1;
764 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
773 /* Check if we need to evaluate the condition codes due to
775 ovl = (dc->cc_mask ^ mask) & ~mask;
777 /* TODO: optimize this case. It trigs all the time. */
778 cris_evaluate_flags (dc);
784 static void cris_update_cc_op(DisasContext *dc, int op, int size)
788 dc->flags_uptodate = 0;
791 static inline void cris_update_cc_x(DisasContext *dc)
793 /* Save the x flag state at the time of the cc snapshot. */
794 if (dc->flagx_known) {
795 if (dc->cc_x_uptodate == (2 | dc->flags_x))
797 tcg_gen_movi_tl(cc_x, dc->flags_x);
798 dc->cc_x_uptodate = 2 | dc->flags_x;
801 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
802 dc->cc_x_uptodate = 1;
806 /* Update cc prior to executing ALU op. Needs source operands untouched. */
807 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
808 TCGv dst, TCGv src, int size)
811 cris_update_cc_op(dc, op, size);
812 tcg_gen_mov_tl(cc_src, src);
821 tcg_gen_mov_tl(cc_dest, dst);
823 cris_update_cc_x(dc);
827 /* Update cc after executing ALU op. needs the result. */
828 static inline void cris_update_result(DisasContext *dc, TCGv res)
831 tcg_gen_mov_tl(cc_result, res);
834 /* Returns one if the write back stage should execute. */
835 static void cris_alu_op_exec(DisasContext *dc, int op,
836 TCGv dst, TCGv a, TCGv b, int size)
838 /* Emit the ALU insns. */
842 tcg_gen_add_tl(dst, a, b);
843 /* Extended arithmetics. */
844 t_gen_addx_carry(dc, dst);
847 tcg_gen_add_tl(dst, a, b);
848 t_gen_add_flag(dst, 0); /* C_FLAG. */
851 tcg_gen_add_tl(dst, a, b);
852 t_gen_add_flag(dst, 8); /* R_FLAG. */
855 tcg_gen_sub_tl(dst, a, b);
856 /* Extended arithmetics. */
857 t_gen_subx_carry(dc, dst);
860 tcg_gen_mov_tl(dst, b);
863 tcg_gen_or_tl(dst, a, b);
866 tcg_gen_and_tl(dst, a, b);
869 tcg_gen_xor_tl(dst, a, b);
872 t_gen_lsl(dst, a, b);
875 t_gen_lsr(dst, a, b);
878 t_gen_asr(dst, a, b);
881 tcg_gen_neg_tl(dst, b);
882 /* Extended arithmetics. */
883 t_gen_subx_carry(dc, dst);
886 t_gen_lz_i32(dst, b);
889 t_gen_btst(dst, a, b);
892 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
895 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
898 t_gen_cris_dstep(dst, a, b);
903 l1 = gen_new_label();
904 tcg_gen_mov_tl(dst, a);
905 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
906 tcg_gen_mov_tl(dst, b);
911 tcg_gen_sub_tl(dst, a, b);
912 /* Extended arithmetics. */
913 t_gen_subx_carry(dc, dst);
916 fprintf (logfile, "illegal ALU op.\n");
922 tcg_gen_andi_tl(dst, dst, 0xff);
924 tcg_gen_andi_tl(dst, dst, 0xffff);
927 static void cris_alu(DisasContext *dc, int op,
928 TCGv d, TCGv op_a, TCGv op_b, int size)
935 if (op == CC_OP_BOUND || op == CC_OP_BTST)
936 tmp = tcg_temp_local_new();
938 if (op == CC_OP_CMP) {
939 tmp = tcg_temp_new();
941 } else if (size == 4) {
945 tmp = tcg_temp_new();
948 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
949 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
950 cris_update_result(dc, tmp);
955 tcg_gen_andi_tl(d, d, ~0xff);
957 tcg_gen_andi_tl(d, d, ~0xffff);
958 tcg_gen_or_tl(d, d, tmp);
960 if (!TCGV_EQUAL(tmp, d))
964 static int arith_cc(DisasContext *dc)
968 case CC_OP_ADDC: return 1;
969 case CC_OP_ADD: return 1;
970 case CC_OP_SUB: return 1;
971 case CC_OP_DSTEP: return 1;
972 case CC_OP_LSL: return 1;
973 case CC_OP_LSR: return 1;
974 case CC_OP_ASR: return 1;
975 case CC_OP_CMP: return 1;
976 case CC_OP_NEG: return 1;
977 case CC_OP_OR: return 1;
978 case CC_OP_XOR: return 1;
979 case CC_OP_MULU: return 1;
980 case CC_OP_MULS: return 1;
988 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
990 int arith_opt, move_opt;
992 /* TODO: optimize more condition codes. */
995 * If the flags are live, we've gotta look into the bits of CCS.
996 * Otherwise, if we just did an arithmetic operation we try to
997 * evaluate the condition code faster.
999 * When this function is done, T0 should be non-zero if the condition
1002 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
1003 move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
1006 if (arith_opt || move_opt) {
1007 /* If cc_result is zero, T0 should be
1008 non-zero otherwise T0 should be zero. */
1010 l1 = gen_new_label();
1011 tcg_gen_movi_tl(cc, 0);
1012 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
1014 tcg_gen_movi_tl(cc, 1);
1018 cris_evaluate_flags(dc);
1020 cpu_PR[PR_CCS], Z_FLAG);
1024 if (arith_opt || move_opt)
1025 tcg_gen_mov_tl(cc, cc_result);
1027 cris_evaluate_flags(dc);
1028 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1030 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1034 cris_evaluate_flags(dc);
1035 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1038 cris_evaluate_flags(dc);
1039 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1040 tcg_gen_andi_tl(cc, cc, C_FLAG);
1043 cris_evaluate_flags(dc);
1044 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
1047 cris_evaluate_flags(dc);
1048 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1050 tcg_gen_andi_tl(cc, cc, V_FLAG);
1053 if (arith_opt || move_opt) {
1056 if (dc->cc_size == 1)
1058 else if (dc->cc_size == 2)
1061 tcg_gen_shri_tl(cc, cc_result, bits);
1062 tcg_gen_xori_tl(cc, cc, 1);
1064 cris_evaluate_flags(dc);
1065 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1067 tcg_gen_andi_tl(cc, cc, N_FLAG);
1071 if (arith_opt || move_opt) {
1074 if (dc->cc_size == 1)
1076 else if (dc->cc_size == 2)
1079 tcg_gen_shri_tl(cc, cc_result, 31);
1082 cris_evaluate_flags(dc);
1083 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1088 cris_evaluate_flags(dc);
1089 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1093 cris_evaluate_flags(dc);
1097 tmp = tcg_temp_new();
1098 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1100 /* Overlay the C flag on top of the Z. */
1101 tcg_gen_shli_tl(cc, tmp, 2);
1102 tcg_gen_and_tl(cc, tmp, cc);
1103 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1109 cris_evaluate_flags(dc);
1110 /* Overlay the V flag on top of the N. */
1111 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1113 cpu_PR[PR_CCS], cc);
1114 tcg_gen_andi_tl(cc, cc, N_FLAG);
1115 tcg_gen_xori_tl(cc, cc, N_FLAG);
1118 cris_evaluate_flags(dc);
1119 /* Overlay the V flag on top of the N. */
1120 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1122 cpu_PR[PR_CCS], cc);
1123 tcg_gen_andi_tl(cc, cc, N_FLAG);
1126 cris_evaluate_flags(dc);
1133 /* To avoid a shift we overlay everything on
1135 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1136 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1138 tcg_gen_xori_tl(z, z, 2);
1140 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1141 tcg_gen_xori_tl(n, n, 2);
1142 tcg_gen_and_tl(cc, z, n);
1143 tcg_gen_andi_tl(cc, cc, 2);
1150 cris_evaluate_flags(dc);
1157 /* To avoid a shift we overlay everything on
1159 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1160 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1162 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1163 tcg_gen_or_tl(cc, z, n);
1164 tcg_gen_andi_tl(cc, cc, 2);
1171 cris_evaluate_flags(dc);
1172 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1175 tcg_gen_movi_tl(cc, 1);
1183 static void cris_store_direct_jmp(DisasContext *dc)
1185 /* Store the direct jmp state into the cpu-state. */
1186 if (dc->jmp == JMP_DIRECT) {
1187 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1188 tcg_gen_movi_tl(env_btaken, 1);
1192 static void cris_prepare_cc_branch (DisasContext *dc,
1193 int offset, int cond)
1195 /* This helps us re-schedule the micro-code to insns in delay-slots
1196 before the actual jump. */
1197 dc->delayed_branch = 2;
1198 dc->jmp_pc = dc->pc + offset;
1202 dc->jmp = JMP_INDIRECT;
1203 gen_tst_cc (dc, env_btaken, cond);
1204 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1206 /* Allow chaining. */
1207 dc->jmp = JMP_DIRECT;
1212 /* jumps, when the dest is in a live reg for example. Direct should be set
1213 when the dest addr is constant to allow tb chaining. */
1214 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1216 /* This helps us re-schedule the micro-code to insns in delay-slots
1217 before the actual jump. */
1218 dc->delayed_branch = 2;
1220 if (type == JMP_INDIRECT)
1221 tcg_gen_movi_tl(env_btaken, 1);
1224 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1226 int mem_index = cpu_mmu_index(dc->env);
1228 /* If we get a fault on a delayslot we must keep the jmp state in
1229 the cpu-state to be able to re-execute the jmp. */
1230 if (dc->delayed_branch == 1)
1231 cris_store_direct_jmp(dc);
1233 tcg_gen_qemu_ld64(dst, addr, mem_index);
1236 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1237 unsigned int size, int sign)
1239 int mem_index = cpu_mmu_index(dc->env);
1241 /* If we get a fault on a delayslot we must keep the jmp state in
1242 the cpu-state to be able to re-execute the jmp. */
1243 if (dc->delayed_branch == 1)
1244 cris_store_direct_jmp(dc);
1248 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1250 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1252 else if (size == 2) {
1254 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1256 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1258 else if (size == 4) {
1259 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1266 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1269 int mem_index = cpu_mmu_index(dc->env);
1271 /* If we get a fault on a delayslot we must keep the jmp state in
1272 the cpu-state to be able to re-execute the jmp. */
1273 if (dc->delayed_branch == 1)
1274 cris_store_direct_jmp(dc);
1277 /* Conditional writes. We only support the kind were X and P are known
1278 at translation time. */
1279 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1281 cris_evaluate_flags(dc);
1282 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1287 tcg_gen_qemu_st8(val, addr, mem_index);
1289 tcg_gen_qemu_st16(val, addr, mem_index);
1291 tcg_gen_qemu_st32(val, addr, mem_index);
1293 if (dc->flagx_known && dc->flags_x) {
1294 cris_evaluate_flags(dc);
1295 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1299 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1302 tcg_gen_ext8s_i32(d, s);
1304 tcg_gen_ext16s_i32(d, s);
1305 else if(!TCGV_EQUAL(d, s))
1306 tcg_gen_mov_tl(d, s);
1309 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1312 tcg_gen_ext8u_i32(d, s);
1314 tcg_gen_ext16u_i32(d, s);
1315 else if (!TCGV_EQUAL(d, s))
1316 tcg_gen_mov_tl(d, s);
1320 static char memsize_char(int size)
1324 case 1: return 'b'; break;
1325 case 2: return 'w'; break;
1326 case 4: return 'd'; break;
1334 static inline unsigned int memsize_z(DisasContext *dc)
1336 return dc->zsize + 1;
1339 static inline unsigned int memsize_zz(DisasContext *dc)
1350 static inline void do_postinc (DisasContext *dc, int size)
1353 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1356 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1357 int size, int s_ext, TCGv dst)
1360 t_gen_sext(dst, cpu_R[rs], size);
1362 t_gen_zext(dst, cpu_R[rs], size);
1365 /* Prepare T0 and T1 for a register alu operation.
1366 s_ext decides if the operand1 should be sign-extended or zero-extended when
1368 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1369 int size, int s_ext, TCGv dst, TCGv src)
1371 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1374 t_gen_sext(dst, cpu_R[rd], size);
1376 t_gen_zext(dst, cpu_R[rd], size);
1379 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1382 unsigned int rs, rd;
1389 is_imm = rs == 15 && dc->postinc;
1391 /* Load [$rs] onto T1. */
1393 insn_len = 2 + memsize;
1400 imm = ldsb_code(dc->pc + 2);
1402 imm = ldsw_code(dc->pc + 2);
1405 imm = ldub_code(dc->pc + 2);
1407 imm = lduw_code(dc->pc + 2);
1410 imm = ldl_code(dc->pc + 2);
1412 tcg_gen_movi_tl(dst, imm);
1415 cris_flush_cc_state(dc);
1416 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1418 t_gen_sext(dst, dst, memsize);
1420 t_gen_zext(dst, dst, memsize);
1425 /* Prepare T0 and T1 for a memory + alu operation.
1426 s_ext decides if the operand1 should be sign-extended or zero-extended when
1428 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1433 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1434 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1439 static const char *cc_name(int cc)
1441 static const char *cc_names[16] = {
1442 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1443 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1446 return cc_names[cc];
1450 /* Start of insn decoders. */
1452 static unsigned int dec_bccq(DisasContext *dc)
1456 uint32_t cond = dc->op2;
1459 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1460 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1463 offset |= sign << 8;
1465 offset = sign_extend(offset, 8);
1467 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1469 /* op2 holds the condition-code. */
1470 cris_cc_mask(dc, 0);
1471 cris_prepare_cc_branch (dc, offset, cond);
1474 static unsigned int dec_addoq(DisasContext *dc)
1478 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1479 imm = sign_extend(dc->op1, 7);
1481 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1482 cris_cc_mask(dc, 0);
1483 /* Fetch register operand, */
1484 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1488 static unsigned int dec_addq(DisasContext *dc)
1490 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1492 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1494 cris_cc_mask(dc, CC_MASK_NZVC);
1496 cris_alu(dc, CC_OP_ADD,
1497 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1500 static unsigned int dec_moveq(DisasContext *dc)
1504 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1505 imm = sign_extend(dc->op1, 5);
1506 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1508 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1511 static unsigned int dec_subq(DisasContext *dc)
1513 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1515 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1517 cris_cc_mask(dc, CC_MASK_NZVC);
1518 cris_alu(dc, CC_OP_SUB,
1519 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1522 static unsigned int dec_cmpq(DisasContext *dc)
1525 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1526 imm = sign_extend(dc->op1, 5);
1528 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1529 cris_cc_mask(dc, CC_MASK_NZVC);
1531 cris_alu(dc, CC_OP_CMP,
1532 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1535 static unsigned int dec_andq(DisasContext *dc)
1538 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1539 imm = sign_extend(dc->op1, 5);
1541 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1542 cris_cc_mask(dc, CC_MASK_NZ);
1544 cris_alu(dc, CC_OP_AND,
1545 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1548 static unsigned int dec_orq(DisasContext *dc)
1551 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1552 imm = sign_extend(dc->op1, 5);
1553 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1554 cris_cc_mask(dc, CC_MASK_NZ);
1556 cris_alu(dc, CC_OP_OR,
1557 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1560 static unsigned int dec_btstq(DisasContext *dc)
1563 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1564 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1566 cris_cc_mask(dc, CC_MASK_NZ);
1567 l0 = tcg_temp_local_new();
1568 cris_alu(dc, CC_OP_BTST,
1569 l0, cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1570 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1571 t_gen_mov_preg_TN(dc, PR_CCS, l0);
1572 dc->flags_uptodate = 1;
1576 static unsigned int dec_asrq(DisasContext *dc)
1578 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1579 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1580 cris_cc_mask(dc, CC_MASK_NZ);
1582 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1583 cris_alu(dc, CC_OP_MOVE,
1585 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1588 static unsigned int dec_lslq(DisasContext *dc)
1590 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1591 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1593 cris_cc_mask(dc, CC_MASK_NZ);
1595 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1597 cris_alu(dc, CC_OP_MOVE,
1599 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1602 static unsigned int dec_lsrq(DisasContext *dc)
1604 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1605 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1607 cris_cc_mask(dc, CC_MASK_NZ);
1609 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1610 cris_alu(dc, CC_OP_MOVE,
1612 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1616 static unsigned int dec_move_r(DisasContext *dc)
1618 int size = memsize_zz(dc);
1620 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1621 memsize_char(size), dc->op1, dc->op2));
1623 cris_cc_mask(dc, CC_MASK_NZ);
1625 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1626 cris_cc_mask(dc, CC_MASK_NZ);
1627 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1628 cris_update_cc_x(dc);
1629 cris_update_result(dc, cpu_R[dc->op2]);
1634 t0 = tcg_temp_new();
1635 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1636 cris_alu(dc, CC_OP_MOVE,
1638 cpu_R[dc->op2], t0, size);
1644 static unsigned int dec_scc_r(DisasContext *dc)
1648 DIS(fprintf (logfile, "s%s $r%u\n",
1649 cc_name(cond), dc->op1));
1655 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1656 l1 = gen_new_label();
1657 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1658 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1662 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1664 cris_cc_mask(dc, 0);
1668 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1671 t[0] = cpu_R[dc->op2];
1672 t[1] = cpu_R[dc->op1];
1674 t[0] = tcg_temp_new();
1675 t[1] = tcg_temp_new();
1679 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1682 tcg_temp_free(t[0]);
1683 tcg_temp_free(t[1]);
1687 static unsigned int dec_and_r(DisasContext *dc)
1690 int size = memsize_zz(dc);
1692 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1693 memsize_char(size), dc->op1, dc->op2));
1695 cris_cc_mask(dc, CC_MASK_NZ);
1697 cris_alu_alloc_temps(dc, size, t);
1698 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1699 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1700 cris_alu_free_temps(dc, size, t);
1704 static unsigned int dec_lz_r(DisasContext *dc)
1707 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1709 cris_cc_mask(dc, CC_MASK_NZ);
1710 t0 = tcg_temp_new();
1711 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1712 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1717 static unsigned int dec_lsl_r(DisasContext *dc)
1720 int size = memsize_zz(dc);
1722 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1723 memsize_char(size), dc->op1, dc->op2));
1725 cris_cc_mask(dc, CC_MASK_NZ);
1726 cris_alu_alloc_temps(dc, size, t);
1727 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1728 tcg_gen_andi_tl(t[1], t[1], 63);
1729 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1730 cris_alu_alloc_temps(dc, size, t);
1734 static unsigned int dec_lsr_r(DisasContext *dc)
1737 int size = memsize_zz(dc);
1739 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1740 memsize_char(size), dc->op1, dc->op2));
1742 cris_cc_mask(dc, CC_MASK_NZ);
1743 cris_alu_alloc_temps(dc, size, t);
1744 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1745 tcg_gen_andi_tl(t[1], t[1], 63);
1746 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1747 cris_alu_free_temps(dc, size, t);
1751 static unsigned int dec_asr_r(DisasContext *dc)
1754 int size = memsize_zz(dc);
1756 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1757 memsize_char(size), dc->op1, dc->op2));
1759 cris_cc_mask(dc, CC_MASK_NZ);
1760 cris_alu_alloc_temps(dc, size, t);
1761 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1762 tcg_gen_andi_tl(t[1], t[1], 63);
1763 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1764 cris_alu_free_temps(dc, size, t);
1768 static unsigned int dec_muls_r(DisasContext *dc)
1771 int size = memsize_zz(dc);
1773 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1774 memsize_char(size), dc->op1, dc->op2));
1775 cris_cc_mask(dc, CC_MASK_NZV);
1776 cris_alu_alloc_temps(dc, size, t);
1777 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1779 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1780 cris_alu_free_temps(dc, size, t);
1784 static unsigned int dec_mulu_r(DisasContext *dc)
1787 int size = memsize_zz(dc);
1789 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1790 memsize_char(size), dc->op1, dc->op2));
1791 cris_cc_mask(dc, CC_MASK_NZV);
1792 cris_alu_alloc_temps(dc, size, t);
1793 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1795 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1796 cris_alu_alloc_temps(dc, size, t);
1801 static unsigned int dec_dstep_r(DisasContext *dc)
1803 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1804 cris_cc_mask(dc, CC_MASK_NZ);
1805 cris_alu(dc, CC_OP_DSTEP,
1806 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1810 static unsigned int dec_xor_r(DisasContext *dc)
1813 int size = memsize_zz(dc);
1814 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1815 memsize_char(size), dc->op1, dc->op2));
1816 BUG_ON(size != 4); /* xor is dword. */
1817 cris_cc_mask(dc, CC_MASK_NZ);
1818 cris_alu_alloc_temps(dc, size, t);
1819 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1821 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1822 cris_alu_free_temps(dc, size, t);
1826 static unsigned int dec_bound_r(DisasContext *dc)
1829 int size = memsize_zz(dc);
1830 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1831 memsize_char(size), dc->op1, dc->op2));
1832 cris_cc_mask(dc, CC_MASK_NZ);
1833 l0 = tcg_temp_local_new();
1834 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1835 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1840 static unsigned int dec_cmp_r(DisasContext *dc)
1843 int size = memsize_zz(dc);
1844 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1845 memsize_char(size), dc->op1, dc->op2));
1846 cris_cc_mask(dc, CC_MASK_NZVC);
1847 cris_alu_alloc_temps(dc, size, t);
1848 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1850 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1851 cris_alu_free_temps(dc, size, t);
1855 static unsigned int dec_abs_r(DisasContext *dc)
1859 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1861 cris_cc_mask(dc, CC_MASK_NZ);
1863 t0 = tcg_temp_new();
1864 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1865 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1866 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1869 cris_alu(dc, CC_OP_MOVE,
1870 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1874 static unsigned int dec_add_r(DisasContext *dc)
1877 int size = memsize_zz(dc);
1878 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1879 memsize_char(size), dc->op1, dc->op2));
1880 cris_cc_mask(dc, CC_MASK_NZVC);
1881 cris_alu_alloc_temps(dc, size, t);
1882 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1884 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1885 cris_alu_free_temps(dc, size, t);
1889 static unsigned int dec_addc_r(DisasContext *dc)
1891 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1893 cris_evaluate_flags(dc);
1894 /* Set for this insn. */
1895 dc->flagx_known = 1;
1896 dc->flags_x = X_FLAG;
1898 cris_cc_mask(dc, CC_MASK_NZVC);
1899 cris_alu(dc, CC_OP_ADDC,
1900 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1904 static unsigned int dec_mcp_r(DisasContext *dc)
1906 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1908 cris_evaluate_flags(dc);
1909 cris_cc_mask(dc, CC_MASK_RNZV);
1910 cris_alu(dc, CC_OP_MCP,
1911 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1916 static char * swapmode_name(int mode, char *modename) {
1919 modename[i++] = 'n';
1921 modename[i++] = 'w';
1923 modename[i++] = 'b';
1925 modename[i++] = 'r';
1931 static unsigned int dec_swap_r(DisasContext *dc)
1937 DIS(fprintf (logfile, "swap%s $r%u\n",
1938 swapmode_name(dc->op2, modename), dc->op1));
1940 cris_cc_mask(dc, CC_MASK_NZ);
1941 t0 = tcg_temp_new();
1942 t_gen_mov_TN_reg(t0, dc->op1);
1944 tcg_gen_not_tl(t0, t0);
1946 t_gen_swapw(t0, t0);
1948 t_gen_swapb(t0, t0);
1950 t_gen_swapr(t0, t0);
1951 cris_alu(dc, CC_OP_MOVE,
1952 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1957 static unsigned int dec_or_r(DisasContext *dc)
1960 int size = memsize_zz(dc);
1961 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1962 memsize_char(size), dc->op1, dc->op2));
1963 cris_cc_mask(dc, CC_MASK_NZ);
1964 cris_alu_alloc_temps(dc, size, t);
1965 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1966 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1967 cris_alu_free_temps(dc, size, t);
1971 static unsigned int dec_addi_r(DisasContext *dc)
1974 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1975 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1976 cris_cc_mask(dc, 0);
1977 t0 = tcg_temp_new();
1978 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1979 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1984 static unsigned int dec_addi_acr(DisasContext *dc)
1987 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1988 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1989 cris_cc_mask(dc, 0);
1990 t0 = tcg_temp_new();
1991 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1992 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1997 static unsigned int dec_neg_r(DisasContext *dc)
2000 int size = memsize_zz(dc);
2001 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
2002 memsize_char(size), dc->op1, dc->op2));
2003 cris_cc_mask(dc, CC_MASK_NZVC);
2004 cris_alu_alloc_temps(dc, size, t);
2005 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
2007 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
2008 cris_alu_free_temps(dc, size, t);
2012 static unsigned int dec_btst_r(DisasContext *dc)
2015 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
2017 cris_cc_mask(dc, CC_MASK_NZ);
2019 l0 = tcg_temp_local_new();
2020 cris_alu(dc, CC_OP_BTST, l0, cpu_R[dc->op2], cpu_R[dc->op1], 4);
2021 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2022 t_gen_mov_preg_TN(dc, PR_CCS, l0);
2023 dc->flags_uptodate = 1;
2028 static unsigned int dec_sub_r(DisasContext *dc)
2031 int size = memsize_zz(dc);
2032 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
2033 memsize_char(size), dc->op1, dc->op2));
2034 cris_cc_mask(dc, CC_MASK_NZVC);
2035 cris_alu_alloc_temps(dc, size, t);
2036 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
2037 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
2038 cris_alu_free_temps(dc, size, t);
2042 /* Zero extension. From size to dword. */
2043 static unsigned int dec_movu_r(DisasContext *dc)
2046 int size = memsize_z(dc);
2047 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
2051 cris_cc_mask(dc, CC_MASK_NZ);
2052 t0 = tcg_temp_new();
2053 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
2054 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2059 /* Sign extension. From size to dword. */
2060 static unsigned int dec_movs_r(DisasContext *dc)
2063 int size = memsize_z(dc);
2064 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
2068 cris_cc_mask(dc, CC_MASK_NZ);
2069 t0 = tcg_temp_new();
2070 /* Size can only be qi or hi. */
2071 t_gen_sext(t0, cpu_R[dc->op1], size);
2072 cris_alu(dc, CC_OP_MOVE,
2073 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
2078 /* zero extension. From size to dword. */
2079 static unsigned int dec_addu_r(DisasContext *dc)
2082 int size = memsize_z(dc);
2083 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
2087 cris_cc_mask(dc, CC_MASK_NZVC);
2088 t0 = tcg_temp_new();
2089 /* Size can only be qi or hi. */
2090 t_gen_zext(t0, cpu_R[dc->op1], size);
2091 cris_alu(dc, CC_OP_ADD,
2092 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2097 /* Sign extension. From size to dword. */
2098 static unsigned int dec_adds_r(DisasContext *dc)
2101 int size = memsize_z(dc);
2102 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2106 cris_cc_mask(dc, CC_MASK_NZVC);
2107 t0 = tcg_temp_new();
2108 /* Size can only be qi or hi. */
2109 t_gen_sext(t0, cpu_R[dc->op1], size);
2110 cris_alu(dc, CC_OP_ADD,
2111 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2116 /* Zero extension. From size to dword. */
2117 static unsigned int dec_subu_r(DisasContext *dc)
2120 int size = memsize_z(dc);
2121 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2125 cris_cc_mask(dc, CC_MASK_NZVC);
2126 t0 = tcg_temp_new();
2127 /* Size can only be qi or hi. */
2128 t_gen_zext(t0, cpu_R[dc->op1], size);
2129 cris_alu(dc, CC_OP_SUB,
2130 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2135 /* Sign extension. From size to dword. */
2136 static unsigned int dec_subs_r(DisasContext *dc)
2139 int size = memsize_z(dc);
2140 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2144 cris_cc_mask(dc, CC_MASK_NZVC);
2145 t0 = tcg_temp_new();
2146 /* Size can only be qi or hi. */
2147 t_gen_sext(t0, cpu_R[dc->op1], size);
2148 cris_alu(dc, CC_OP_SUB,
2149 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2154 static unsigned int dec_setclrf(DisasContext *dc)
2157 int set = (~dc->opcode >> 2) & 1;
2160 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2161 | EXTRACT_FIELD(dc->ir, 0, 3);
2162 if (set && flags == 0) {
2163 DIS(fprintf (logfile, "nop\n"));
2165 } else if (!set && (flags & 0x20)) {
2166 DIS(fprintf (logfile, "di\n"));
2169 DIS(fprintf (logfile, "%sf %x\n",
2170 set ? "set" : "clr",
2174 /* User space is not allowed to touch these. Silently ignore. */
2175 if (dc->tb_flags & U_FLAG) {
2176 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2179 if (flags & X_FLAG) {
2180 dc->flagx_known = 1;
2182 dc->flags_x = X_FLAG;
2187 /* Break the TB if the P flag changes. */
2188 if (flags & P_FLAG) {
2189 if ((set && !(dc->tb_flags & P_FLAG))
2190 || (!set && (dc->tb_flags & P_FLAG))) {
2191 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2192 dc->is_jmp = DISAS_UPDATE;
2193 dc->cpustate_changed = 1;
2196 if (flags & S_FLAG) {
2197 dc->cpustate_changed = 1;
2201 /* Simply decode the flags. */
2202 cris_evaluate_flags (dc);
2203 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2204 cris_update_cc_x(dc);
2205 tcg_gen_movi_tl(cc_op, dc->cc_op);
2208 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2209 /* Enter user mode. */
2210 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2211 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2212 dc->cpustate_changed = 1;
2214 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2217 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2219 dc->flags_uptodate = 1;
2224 static unsigned int dec_move_rs(DisasContext *dc)
2226 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2227 cris_cc_mask(dc, 0);
2228 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2231 static unsigned int dec_move_sr(DisasContext *dc)
2233 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2234 cris_cc_mask(dc, 0);
2235 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2239 static unsigned int dec_move_rp(DisasContext *dc)
2242 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2243 cris_cc_mask(dc, 0);
2245 t[0] = tcg_temp_new();
2246 if (dc->op2 == PR_CCS) {
2247 cris_evaluate_flags(dc);
2248 t_gen_mov_TN_reg(t[0], dc->op1);
2249 if (dc->tb_flags & U_FLAG) {
2250 t[1] = tcg_temp_new();
2251 /* User space is not allowed to touch all flags. */
2252 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2253 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2254 tcg_gen_or_tl(t[0], t[1], t[0]);
2255 tcg_temp_free(t[1]);
2259 t_gen_mov_TN_reg(t[0], dc->op1);
2261 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2262 if (dc->op2 == PR_CCS) {
2263 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2264 dc->flags_uptodate = 1;
2266 tcg_temp_free(t[0]);
2269 static unsigned int dec_move_pr(DisasContext *dc)
2272 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2273 cris_cc_mask(dc, 0);
2275 if (dc->op2 == PR_CCS)
2276 cris_evaluate_flags(dc);
2278 t0 = tcg_temp_new();
2279 t_gen_mov_TN_preg(t0, dc->op2);
2280 cris_alu(dc, CC_OP_MOVE,
2281 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2286 static unsigned int dec_move_mr(DisasContext *dc)
2288 int memsize = memsize_zz(dc);
2290 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2291 memsize_char(memsize),
2292 dc->op1, dc->postinc ? "+]" : "]",
2296 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2297 cris_cc_mask(dc, CC_MASK_NZ);
2298 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2299 cris_update_cc_x(dc);
2300 cris_update_result(dc, cpu_R[dc->op2]);
2305 t0 = tcg_temp_new();
2306 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2307 cris_cc_mask(dc, CC_MASK_NZ);
2308 cris_alu(dc, CC_OP_MOVE,
2309 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2312 do_postinc(dc, memsize);
2316 static inline void cris_alu_m_alloc_temps(TCGv *t)
2318 t[0] = tcg_temp_new();
2319 t[1] = tcg_temp_new();
2322 static inline void cris_alu_m_free_temps(TCGv *t)
2324 tcg_temp_free(t[0]);
2325 tcg_temp_free(t[1]);
2328 static unsigned int dec_movs_m(DisasContext *dc)
2331 int memsize = memsize_z(dc);
2333 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2334 memsize_char(memsize),
2335 dc->op1, dc->postinc ? "+]" : "]",
2338 cris_alu_m_alloc_temps(t);
2340 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2341 cris_cc_mask(dc, CC_MASK_NZ);
2342 cris_alu(dc, CC_OP_MOVE,
2343 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2344 do_postinc(dc, memsize);
2345 cris_alu_m_free_temps(t);
2349 static unsigned int dec_addu_m(DisasContext *dc)
2352 int memsize = memsize_z(dc);
2354 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2355 memsize_char(memsize),
2356 dc->op1, dc->postinc ? "+]" : "]",
2359 cris_alu_m_alloc_temps(t);
2361 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2362 cris_cc_mask(dc, CC_MASK_NZVC);
2363 cris_alu(dc, CC_OP_ADD,
2364 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2365 do_postinc(dc, memsize);
2366 cris_alu_m_free_temps(t);
2370 static unsigned int dec_adds_m(DisasContext *dc)
2373 int memsize = memsize_z(dc);
2375 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2376 memsize_char(memsize),
2377 dc->op1, dc->postinc ? "+]" : "]",
2380 cris_alu_m_alloc_temps(t);
2382 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2383 cris_cc_mask(dc, CC_MASK_NZVC);
2384 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2385 do_postinc(dc, memsize);
2386 cris_alu_m_free_temps(t);
2390 static unsigned int dec_subu_m(DisasContext *dc)
2393 int memsize = memsize_z(dc);
2395 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2396 memsize_char(memsize),
2397 dc->op1, dc->postinc ? "+]" : "]",
2400 cris_alu_m_alloc_temps(t);
2402 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2403 cris_cc_mask(dc, CC_MASK_NZVC);
2404 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2405 do_postinc(dc, memsize);
2406 cris_alu_m_free_temps(t);
2410 static unsigned int dec_subs_m(DisasContext *dc)
2413 int memsize = memsize_z(dc);
2415 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2416 memsize_char(memsize),
2417 dc->op1, dc->postinc ? "+]" : "]",
2420 cris_alu_m_alloc_temps(t);
2422 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2423 cris_cc_mask(dc, CC_MASK_NZVC);
2424 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2425 do_postinc(dc, memsize);
2426 cris_alu_m_free_temps(t);
2430 static unsigned int dec_movu_m(DisasContext *dc)
2433 int memsize = memsize_z(dc);
2436 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2437 memsize_char(memsize),
2438 dc->op1, dc->postinc ? "+]" : "]",
2441 cris_alu_m_alloc_temps(t);
2442 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2443 cris_cc_mask(dc, CC_MASK_NZ);
2444 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2445 do_postinc(dc, memsize);
2446 cris_alu_m_free_temps(t);
2450 static unsigned int dec_cmpu_m(DisasContext *dc)
2453 int memsize = memsize_z(dc);
2455 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2456 memsize_char(memsize),
2457 dc->op1, dc->postinc ? "+]" : "]",
2460 cris_alu_m_alloc_temps(t);
2461 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2462 cris_cc_mask(dc, CC_MASK_NZVC);
2463 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2464 do_postinc(dc, memsize);
2465 cris_alu_m_free_temps(t);
2469 static unsigned int dec_cmps_m(DisasContext *dc)
2472 int memsize = memsize_z(dc);
2474 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2475 memsize_char(memsize),
2476 dc->op1, dc->postinc ? "+]" : "]",
2479 cris_alu_m_alloc_temps(t);
2480 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2481 cris_cc_mask(dc, CC_MASK_NZVC);
2482 cris_alu(dc, CC_OP_CMP,
2483 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2485 do_postinc(dc, memsize);
2486 cris_alu_m_free_temps(t);
2490 static unsigned int dec_cmp_m(DisasContext *dc)
2493 int memsize = memsize_zz(dc);
2495 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2496 memsize_char(memsize),
2497 dc->op1, dc->postinc ? "+]" : "]",
2500 cris_alu_m_alloc_temps(t);
2501 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2502 cris_cc_mask(dc, CC_MASK_NZVC);
2503 cris_alu(dc, CC_OP_CMP,
2504 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2506 do_postinc(dc, memsize);
2507 cris_alu_m_free_temps(t);
2511 static unsigned int dec_test_m(DisasContext *dc)
2514 int memsize = memsize_zz(dc);
2516 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2517 memsize_char(memsize),
2518 dc->op1, dc->postinc ? "+]" : "]",
2521 cris_evaluate_flags(dc);
2523 cris_alu_m_alloc_temps(t);
2524 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2525 cris_cc_mask(dc, CC_MASK_NZ);
2526 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2528 cris_alu(dc, CC_OP_CMP,
2529 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2530 do_postinc(dc, memsize);
2531 cris_alu_m_free_temps(t);
2535 static unsigned int dec_and_m(DisasContext *dc)
2538 int memsize = memsize_zz(dc);
2540 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2541 memsize_char(memsize),
2542 dc->op1, dc->postinc ? "+]" : "]",
2545 cris_alu_m_alloc_temps(t);
2546 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2547 cris_cc_mask(dc, CC_MASK_NZ);
2548 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2549 do_postinc(dc, memsize);
2550 cris_alu_m_free_temps(t);
2554 static unsigned int dec_add_m(DisasContext *dc)
2557 int memsize = memsize_zz(dc);
2559 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2560 memsize_char(memsize),
2561 dc->op1, dc->postinc ? "+]" : "]",
2564 cris_alu_m_alloc_temps(t);
2565 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2566 cris_cc_mask(dc, CC_MASK_NZVC);
2567 cris_alu(dc, CC_OP_ADD,
2568 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2569 do_postinc(dc, memsize);
2570 cris_alu_m_free_temps(t);
2574 static unsigned int dec_addo_m(DisasContext *dc)
2577 int memsize = memsize_zz(dc);
2579 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2580 memsize_char(memsize),
2581 dc->op1, dc->postinc ? "+]" : "]",
2584 cris_alu_m_alloc_temps(t);
2585 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2586 cris_cc_mask(dc, 0);
2587 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2588 do_postinc(dc, memsize);
2589 cris_alu_m_free_temps(t);
2593 static unsigned int dec_bound_m(DisasContext *dc)
2596 int memsize = memsize_zz(dc);
2598 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2599 memsize_char(memsize),
2600 dc->op1, dc->postinc ? "+]" : "]",
2603 l[0] = tcg_temp_local_new();
2604 l[1] = tcg_temp_local_new();
2605 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2606 cris_cc_mask(dc, CC_MASK_NZ);
2607 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2608 do_postinc(dc, memsize);
2609 tcg_temp_free(l[0]);
2610 tcg_temp_free(l[1]);
2614 static unsigned int dec_addc_mr(DisasContext *dc)
2618 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2619 dc->op1, dc->postinc ? "+]" : "]",
2622 cris_evaluate_flags(dc);
2624 /* Set for this insn. */
2625 dc->flagx_known = 1;
2626 dc->flags_x = X_FLAG;
2628 cris_alu_m_alloc_temps(t);
2629 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2630 cris_cc_mask(dc, CC_MASK_NZVC);
2631 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2633 cris_alu_m_free_temps(t);
2637 static unsigned int dec_sub_m(DisasContext *dc)
2640 int memsize = memsize_zz(dc);
2642 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2643 memsize_char(memsize),
2644 dc->op1, dc->postinc ? "+]" : "]",
2645 dc->op2, dc->ir, dc->zzsize));
2647 cris_alu_m_alloc_temps(t);
2648 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2649 cris_cc_mask(dc, CC_MASK_NZVC);
2650 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2651 do_postinc(dc, memsize);
2652 cris_alu_m_free_temps(t);
2656 static unsigned int dec_or_m(DisasContext *dc)
2659 int memsize = memsize_zz(dc);
2661 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2662 memsize_char(memsize),
2663 dc->op1, dc->postinc ? "+]" : "]",
2666 cris_alu_m_alloc_temps(t);
2667 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2668 cris_cc_mask(dc, CC_MASK_NZ);
2669 cris_alu(dc, CC_OP_OR,
2670 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2671 do_postinc(dc, memsize);
2672 cris_alu_m_free_temps(t);
2676 static unsigned int dec_move_mp(DisasContext *dc)
2679 int memsize = memsize_zz(dc);
2682 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2683 memsize_char(memsize),
2685 dc->postinc ? "+]" : "]",
2688 cris_alu_m_alloc_temps(t);
2689 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2690 cris_cc_mask(dc, 0);
2691 if (dc->op2 == PR_CCS) {
2692 cris_evaluate_flags(dc);
2693 if (dc->tb_flags & U_FLAG) {
2694 /* User space is not allowed to touch all flags. */
2695 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2696 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2697 tcg_gen_or_tl(t[1], t[0], t[1]);
2701 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2703 do_postinc(dc, memsize);
2704 cris_alu_m_free_temps(t);
2708 static unsigned int dec_move_pm(DisasContext *dc)
2713 memsize = preg_sizes[dc->op2];
2715 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2716 memsize_char(memsize),
2717 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2719 /* prepare store. Address in T0, value in T1. */
2720 if (dc->op2 == PR_CCS)
2721 cris_evaluate_flags(dc);
2722 t0 = tcg_temp_new();
2723 t_gen_mov_TN_preg(t0, dc->op2);
2724 cris_flush_cc_state(dc);
2725 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2728 cris_cc_mask(dc, 0);
2730 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2734 static unsigned int dec_movem_mr(DisasContext *dc)
2740 int nr = dc->op2 + 1;
2742 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2743 dc->postinc ? "+]" : "]", dc->op2));
2745 addr = tcg_temp_new();
2746 /* There are probably better ways of doing this. */
2747 cris_flush_cc_state(dc);
2748 for (i = 0; i < (nr >> 1); i++) {
2749 tmp[i] = tcg_temp_new_i64();
2750 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2751 gen_load64(dc, tmp[i], addr);
2754 tmp32 = tcg_temp_new_i32();
2755 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2756 gen_load(dc, tmp32, addr, 4, 0);
2758 tcg_temp_free(addr);
2760 for (i = 0; i < (nr >> 1); i++) {
2761 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2762 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2763 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2764 tcg_temp_free_i64(tmp[i]);
2767 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2768 tcg_temp_free(tmp32);
2771 /* writeback the updated pointer value. */
2773 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2775 /* gen_load might want to evaluate the previous insns flags. */
2776 cris_cc_mask(dc, 0);
2780 static unsigned int dec_movem_rm(DisasContext *dc)
2786 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2787 dc->postinc ? "+]" : "]"));
2789 cris_flush_cc_state(dc);
2791 tmp = tcg_temp_new();
2792 addr = tcg_temp_new();
2793 tcg_gen_movi_tl(tmp, 4);
2794 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2795 for (i = 0; i <= dc->op2; i++) {
2796 /* Displace addr. */
2797 /* Perform the store. */
2798 gen_store(dc, addr, cpu_R[i], 4);
2799 tcg_gen_add_tl(addr, addr, tmp);
2802 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2803 cris_cc_mask(dc, 0);
2805 tcg_temp_free(addr);
2809 static unsigned int dec_move_rm(DisasContext *dc)
2813 memsize = memsize_zz(dc);
2815 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2816 memsize, dc->op2, dc->op1));
2818 /* prepare store. */
2819 cris_flush_cc_state(dc);
2820 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2823 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2824 cris_cc_mask(dc, 0);
2828 static unsigned int dec_lapcq(DisasContext *dc)
2830 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2831 dc->pc + dc->op1*2, dc->op2));
2832 cris_cc_mask(dc, 0);
2833 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2837 static unsigned int dec_lapc_im(DisasContext *dc)
2845 cris_cc_mask(dc, 0);
2846 imm = ldl_code(dc->pc + 2);
2847 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2851 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2855 /* Jump to special reg. */
2856 static unsigned int dec_jump_p(DisasContext *dc)
2858 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2860 if (dc->op2 == PR_CCS)
2861 cris_evaluate_flags(dc);
2862 t_gen_mov_TN_preg(env_btarget, dc->op2);
2863 /* rete will often have low bit set to indicate delayslot. */
2864 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2865 cris_cc_mask(dc, 0);
2866 cris_prepare_jmp(dc, JMP_INDIRECT);
2870 /* Jump and save. */
2871 static unsigned int dec_jas_r(DisasContext *dc)
2873 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2874 cris_cc_mask(dc, 0);
2875 /* Store the return address in Pd. */
2876 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2879 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2881 cris_prepare_jmp(dc, JMP_INDIRECT);
2885 static unsigned int dec_jas_im(DisasContext *dc)
2889 imm = ldl_code(dc->pc + 2);
2891 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2892 cris_cc_mask(dc, 0);
2893 /* Store the return address in Pd. */
2894 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2897 cris_prepare_jmp(dc, JMP_DIRECT);
2901 static unsigned int dec_jasc_im(DisasContext *dc)
2905 imm = ldl_code(dc->pc + 2);
2907 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2908 cris_cc_mask(dc, 0);
2909 /* Store the return address in Pd. */
2910 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2913 cris_prepare_jmp(dc, JMP_DIRECT);
2917 static unsigned int dec_jasc_r(DisasContext *dc)
2919 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2920 cris_cc_mask(dc, 0);
2921 /* Store the return address in Pd. */
2922 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2923 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2924 cris_prepare_jmp(dc, JMP_INDIRECT);
2928 static unsigned int dec_bcc_im(DisasContext *dc)
2931 uint32_t cond = dc->op2;
2933 offset = ldsw_code(dc->pc + 2);
2935 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2936 cc_name(cond), offset,
2937 dc->pc, dc->pc + offset));
2939 cris_cc_mask(dc, 0);
2940 /* op2 holds the condition-code. */
2941 cris_prepare_cc_branch (dc, offset, cond);
2945 static unsigned int dec_bas_im(DisasContext *dc)
2950 simm = ldl_code(dc->pc + 2);
2952 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2953 cris_cc_mask(dc, 0);
2954 /* Store the return address in Pd. */
2955 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2957 dc->jmp_pc = dc->pc + simm;
2958 cris_prepare_jmp(dc, JMP_DIRECT);
2962 static unsigned int dec_basc_im(DisasContext *dc)
2965 simm = ldl_code(dc->pc + 2);
2967 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2968 cris_cc_mask(dc, 0);
2969 /* Store the return address in Pd. */
2970 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2972 dc->jmp_pc = dc->pc + simm;
2973 cris_prepare_jmp(dc, JMP_DIRECT);
2977 static unsigned int dec_rfe_etc(DisasContext *dc)
2979 cris_cc_mask(dc, 0);
2981 if (dc->op2 == 15) /* ignore halt. */
2984 switch (dc->op2 & 7) {
2987 DIS(fprintf(logfile, "rfe\n"));
2988 cris_evaluate_flags(dc);
2990 dc->is_jmp = DISAS_UPDATE;
2994 DIS(fprintf(logfile, "rfn\n"));
2995 cris_evaluate_flags(dc);
2997 dc->is_jmp = DISAS_UPDATE;
3000 DIS(fprintf(logfile, "break %d\n", dc->op1));
3001 cris_evaluate_flags (dc);
3003 tcg_gen_movi_tl(env_pc, dc->pc + 2);
3005 /* Breaks start at 16 in the exception vector. */
3006 t_gen_mov_env_TN(trap_vector,
3007 tcg_const_tl(dc->op1 + 16));
3008 t_gen_raise_exception(EXCP_BREAK);
3009 dc->is_jmp = DISAS_UPDATE;
3012 printf ("op2=%x\n", dc->op2);
3020 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
3025 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
3030 static unsigned int dec_null(DisasContext *dc)
3032 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
3033 dc->pc, dc->opcode, dc->op1, dc->op2);
3039 static struct decoder_info {
3044 unsigned int (*dec)(DisasContext *dc);
3046 /* Order matters here. */
3047 {DEC_MOVEQ, dec_moveq},
3048 {DEC_BTSTQ, dec_btstq},
3049 {DEC_CMPQ, dec_cmpq},
3050 {DEC_ADDOQ, dec_addoq},
3051 {DEC_ADDQ, dec_addq},
3052 {DEC_SUBQ, dec_subq},
3053 {DEC_ANDQ, dec_andq},
3055 {DEC_ASRQ, dec_asrq},
3056 {DEC_LSLQ, dec_lslq},
3057 {DEC_LSRQ, dec_lsrq},
3058 {DEC_BCCQ, dec_bccq},
3060 {DEC_BCC_IM, dec_bcc_im},
3061 {DEC_JAS_IM, dec_jas_im},
3062 {DEC_JAS_R, dec_jas_r},
3063 {DEC_JASC_IM, dec_jasc_im},
3064 {DEC_JASC_R, dec_jasc_r},
3065 {DEC_BAS_IM, dec_bas_im},
3066 {DEC_BASC_IM, dec_basc_im},
3067 {DEC_JUMP_P, dec_jump_p},
3068 {DEC_LAPC_IM, dec_lapc_im},
3069 {DEC_LAPCQ, dec_lapcq},
3071 {DEC_RFE_ETC, dec_rfe_etc},
3072 {DEC_ADDC_MR, dec_addc_mr},
3074 {DEC_MOVE_MP, dec_move_mp},
3075 {DEC_MOVE_PM, dec_move_pm},
3076 {DEC_MOVEM_MR, dec_movem_mr},
3077 {DEC_MOVEM_RM, dec_movem_rm},
3078 {DEC_MOVE_PR, dec_move_pr},
3079 {DEC_SCC_R, dec_scc_r},
3080 {DEC_SETF, dec_setclrf},
3081 {DEC_CLEARF, dec_setclrf},
3083 {DEC_MOVE_SR, dec_move_sr},
3084 {DEC_MOVE_RP, dec_move_rp},
3085 {DEC_SWAP_R, dec_swap_r},
3086 {DEC_ABS_R, dec_abs_r},
3087 {DEC_LZ_R, dec_lz_r},
3088 {DEC_MOVE_RS, dec_move_rs},
3089 {DEC_BTST_R, dec_btst_r},
3090 {DEC_ADDC_R, dec_addc_r},
3092 {DEC_DSTEP_R, dec_dstep_r},
3093 {DEC_XOR_R, dec_xor_r},
3094 {DEC_MCP_R, dec_mcp_r},
3095 {DEC_CMP_R, dec_cmp_r},
3097 {DEC_ADDI_R, dec_addi_r},
3098 {DEC_ADDI_ACR, dec_addi_acr},
3100 {DEC_ADD_R, dec_add_r},
3101 {DEC_SUB_R, dec_sub_r},
3103 {DEC_ADDU_R, dec_addu_r},
3104 {DEC_ADDS_R, dec_adds_r},
3105 {DEC_SUBU_R, dec_subu_r},
3106 {DEC_SUBS_R, dec_subs_r},
3107 {DEC_LSL_R, dec_lsl_r},
3109 {DEC_AND_R, dec_and_r},
3110 {DEC_OR_R, dec_or_r},
3111 {DEC_BOUND_R, dec_bound_r},
3112 {DEC_ASR_R, dec_asr_r},
3113 {DEC_LSR_R, dec_lsr_r},
3115 {DEC_MOVU_R, dec_movu_r},
3116 {DEC_MOVS_R, dec_movs_r},
3117 {DEC_NEG_R, dec_neg_r},
3118 {DEC_MOVE_R, dec_move_r},
3120 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3121 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3123 {DEC_MULS_R, dec_muls_r},
3124 {DEC_MULU_R, dec_mulu_r},
3126 {DEC_ADDU_M, dec_addu_m},
3127 {DEC_ADDS_M, dec_adds_m},
3128 {DEC_SUBU_M, dec_subu_m},
3129 {DEC_SUBS_M, dec_subs_m},
3131 {DEC_CMPU_M, dec_cmpu_m},
3132 {DEC_CMPS_M, dec_cmps_m},
3133 {DEC_MOVU_M, dec_movu_m},
3134 {DEC_MOVS_M, dec_movs_m},
3136 {DEC_CMP_M, dec_cmp_m},
3137 {DEC_ADDO_M, dec_addo_m},
3138 {DEC_BOUND_M, dec_bound_m},
3139 {DEC_ADD_M, dec_add_m},
3140 {DEC_SUB_M, dec_sub_m},
3141 {DEC_AND_M, dec_and_m},
3142 {DEC_OR_M, dec_or_m},
3143 {DEC_MOVE_RM, dec_move_rm},
3144 {DEC_TEST_M, dec_test_m},
3145 {DEC_MOVE_MR, dec_move_mr},
3150 static inline unsigned int
3151 cris_decoder(DisasContext *dc)
3153 unsigned int insn_len = 2;
3156 if (unlikely(loglevel & CPU_LOG_TB_OP))
3157 tcg_gen_debug_insn_start(dc->pc);
3159 /* Load a halfword onto the instruction register. */
3160 dc->ir = lduw_code(dc->pc);
3162 /* Now decode it. */
3163 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3164 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3165 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3166 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3167 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3168 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3170 /* Large switch for all insns. */
3171 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3172 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3174 insn_len = decinfo[i].dec(dc);
3179 #if !defined(CONFIG_USER_ONLY)
3180 /* Single-stepping ? */
3181 if (dc->tb_flags & S_FLAG) {
3184 l1 = gen_new_label();
3185 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3186 /* We treat SPC as a break with an odd trap vector. */
3187 cris_evaluate_flags (dc);
3188 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3189 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3190 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3191 t_gen_raise_exception(EXCP_BREAK);
3198 static void check_breakpoint(CPUState *env, DisasContext *dc)
3202 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
3203 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
3204 if (bp->pc == dc->pc) {
3205 cris_evaluate_flags (dc);
3206 tcg_gen_movi_tl(env_pc, dc->pc);
3207 t_gen_raise_exception(EXCP_DEBUG);
3208 dc->is_jmp = DISAS_UPDATE;
3216 * Delay slots on QEMU/CRIS.
3218 * If an exception hits on a delayslot, the core will let ERP (the Exception
3219 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3220 * to give SW a hint that the exception actually hit on the dslot.
3222 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3223 * the core and any jmp to an odd addresses will mask off that lsb. It is
3224 * simply there to let sw know there was an exception on a dslot.
3226 * When the software returns from an exception, the branch will re-execute.
3227 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3228 * and the branch and delayslot dont share pages.
3230 * The TB contaning the branch insn will set up env->btarget and evaluate
3231 * env->btaken. When the translation loop exits we will note that the branch
3232 * sequence is broken and let env->dslot be the size of the branch insn (those
3235 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3236 * set). It will also expect to have env->dslot setup with the size of the
3237 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3238 * will execute the dslot and take the branch, either to btarget or just one
3241 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3242 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3243 * branch and set lsb). Then env->dslot gets cleared so that the exception
3244 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3245 * masked off and we will reexecute the branch insn.
3249 /* generate intermediate code for basic block 'tb'. */
3251 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3254 uint16_t *gen_opc_end;
3256 unsigned int insn_len;
3258 struct DisasContext ctx;
3259 struct DisasContext *dc = &ctx;
3260 uint32_t next_page_start;
3268 /* Odd PC indicates that branch is rexecuting due to exception in the
3269 * delayslot, like in real hw.
3271 pc_start = tb->pc & ~1;
3275 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3277 dc->is_jmp = DISAS_NEXT;
3280 dc->singlestep_enabled = env->singlestep_enabled;
3281 dc->flags_uptodate = 1;
3282 dc->flagx_known = 1;
3283 dc->flags_x = tb->flags & X_FLAG;
3284 dc->cc_x_uptodate = 0;
3288 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3289 dc->cc_size_uptodate = -1;
3291 /* Decode TB flags. */
3292 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3293 dc->delayed_branch = !!(tb->flags & 7);
3294 if (dc->delayed_branch)
3295 dc->jmp = JMP_INDIRECT;
3297 dc->jmp = JMP_NOJMP;
3299 dc->cpustate_changed = 0;
3301 if (loglevel & CPU_LOG_TB_IN_ASM) {
3303 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3309 search_pc, dc->pc, dc->ppc,
3310 (unsigned long long)tb->flags,
3311 env->btarget, (unsigned)tb->flags & 7,
3313 env->pregs[PR_PID], env->pregs[PR_USP],
3314 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3315 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3316 env->regs[8], env->regs[9],
3317 env->regs[10], env->regs[11],
3318 env->regs[12], env->regs[13],
3319 env->regs[14], env->regs[15]);
3320 fprintf(logfile, "--------------\n");
3321 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3324 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3327 max_insns = tb->cflags & CF_COUNT_MASK;
3329 max_insns = CF_COUNT_MASK;
3334 check_breakpoint(env, dc);
3337 j = gen_opc_ptr - gen_opc_buf;
3341 gen_opc_instr_start[lj++] = 0;
3343 if (dc->delayed_branch == 1)
3344 gen_opc_pc[lj] = dc->ppc | 1;
3346 gen_opc_pc[lj] = dc->pc;
3347 gen_opc_instr_start[lj] = 1;
3348 gen_opc_icount[lj] = num_insns;
3352 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3354 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3358 insn_len = cris_decoder(dc);
3362 cris_clear_x_flag(dc);
3365 /* Check for delayed branches here. If we do it before
3366 actually generating any host code, the simulator will just
3367 loop doing nothing for on this program location. */
3368 if (dc->delayed_branch) {
3369 dc->delayed_branch--;
3370 if (dc->delayed_branch == 0)
3373 t_gen_mov_env_TN(dslot,
3375 if (dc->jmp == JMP_DIRECT) {
3376 dc->is_jmp = DISAS_NEXT;
3378 t_gen_cc_jmp(env_btarget,
3379 tcg_const_tl(dc->pc));
3380 dc->is_jmp = DISAS_JUMP;
3386 /* If we are rexecuting a branch due to exceptions on
3387 delay slots dont break. */
3388 if (!(tb->pc & 1) && env->singlestep_enabled)
3390 } while (!dc->is_jmp && !dc->cpustate_changed
3391 && gen_opc_ptr < gen_opc_end
3392 && (dc->pc < next_page_start)
3393 && num_insns < max_insns);
3396 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3399 if (tb->cflags & CF_LAST_IO)
3401 /* Force an update if the per-tb cpu state has changed. */
3402 if (dc->is_jmp == DISAS_NEXT
3403 && (dc->cpustate_changed || !dc->flagx_known
3404 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3405 dc->is_jmp = DISAS_UPDATE;
3406 tcg_gen_movi_tl(env_pc, npc);
3408 /* Broken branch+delayslot sequence. */
3409 if (dc->delayed_branch == 1) {
3410 /* Set env->dslot to the size of the branch insn. */
3411 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3412 cris_store_direct_jmp(dc);
3415 cris_evaluate_flags (dc);
3417 if (unlikely(env->singlestep_enabled)) {
3418 if (dc->is_jmp == DISAS_NEXT)
3419 tcg_gen_movi_tl(env_pc, npc);
3420 t_gen_raise_exception(EXCP_DEBUG);
3422 switch(dc->is_jmp) {
3424 gen_goto_tb(dc, 1, npc);
3429 /* indicate that the hash table must be used
3430 to find the next TB */
3435 /* nothing more to generate */
3439 gen_icount_end(tb, num_insns);
3440 *gen_opc_ptr = INDEX_op_end;
3442 j = gen_opc_ptr - gen_opc_buf;
3445 gen_opc_instr_start[lj++] = 0;
3447 tb->size = dc->pc - pc_start;
3448 tb->icount = num_insns;
3453 if (loglevel & CPU_LOG_TB_IN_ASM) {
3454 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3455 fprintf(logfile, "\nisize=%d osize=%zd\n",
3456 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3462 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3464 gen_intermediate_code_internal(env, tb, 0);
3467 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3469 gen_intermediate_code_internal(env, tb, 1);
3472 void cpu_dump_state (CPUState *env, FILE *f,
3473 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3482 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3483 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3484 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3486 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3489 for (i = 0; i < 16; i++) {
3490 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3491 if ((i + 1) % 4 == 0)
3492 cpu_fprintf(f, "\n");
3494 cpu_fprintf(f, "\nspecial regs:\n");
3495 for (i = 0; i < 16; i++) {
3496 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3497 if ((i + 1) % 4 == 0)
3498 cpu_fprintf(f, "\n");
3500 srs = env->pregs[PR_SRS];
3501 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3503 for (i = 0; i < 16; i++) {
3504 cpu_fprintf(f, "s%2.2d=%8.8x ",
3505 i, env->sregs[srs][i]);
3506 if ((i + 1) % 4 == 0)
3507 cpu_fprintf(f, "\n");
3510 cpu_fprintf(f, "\n\n");
3514 CPUCRISState *cpu_cris_init (const char *cpu_model)
3517 static int tcg_initialized = 0;
3520 env = qemu_mallocz(sizeof(CPUCRISState));
3527 if (tcg_initialized)
3530 tcg_initialized = 1;
3532 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3533 cc_x = tcg_global_mem_new(TCG_AREG0,
3534 offsetof(CPUState, cc_x), "cc_x");
3535 cc_src = tcg_global_mem_new(TCG_AREG0,
3536 offsetof(CPUState, cc_src), "cc_src");
3537 cc_dest = tcg_global_mem_new(TCG_AREG0,
3538 offsetof(CPUState, cc_dest),
3540 cc_result = tcg_global_mem_new(TCG_AREG0,
3541 offsetof(CPUState, cc_result),
3543 cc_op = tcg_global_mem_new(TCG_AREG0,
3544 offsetof(CPUState, cc_op), "cc_op");
3545 cc_size = tcg_global_mem_new(TCG_AREG0,
3546 offsetof(CPUState, cc_size),
3548 cc_mask = tcg_global_mem_new(TCG_AREG0,
3549 offsetof(CPUState, cc_mask),
3552 env_pc = tcg_global_mem_new(TCG_AREG0,
3553 offsetof(CPUState, pc),
3555 env_btarget = tcg_global_mem_new(TCG_AREG0,
3556 offsetof(CPUState, btarget),
3558 env_btaken = tcg_global_mem_new(TCG_AREG0,
3559 offsetof(CPUState, btaken),
3561 for (i = 0; i < 16; i++) {
3562 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3563 offsetof(CPUState, regs[i]),
3566 for (i = 0; i < 16; i++) {
3567 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3568 offsetof(CPUState, pregs[i]),
3572 #define GEN_HELPER 2
3578 void cpu_reset (CPUCRISState *env)
3580 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3583 env->pregs[PR_VR] = 32;
3584 #if defined(CONFIG_USER_ONLY)
3585 /* start in user mode with interrupts enabled. */
3586 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3588 env->pregs[PR_CCS] = 0;
3592 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3593 unsigned long searched_pc, int pc_pos, void *puc)
3595 env->pc = gen_opc_pc[pc_pos];