2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
96 unsigned int zsize, zzsize;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
108 int clear_x; /* Clear x after this insn? */
110 int user; /* user or kernel mode. */
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
130 cris_prepare_jmp (dc, 0x70000000 + line);
133 const char *regnames[] =
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
140 const char *pregnames[] =
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
148 /* We need this table to handle preg-moves with implicit width. */
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
220 tcg_gen_helper_0_0(helper_tlb_flush);
222 tcg_gen_mov_tl(cpu_PR[r], tn);
226 static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
228 tcg_gen_movi_tl(tn, val);
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
310 /* 32bit branch-free binary search for counting leading zeros. */
311 static void t_gen_lz_i32(TCGv d, TCGv x)
315 y = tcg_temp_new(TCG_TYPE_I32);
316 m = tcg_temp_new(TCG_TYPE_I32);
317 n = tcg_temp_new(TCG_TYPE_I32);
320 tcg_gen_shri_i32(y, x, 16);
321 tcg_gen_sub_i32(y, tcg_const_i32(0), y);
323 /* m = (y >> 16) & 16 */
324 tcg_gen_sari_i32(m, y, 16);
325 tcg_gen_andi_i32(m, m, 16);
328 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
330 tcg_gen_shr_i32(x, x, m);
333 tcg_gen_subi_i32(y, x, 0x100);
334 /* m = (y >> 16) & 8 */
335 tcg_gen_sari_i32(m, y, 16);
336 tcg_gen_andi_i32(m, m, 8);
338 tcg_gen_add_i32(n, n, m);
340 tcg_gen_shl_i32(x, x, m);
343 tcg_gen_subi_i32(y, x, 0x1000);
344 /* m = (y >> 16) & 4 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 4);
348 tcg_gen_add_i32(n, n, m);
350 tcg_gen_shl_i32(x, x, m);
353 tcg_gen_subi_i32(y, x, 0x4000);
354 /* m = (y >> 16) & 2 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 2);
358 tcg_gen_add_i32(n, n, m);
360 tcg_gen_shl_i32(x, x, m);
363 tcg_gen_shri_i32(y, x, 14);
364 /* m = y & ~(y >> 1) */
365 tcg_gen_sari_i32(m, y, 1);
366 tcg_gen_xori_i32(m, m, 0xffffffff);
367 tcg_gen_and_i32(m, m, y);
370 tcg_gen_addi_i32(d, n, 2);
371 tcg_gen_sub_i32(d, d, m);
373 tcg_gen_discard_i32(y);
374 tcg_gen_discard_i32(m);
375 tcg_gen_discard_i32(n);
378 /* Extended arithmetics on CRIS. */
379 static inline void t_gen_add_flag(TCGv d, int flag)
383 c = tcg_temp_new(TCG_TYPE_TL);
384 t_gen_mov_TN_preg(c, PR_CCS);
385 /* Propagate carry into d. */
386 tcg_gen_andi_tl(c, c, 1 << flag);
388 tcg_gen_shri_tl(c, c, flag);
389 tcg_gen_add_tl(d, d, c);
390 tcg_gen_discard_tl(c);
393 static inline void t_gen_addx_carry(TCGv d)
397 x = tcg_temp_new(TCG_TYPE_TL);
398 c = tcg_temp_new(TCG_TYPE_TL);
399 t_gen_mov_TN_preg(x, PR_CCS);
400 tcg_gen_mov_tl(c, x);
402 /* Propagate carry into d if X is set. Branch free. */
403 tcg_gen_andi_tl(c, c, C_FLAG);
404 tcg_gen_andi_tl(x, x, X_FLAG);
405 tcg_gen_shri_tl(x, x, 4);
407 tcg_gen_and_tl(x, x, c);
408 tcg_gen_add_tl(d, d, x);
409 tcg_gen_discard_tl(x);
410 tcg_gen_discard_tl(c);
413 static inline void t_gen_subx_carry(TCGv d)
417 x = tcg_temp_new(TCG_TYPE_TL);
418 c = tcg_temp_new(TCG_TYPE_TL);
419 t_gen_mov_TN_preg(x, PR_CCS);
420 tcg_gen_mov_tl(c, x);
422 /* Propagate carry into d if X is set. Branch free. */
423 tcg_gen_andi_tl(c, c, C_FLAG);
424 tcg_gen_andi_tl(x, x, X_FLAG);
425 tcg_gen_shri_tl(x, x, 4);
427 tcg_gen_and_tl(x, x, c);
428 tcg_gen_sub_tl(d, d, x);
429 tcg_gen_discard_tl(x);
430 tcg_gen_discard_tl(c);
433 /* Swap the two bytes within each half word of the s operand.
434 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
435 static inline void t_gen_swapb(TCGv d, TCGv s)
439 t = tcg_temp_new(TCG_TYPE_TL);
440 org_s = tcg_temp_new(TCG_TYPE_TL);
442 /* d and s may refer to the same object. */
443 tcg_gen_mov_tl(org_s, s);
444 tcg_gen_shli_tl(t, org_s, 8);
445 tcg_gen_andi_tl(d, t, 0xff00ff00);
446 tcg_gen_shri_tl(t, org_s, 8);
447 tcg_gen_andi_tl(t, t, 0x00ff00ff);
448 tcg_gen_or_tl(d, d, t);
449 tcg_gen_discard_tl(t);
450 tcg_gen_discard_tl(org_s);
453 /* Swap the halfwords of the s operand. */
454 static inline void t_gen_swapw(TCGv d, TCGv s)
457 /* d and s refer the same object. */
458 t = tcg_temp_new(TCG_TYPE_TL);
459 tcg_gen_mov_tl(t, s);
460 tcg_gen_shli_tl(d, t, 16);
461 tcg_gen_shri_tl(t, t, 16);
462 tcg_gen_or_tl(d, d, t);
463 tcg_gen_discard_tl(t);
466 /* Reverse the within each byte.
467 T0 = (((T0 << 7) & 0x80808080) |
468 ((T0 << 5) & 0x40404040) |
469 ((T0 << 3) & 0x20202020) |
470 ((T0 << 1) & 0x10101010) |
471 ((T0 >> 1) & 0x08080808) |
472 ((T0 >> 3) & 0x04040404) |
473 ((T0 >> 5) & 0x02020202) |
474 ((T0 >> 7) & 0x01010101));
476 static inline void t_gen_swapr(TCGv d, TCGv s)
479 int shift; /* LSL when positive, LSR when negative. */
494 /* d and s refer the same object. */
495 t = tcg_temp_new(TCG_TYPE_TL);
496 org_s = tcg_temp_new(TCG_TYPE_TL);
497 tcg_gen_mov_tl(org_s, s);
499 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
500 tcg_gen_andi_tl(d, t, bitrev[0].mask);
501 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
502 if (bitrev[i].shift >= 0) {
503 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
505 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
507 tcg_gen_andi_tl(t, t, bitrev[i].mask);
508 tcg_gen_or_tl(d, d, t);
510 tcg_gen_discard_tl(t);
511 tcg_gen_discard_tl(org_s);
514 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
516 TranslationBlock *tb;
518 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
520 tcg_gen_movi_tl(env_pc, dest);
521 tcg_gen_exit_tb((long)tb + n);
523 tcg_gen_mov_tl(env_pc, cpu_T[0]);
528 /* Sign extend at translation time. */
529 static int sign_extend(unsigned int val, unsigned int width)
541 static inline void cris_clear_x_flag(DisasContext *dc)
544 || (dc->flagx_live && dc->flags_x)
545 || dc->cc_op != CC_OP_FLAGS)
546 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
551 static void cris_evaluate_flags(DisasContext *dc)
553 if (!dc->flags_live) {
554 tcg_gen_movi_tl(cc_op, dc->cc_op);
555 tcg_gen_movi_tl(cc_size, dc->cc_size);
556 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
561 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
564 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
567 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
573 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
576 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
579 tcg_gen_helper_0_0(helper_evaluate_flags);
591 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
594 tcg_gen_helper_0_0(helper_evaluate_flags);
604 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
608 /* Check if we need to evaluate the condition codes due to
610 ovl = (dc->cc_mask ^ mask) & ~mask;
612 /* TODO: optimize this case. It trigs all the time. */
613 cris_evaluate_flags (dc);
624 static void cris_update_cc_op(DisasContext *dc, int op, int size)
631 /* op is the operation.
632 T0, T1 are the operands.
633 dst is the destination reg.
635 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
639 cris_update_cc_op(dc, op, size);
640 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
642 /* FIXME: This shouldn't be needed. But we don't pass the
643 tests without it. Investigate. */
644 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
645 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
648 /* Emit the ALU insns. */
652 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
653 /* Extended arithmetics. */
654 t_gen_addx_carry(cpu_T[0]);
657 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
658 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
661 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
662 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
665 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
666 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
667 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
668 /* CRIS flag evaluation needs ~src. */
669 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
671 /* Extended arithmetics. */
672 t_gen_subx_carry(cpu_T[0]);
675 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
678 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
681 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
684 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
687 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
690 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
693 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
696 /* Hopefully the TCG backend recognizes this pattern
697 and makes a real neg out of it. */
698 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
699 /* Extended arithmetics. */
700 t_gen_subx_carry(cpu_T[0]);
703 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
712 mof = tcg_temp_new(TCG_TYPE_TL);
713 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
714 t_gen_mov_preg_TN(PR_MOF, mof);
715 tcg_gen_discard_tl(mof);
721 mof = tcg_temp_new(TCG_TYPE_TL);
722 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
723 t_gen_mov_preg_TN(PR_MOF, mof);
724 tcg_gen_discard_tl(mof);
728 gen_op_dstep_T0_T1();
733 l1 = gen_new_label();
734 tcg_gen_brcond_tl(TCG_COND_LEU,
735 cpu_T[0], cpu_T[1], l1);
736 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
741 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
742 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
743 /* CRIS flag evaluation needs ~src. */
744 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
745 /* CRIS flag evaluation needs ~src. */
746 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
748 /* Extended arithmetics. */
749 t_gen_subx_carry(cpu_T[0]);
753 fprintf (logfile, "illegal ALU op.\n");
759 tcg_gen_mov_tl(cc_src, cpu_T[1]);
762 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
764 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
769 t_gen_mov_reg_TN(rd, cpu_T[0]);
771 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
772 t_gen_mov_TN_reg(cpu_T[0], rd);
774 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
776 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
777 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
778 t_gen_mov_reg_TN(rd, cpu_T[0]);
779 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
783 tcg_gen_mov_tl(cc_result, cpu_T[0]);
786 /* TODO: Optimize this. */
788 cris_evaluate_flags(dc);
792 static int arith_cc(DisasContext *dc)
796 case CC_OP_ADD: return 1;
797 case CC_OP_SUB: return 1;
798 case CC_OP_LSL: return 1;
799 case CC_OP_LSR: return 1;
800 case CC_OP_ASR: return 1;
801 case CC_OP_CMP: return 1;
809 static void gen_tst_cc (DisasContext *dc, int cond)
813 /* TODO: optimize more condition codes. */
814 arith_opt = arith_cc(dc) && !dc->flags_live;
818 gen_op_tst_cc_eq_fast ();
820 cris_evaluate_flags(dc);
826 gen_op_tst_cc_ne_fast ();
828 cris_evaluate_flags(dc);
833 cris_evaluate_flags(dc);
837 cris_evaluate_flags(dc);
841 cris_evaluate_flags(dc);
845 cris_evaluate_flags(dc);
850 gen_op_tst_cc_pl_fast ();
852 cris_evaluate_flags(dc);
858 gen_op_tst_cc_mi_fast ();
860 cris_evaluate_flags(dc);
865 cris_evaluate_flags(dc);
869 cris_evaluate_flags(dc);
873 cris_evaluate_flags(dc);
877 cris_evaluate_flags(dc);
881 cris_evaluate_flags(dc);
885 cris_evaluate_flags(dc);
889 cris_evaluate_flags(dc);
893 cris_evaluate_flags(dc);
894 gen_op_movl_T0_im (1);
902 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
904 /* This helps us re-schedule the micro-code to insns in delay-slots
905 before the actual jump. */
906 dc->delayed_branch = 2;
907 dc->delayed_pc = dc->pc + offset;
911 gen_tst_cc (dc, cond);
912 gen_op_evaluate_bcc ();
914 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
918 /* Dynamic jumps, when the dest is in a live reg for example. */
919 void cris_prepare_dyn_jmp (DisasContext *dc)
921 /* This helps us re-schedule the micro-code to insns in delay-slots
922 before the actual jump. */
923 dc->delayed_branch = 2;
928 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
930 /* This helps us re-schedule the micro-code to insns in delay-slots
931 before the actual jump. */
932 dc->delayed_branch = 2;
933 dc->delayed_pc = dst;
938 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
939 unsigned int size, int sign)
941 int mem_index = cpu_mmu_index(dc->env);
943 /* FIXME: qemu_ld does not act as a barrier? */
944 tcg_gen_helper_0_0(helper_dummy);
945 cris_evaluate_flags(dc);
948 tcg_gen_qemu_ld8s(dst, addr, mem_index);
950 tcg_gen_qemu_ld8u(dst, addr, mem_index);
952 else if (size == 2) {
954 tcg_gen_qemu_ld16s(dst, addr, mem_index);
956 tcg_gen_qemu_ld16u(dst, addr, mem_index);
959 tcg_gen_qemu_ld32s(dst, addr, mem_index);
963 void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
965 int mem_index = cpu_mmu_index(dc->env);
967 /* FIXME: qemu_st does not act as a barrier? */
968 tcg_gen_helper_0_0(helper_dummy);
969 cris_evaluate_flags(dc);
971 /* Remember, operands are flipped. CRIS has reversed order. */
973 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
975 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
977 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
980 static inline void t_gen_sext(TCGv d, TCGv s, int size)
983 tcg_gen_ext8s_i32(d, s);
985 tcg_gen_ext16s_i32(d, s);
987 tcg_gen_mov_tl(d, s);
990 static inline void t_gen_zext(TCGv d, TCGv s, int size)
992 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
994 tcg_gen_andi_i32(d, s, 0xff);
996 tcg_gen_andi_i32(d, s, 0xffff);
998 tcg_gen_mov_tl(d, s);
1002 static char memsize_char(int size)
1006 case 1: return 'b'; break;
1007 case 2: return 'w'; break;
1008 case 4: return 'd'; break;
1016 static unsigned int memsize_z(DisasContext *dc)
1018 return dc->zsize + 1;
1021 static unsigned int memsize_zz(DisasContext *dc)
1032 static inline void do_postinc (DisasContext *dc, int size)
1035 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1039 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1040 int size, int s_ext)
1043 t_gen_sext(cpu_T[1], cpu_R[rs], size);
1045 t_gen_zext(cpu_T[1], cpu_R[rs], size);
1048 /* Prepare T0 and T1 for a register alu operation.
1049 s_ext decides if the operand1 should be sign-extended or zero-extended when
1051 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1052 int size, int s_ext)
1054 dec_prep_move_r(dc, rs, rd, size, s_ext);
1057 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1059 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1062 /* Prepare T0 and T1 for a memory + alu operation.
1063 s_ext decides if the operand1 should be sign-extended or zero-extended when
1065 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1067 unsigned int rs, rd;
1074 is_imm = rs == 15 && dc->postinc;
1076 /* Load [$rs] onto T1. */
1078 insn_len = 2 + memsize;
1082 imm = ldl_code(dc->pc + 2);
1085 imm = sign_extend(imm, (memsize * 8) - 1);
1093 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1094 imm, rd, s_ext, memsize));
1095 tcg_gen_movi_tl(cpu_T[1], imm);
1098 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1100 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1102 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1105 /* put dest in T0. */
1106 t_gen_mov_TN_reg(cpu_T[0], rd);
1111 static const char *cc_name(int cc)
1113 static char *cc_names[16] = {
1114 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1115 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1118 return cc_names[cc];
1122 /* Start of insn decoders. */
1124 static unsigned int dec_bccq(DisasContext *dc)
1128 uint32_t cond = dc->op2;
1131 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1132 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1135 offset |= sign << 8;
1137 offset = sign_extend(offset, 8);
1139 /* op2 holds the condition-code. */
1140 cris_cc_mask(dc, 0);
1141 cris_prepare_cc_branch (dc, offset, cond);
1144 static unsigned int dec_addoq(DisasContext *dc)
1148 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1149 imm = sign_extend(dc->op1, 7);
1151 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1152 cris_cc_mask(dc, 0);
1153 /* Fetch register operand, */
1154 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1157 static unsigned int dec_addq(DisasContext *dc)
1159 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1161 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1163 cris_cc_mask(dc, CC_MASK_NZVC);
1164 /* Fetch register operand, */
1165 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1166 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1167 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1170 static unsigned int dec_moveq(DisasContext *dc)
1174 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1175 imm = sign_extend(dc->op1, 5);
1176 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1178 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1181 static unsigned int dec_subq(DisasContext *dc)
1183 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1185 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1187 cris_cc_mask(dc, CC_MASK_NZVC);
1188 /* Fetch register operand, */
1189 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1190 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1191 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1194 static unsigned int dec_cmpq(DisasContext *dc)
1197 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1198 imm = sign_extend(dc->op1, 5);
1200 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1201 cris_cc_mask(dc, CC_MASK_NZVC);
1202 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1203 t_gen_mov_TN_im(cpu_T[1], imm);
1204 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1207 static unsigned int dec_andq(DisasContext *dc)
1210 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1211 imm = sign_extend(dc->op1, 5);
1213 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1214 cris_cc_mask(dc, CC_MASK_NZ);
1215 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1216 t_gen_mov_TN_im(cpu_T[1], imm);
1217 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1220 static unsigned int dec_orq(DisasContext *dc)
1223 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1224 imm = sign_extend(dc->op1, 5);
1225 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1226 cris_cc_mask(dc, CC_MASK_NZ);
1227 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1228 t_gen_mov_TN_im(cpu_T[1], imm);
1229 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1232 static unsigned int dec_btstq(DisasContext *dc)
1234 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1235 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1236 cris_cc_mask(dc, CC_MASK_NZ);
1237 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1238 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1239 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1241 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1242 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1246 static unsigned int dec_asrq(DisasContext *dc)
1248 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1249 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1250 cris_cc_mask(dc, CC_MASK_NZ);
1251 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1252 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1253 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1256 static unsigned int dec_lslq(DisasContext *dc)
1258 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1259 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1261 cris_cc_mask(dc, CC_MASK_NZ);
1262 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1263 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1264 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1267 static unsigned int dec_lsrq(DisasContext *dc)
1269 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1270 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1272 cris_cc_mask(dc, CC_MASK_NZ);
1273 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1274 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1275 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1279 static unsigned int dec_move_r(DisasContext *dc)
1281 int size = memsize_zz(dc);
1283 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1284 memsize_char(size), dc->op1, dc->op2));
1286 cris_cc_mask(dc, CC_MASK_NZ);
1287 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1288 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1292 static unsigned int dec_scc_r(DisasContext *dc)
1296 DIS(fprintf (logfile, "s%s $r%u\n",
1297 cc_name(cond), dc->op1));
1301 gen_tst_cc (dc, cond);
1302 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1305 tcg_gen_movi_tl(cpu_T[1], 1);
1307 cris_cc_mask(dc, 0);
1308 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1312 static unsigned int dec_and_r(DisasContext *dc)
1314 int size = memsize_zz(dc);
1316 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1317 memsize_char(size), dc->op1, dc->op2));
1318 cris_cc_mask(dc, CC_MASK_NZ);
1319 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1320 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1324 static unsigned int dec_lz_r(DisasContext *dc)
1326 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1328 cris_cc_mask(dc, CC_MASK_NZ);
1329 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1330 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1334 static unsigned int dec_lsl_r(DisasContext *dc)
1336 int size = memsize_zz(dc);
1338 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1339 memsize_char(size), dc->op1, dc->op2));
1340 cris_cc_mask(dc, CC_MASK_NZ);
1341 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1342 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1343 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1347 static unsigned int dec_lsr_r(DisasContext *dc)
1349 int size = memsize_zz(dc);
1351 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1352 memsize_char(size), dc->op1, dc->op2));
1353 cris_cc_mask(dc, CC_MASK_NZ);
1354 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1355 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1356 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1360 static unsigned int dec_asr_r(DisasContext *dc)
1362 int size = memsize_zz(dc);
1364 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1365 memsize_char(size), dc->op1, dc->op2));
1366 cris_cc_mask(dc, CC_MASK_NZ);
1367 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1368 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1369 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1373 static unsigned int dec_muls_r(DisasContext *dc)
1375 int size = memsize_zz(dc);
1377 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1378 memsize_char(size), dc->op1, dc->op2));
1379 cris_cc_mask(dc, CC_MASK_NZV);
1380 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1381 t_gen_sext(cpu_T[0], cpu_T[0], size);
1382 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1386 static unsigned int dec_mulu_r(DisasContext *dc)
1388 int size = memsize_zz(dc);
1390 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1391 memsize_char(size), dc->op1, dc->op2));
1392 cris_cc_mask(dc, CC_MASK_NZV);
1393 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1394 t_gen_zext(cpu_T[0], cpu_T[0], size);
1395 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1400 static unsigned int dec_dstep_r(DisasContext *dc)
1402 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1403 cris_cc_mask(dc, CC_MASK_NZ);
1404 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1405 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1406 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1410 static unsigned int dec_xor_r(DisasContext *dc)
1412 int size = memsize_zz(dc);
1413 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1414 memsize_char(size), dc->op1, dc->op2));
1415 BUG_ON(size != 4); /* xor is dword. */
1416 cris_cc_mask(dc, CC_MASK_NZ);
1417 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1418 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1422 static unsigned int dec_bound_r(DisasContext *dc)
1424 int size = memsize_zz(dc);
1425 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1426 memsize_char(size), dc->op1, dc->op2));
1427 cris_cc_mask(dc, CC_MASK_NZ);
1428 /* TODO: needs optmimization. */
1429 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1430 /* rd should be 4. */
1431 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1432 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1436 static unsigned int dec_cmp_r(DisasContext *dc)
1438 int size = memsize_zz(dc);
1439 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1440 memsize_char(size), dc->op1, dc->op2));
1441 cris_cc_mask(dc, CC_MASK_NZVC);
1442 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1443 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1447 static unsigned int dec_abs_r(DisasContext *dc)
1451 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1453 cris_cc_mask(dc, CC_MASK_NZ);
1454 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1456 /* TODO: consider a branch free approach. */
1457 l1 = gen_new_label();
1458 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1459 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1461 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1465 static unsigned int dec_add_r(DisasContext *dc)
1467 int size = memsize_zz(dc);
1468 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1469 memsize_char(size), dc->op1, dc->op2));
1470 cris_cc_mask(dc, CC_MASK_NZVC);
1471 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1472 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1476 static unsigned int dec_addc_r(DisasContext *dc)
1478 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1480 cris_evaluate_flags(dc);
1481 cris_cc_mask(dc, CC_MASK_NZVC);
1482 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1483 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1487 static unsigned int dec_mcp_r(DisasContext *dc)
1489 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1491 cris_evaluate_flags(dc);
1492 cris_cc_mask(dc, CC_MASK_RNZV);
1493 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1494 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1495 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1500 static char * swapmode_name(int mode, char *modename) {
1503 modename[i++] = 'n';
1505 modename[i++] = 'w';
1507 modename[i++] = 'b';
1509 modename[i++] = 'r';
1515 static unsigned int dec_swap_r(DisasContext *dc)
1517 DIS(char modename[4]);
1518 DIS(fprintf (logfile, "swap%s $r%u\n",
1519 swapmode_name(dc->op2, modename), dc->op1));
1521 cris_cc_mask(dc, CC_MASK_NZ);
1522 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1524 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1526 t_gen_swapw(cpu_T[0], cpu_T[0]);
1528 t_gen_swapb(cpu_T[0], cpu_T[0]);
1530 t_gen_swapr(cpu_T[0], cpu_T[0]);
1531 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1532 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1536 static unsigned int dec_or_r(DisasContext *dc)
1538 int size = memsize_zz(dc);
1539 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1540 memsize_char(size), dc->op1, dc->op2));
1541 cris_cc_mask(dc, CC_MASK_NZ);
1542 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1543 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1547 static unsigned int dec_addi_r(DisasContext *dc)
1549 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1550 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1551 cris_cc_mask(dc, 0);
1552 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1553 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1554 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1555 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1559 static unsigned int dec_addi_acr(DisasContext *dc)
1561 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1562 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1563 cris_cc_mask(dc, 0);
1564 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1565 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1567 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1568 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1572 static unsigned int dec_neg_r(DisasContext *dc)
1574 int size = memsize_zz(dc);
1575 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1576 memsize_char(size), dc->op1, dc->op2));
1577 cris_cc_mask(dc, CC_MASK_NZVC);
1578 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1579 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1583 static unsigned int dec_btst_r(DisasContext *dc)
1585 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1587 cris_cc_mask(dc, CC_MASK_NZ);
1588 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1589 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1591 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1592 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1597 static unsigned int dec_sub_r(DisasContext *dc)
1599 int size = memsize_zz(dc);
1600 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1601 memsize_char(size), dc->op1, dc->op2));
1602 cris_cc_mask(dc, CC_MASK_NZVC);
1603 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1604 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1608 /* Zero extension. From size to dword. */
1609 static unsigned int dec_movu_r(DisasContext *dc)
1611 int size = memsize_z(dc);
1612 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1616 cris_cc_mask(dc, CC_MASK_NZ);
1617 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1618 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1622 /* Sign extension. From size to dword. */
1623 static unsigned int dec_movs_r(DisasContext *dc)
1625 int size = memsize_z(dc);
1626 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1630 cris_cc_mask(dc, CC_MASK_NZ);
1631 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1632 /* Size can only be qi or hi. */
1633 t_gen_sext(cpu_T[1], cpu_T[0], size);
1634 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1638 /* zero extension. From size to dword. */
1639 static unsigned int dec_addu_r(DisasContext *dc)
1641 int size = memsize_z(dc);
1642 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1646 cris_cc_mask(dc, CC_MASK_NZVC);
1647 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1648 /* Size can only be qi or hi. */
1649 t_gen_zext(cpu_T[1], cpu_T[1], size);
1650 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1651 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1655 /* Sign extension. From size to dword. */
1656 static unsigned int dec_adds_r(DisasContext *dc)
1658 int size = memsize_z(dc);
1659 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1663 cris_cc_mask(dc, CC_MASK_NZVC);
1664 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1665 /* Size can only be qi or hi. */
1666 t_gen_sext(cpu_T[1], cpu_T[1], size);
1667 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1669 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1673 /* Zero extension. From size to dword. */
1674 static unsigned int dec_subu_r(DisasContext *dc)
1676 int size = memsize_z(dc);
1677 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1681 cris_cc_mask(dc, CC_MASK_NZVC);
1682 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1683 /* Size can only be qi or hi. */
1684 t_gen_zext(cpu_T[1], cpu_T[1], size);
1685 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1686 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1690 /* Sign extension. From size to dword. */
1691 static unsigned int dec_subs_r(DisasContext *dc)
1693 int size = memsize_z(dc);
1694 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1698 cris_cc_mask(dc, CC_MASK_NZVC);
1699 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1700 /* Size can only be qi or hi. */
1701 t_gen_sext(cpu_T[1], cpu_T[1], size);
1702 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1703 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1707 static unsigned int dec_setclrf(DisasContext *dc)
1710 int set = (~dc->opcode >> 2) & 1;
1712 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1713 | EXTRACT_FIELD(dc->ir, 0, 3);
1714 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1715 if (set && flags == 0)
1716 DIS(fprintf (logfile, "nop\n"));
1717 else if (!set && (flags & 0x20))
1718 DIS(fprintf (logfile, "di\n"));
1720 DIS(fprintf (logfile, "%sf %x\n",
1721 set ? "set" : "clr",
1724 if (set && (flags & X_FLAG)) {
1729 /* Simply decode the flags. */
1730 cris_evaluate_flags (dc);
1731 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1732 tcg_gen_movi_tl(cc_op, dc->cc_op);
1743 static unsigned int dec_move_rs(DisasContext *dc)
1745 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1746 cris_cc_mask(dc, 0);
1747 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1748 gen_op_movl_sreg_T0(dc->op2);
1750 #if !defined(CONFIG_USER_ONLY)
1752 gen_op_movl_tlb_hi_T0();
1753 else if (dc->op2 == 5) { /* srs is checked at runtime. */
1754 tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
1755 gen_op_movl_tlb_lo_T0();
1760 static unsigned int dec_move_sr(DisasContext *dc)
1762 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1763 cris_cc_mask(dc, 0);
1764 gen_op_movl_T0_sreg(dc->op2);
1765 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1766 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1769 static unsigned int dec_move_rp(DisasContext *dc)
1771 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1772 cris_cc_mask(dc, 0);
1774 if (dc->op2 == PR_CCS) {
1775 cris_evaluate_flags(dc);
1776 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1778 /* User space is not allowed to touch all flags. */
1779 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1780 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1781 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1785 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1787 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1788 if (dc->op2 == PR_CCS) {
1789 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1794 static unsigned int dec_move_pr(DisasContext *dc)
1796 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1797 cris_cc_mask(dc, 0);
1798 /* Support register 0 is hardwired to zero.
1799 Treat it specially. */
1801 tcg_gen_movi_tl(cpu_T[1], 0);
1802 else if (dc->op2 == PR_CCS) {
1803 cris_evaluate_flags(dc);
1804 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1806 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1807 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1811 static unsigned int dec_move_mr(DisasContext *dc)
1813 int memsize = memsize_zz(dc);
1815 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1816 memsize_char(memsize),
1817 dc->op1, dc->postinc ? "+]" : "]",
1820 insn_len = dec_prep_alu_m(dc, 0, memsize);
1821 cris_cc_mask(dc, CC_MASK_NZ);
1822 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1823 do_postinc(dc, memsize);
1827 static unsigned int dec_movs_m(DisasContext *dc)
1829 int memsize = memsize_z(dc);
1831 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1832 memsize_char(memsize),
1833 dc->op1, dc->postinc ? "+]" : "]",
1837 insn_len = dec_prep_alu_m(dc, 1, memsize);
1838 cris_cc_mask(dc, CC_MASK_NZ);
1839 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1840 do_postinc(dc, memsize);
1844 static unsigned int dec_addu_m(DisasContext *dc)
1846 int memsize = memsize_z(dc);
1848 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
1849 memsize_char(memsize),
1850 dc->op1, dc->postinc ? "+]" : "]",
1854 insn_len = dec_prep_alu_m(dc, 0, memsize);
1855 cris_cc_mask(dc, CC_MASK_NZVC);
1856 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1857 do_postinc(dc, memsize);
1861 static unsigned int dec_adds_m(DisasContext *dc)
1863 int memsize = memsize_z(dc);
1865 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
1866 memsize_char(memsize),
1867 dc->op1, dc->postinc ? "+]" : "]",
1871 insn_len = dec_prep_alu_m(dc, 1, memsize);
1872 cris_cc_mask(dc, CC_MASK_NZVC);
1873 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1874 do_postinc(dc, memsize);
1878 static unsigned int dec_subu_m(DisasContext *dc)
1880 int memsize = memsize_z(dc);
1882 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
1883 memsize_char(memsize),
1884 dc->op1, dc->postinc ? "+]" : "]",
1888 insn_len = dec_prep_alu_m(dc, 0, memsize);
1889 cris_cc_mask(dc, CC_MASK_NZVC);
1890 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1891 do_postinc(dc, memsize);
1895 static unsigned int dec_subs_m(DisasContext *dc)
1897 int memsize = memsize_z(dc);
1899 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
1900 memsize_char(memsize),
1901 dc->op1, dc->postinc ? "+]" : "]",
1905 insn_len = dec_prep_alu_m(dc, 1, memsize);
1906 cris_cc_mask(dc, CC_MASK_NZVC);
1907 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1908 do_postinc(dc, memsize);
1912 static unsigned int dec_movu_m(DisasContext *dc)
1914 int memsize = memsize_z(dc);
1917 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
1918 memsize_char(memsize),
1919 dc->op1, dc->postinc ? "+]" : "]",
1922 insn_len = dec_prep_alu_m(dc, 0, memsize);
1923 cris_cc_mask(dc, CC_MASK_NZ);
1924 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1925 do_postinc(dc, memsize);
1929 static unsigned int dec_cmpu_m(DisasContext *dc)
1931 int memsize = memsize_z(dc);
1933 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
1934 memsize_char(memsize),
1935 dc->op1, dc->postinc ? "+]" : "]",
1938 insn_len = dec_prep_alu_m(dc, 0, memsize);
1939 cris_cc_mask(dc, CC_MASK_NZVC);
1940 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1941 do_postinc(dc, memsize);
1945 static unsigned int dec_cmps_m(DisasContext *dc)
1947 int memsize = memsize_z(dc);
1949 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
1950 memsize_char(memsize),
1951 dc->op1, dc->postinc ? "+]" : "]",
1954 insn_len = dec_prep_alu_m(dc, 1, memsize);
1955 cris_cc_mask(dc, CC_MASK_NZVC);
1956 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1957 do_postinc(dc, memsize);
1961 static unsigned int dec_cmp_m(DisasContext *dc)
1963 int memsize = memsize_zz(dc);
1965 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
1966 memsize_char(memsize),
1967 dc->op1, dc->postinc ? "+]" : "]",
1970 insn_len = dec_prep_alu_m(dc, 0, memsize);
1971 cris_cc_mask(dc, CC_MASK_NZVC);
1972 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1973 do_postinc(dc, memsize);
1977 static unsigned int dec_test_m(DisasContext *dc)
1979 int memsize = memsize_zz(dc);
1981 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
1982 memsize_char(memsize),
1983 dc->op1, dc->postinc ? "+]" : "]",
1986 insn_len = dec_prep_alu_m(dc, 0, memsize);
1987 cris_cc_mask(dc, CC_MASK_NZ);
1990 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1991 tcg_gen_movi_tl(cpu_T[1], 0);
1992 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1993 do_postinc(dc, memsize);
1997 static unsigned int dec_and_m(DisasContext *dc)
1999 int memsize = memsize_zz(dc);
2001 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2002 memsize_char(memsize),
2003 dc->op1, dc->postinc ? "+]" : "]",
2006 insn_len = dec_prep_alu_m(dc, 0, memsize);
2007 cris_cc_mask(dc, CC_MASK_NZ);
2008 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2009 do_postinc(dc, memsize);
2013 static unsigned int dec_add_m(DisasContext *dc)
2015 int memsize = memsize_zz(dc);
2017 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2018 memsize_char(memsize),
2019 dc->op1, dc->postinc ? "+]" : "]",
2022 insn_len = dec_prep_alu_m(dc, 0, memsize);
2023 cris_cc_mask(dc, CC_MASK_NZVC);
2024 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2025 do_postinc(dc, memsize);
2029 static unsigned int dec_addo_m(DisasContext *dc)
2031 int memsize = memsize_zz(dc);
2033 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2034 memsize_char(memsize),
2035 dc->op1, dc->postinc ? "+]" : "]",
2038 insn_len = dec_prep_alu_m(dc, 1, memsize);
2039 cris_cc_mask(dc, 0);
2040 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
2041 do_postinc(dc, memsize);
2045 static unsigned int dec_bound_m(DisasContext *dc)
2047 int memsize = memsize_zz(dc);
2049 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2050 memsize_char(memsize),
2051 dc->op1, dc->postinc ? "+]" : "]",
2054 insn_len = dec_prep_alu_m(dc, 0, memsize);
2055 cris_cc_mask(dc, CC_MASK_NZ);
2056 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2057 do_postinc(dc, memsize);
2061 static unsigned int dec_addc_mr(DisasContext *dc)
2064 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2065 dc->op1, dc->postinc ? "+]" : "]",
2068 cris_evaluate_flags(dc);
2069 insn_len = dec_prep_alu_m(dc, 0, 4);
2070 cris_cc_mask(dc, CC_MASK_NZVC);
2071 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2076 static unsigned int dec_sub_m(DisasContext *dc)
2078 int memsize = memsize_zz(dc);
2080 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2081 memsize_char(memsize),
2082 dc->op1, dc->postinc ? "+]" : "]",
2083 dc->op2, dc->ir, dc->zzsize));
2085 insn_len = dec_prep_alu_m(dc, 0, memsize);
2086 cris_cc_mask(dc, CC_MASK_NZVC);
2087 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2088 do_postinc(dc, memsize);
2092 static unsigned int dec_or_m(DisasContext *dc)
2094 int memsize = memsize_zz(dc);
2096 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2097 memsize_char(memsize),
2098 dc->op1, dc->postinc ? "+]" : "]",
2101 insn_len = dec_prep_alu_m(dc, 0, memsize);
2102 cris_cc_mask(dc, CC_MASK_NZ);
2103 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2104 do_postinc(dc, memsize);
2108 static unsigned int dec_move_mp(DisasContext *dc)
2110 int memsize = memsize_zz(dc);
2113 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2114 memsize_char(memsize),
2116 dc->postinc ? "+]" : "]",
2119 insn_len = dec_prep_alu_m(dc, 0, memsize);
2120 cris_cc_mask(dc, 0);
2121 if (dc->op2 == PR_CCS) {
2122 cris_evaluate_flags(dc);
2124 /* User space is not allowed to touch all flags. */
2125 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2126 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2127 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2131 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2133 do_postinc(dc, memsize);
2137 static unsigned int dec_move_pm(DisasContext *dc)
2141 memsize = preg_sizes[dc->op2];
2143 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2144 memsize_char(memsize),
2145 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2147 /* prepare store. Address in T0, value in T1. */
2148 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2149 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2150 gen_store_T0_T1(dc, memsize);
2151 cris_cc_mask(dc, 0);
2154 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2155 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2160 static unsigned int dec_movem_mr(DisasContext *dc)
2164 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2165 dc->postinc ? "+]" : "]", dc->op2));
2167 /* fetch the address into T0 and T1. */
2168 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
2169 for (i = 0; i <= dc->op2; i++) {
2170 /* Perform the load onto regnum i. Always dword wide. */
2171 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2172 gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
2173 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
2175 /* writeback the updated pointer value. */
2177 t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
2179 /* gen_load might want to evaluate the previous insns flags. */
2180 cris_cc_mask(dc, 0);
2184 static unsigned int dec_movem_rm(DisasContext *dc)
2188 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2189 dc->postinc ? "+]" : "]"));
2191 for (i = 0; i <= dc->op2; i++) {
2192 /* Fetch register i into T1. */
2193 t_gen_mov_TN_reg(cpu_T[1], i);
2194 /* Fetch the address into T0. */
2195 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2197 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
2198 /* Perform the store. */
2199 gen_store_T0_T1(dc, 4);
2202 /* T0 should point to the last written addr, advance one more
2204 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
2205 /* writeback the updated pointer value. */
2206 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2208 cris_cc_mask(dc, 0);
2212 static unsigned int dec_move_rm(DisasContext *dc)
2216 memsize = memsize_zz(dc);
2218 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2219 memsize, dc->op2, dc->op1));
2221 /* prepare store. */
2222 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2223 t_gen_mov_TN_reg(cpu_T[1], dc->op2);
2224 gen_store_T0_T1(dc, memsize);
2227 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2228 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
2230 cris_cc_mask(dc, 0);
2234 static unsigned int dec_lapcq(DisasContext *dc)
2236 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2237 dc->pc + dc->op1*2, dc->op2));
2238 cris_cc_mask(dc, 0);
2239 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2240 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2244 static unsigned int dec_lapc_im(DisasContext *dc)
2252 cris_cc_mask(dc, 0);
2253 imm = ldl_code(dc->pc + 2);
2254 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2258 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2262 /* Jump to special reg. */
2263 static unsigned int dec_jump_p(DisasContext *dc)
2265 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2266 cris_cc_mask(dc, 0);
2268 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2269 /* rete will often have low bit set to indicate delayslot. */
2270 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2271 cris_prepare_dyn_jmp(dc);
2275 /* Jump and save. */
2276 static unsigned int dec_jas_r(DisasContext *dc)
2278 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2279 cris_cc_mask(dc, 0);
2280 /* Store the return address in Pd. */
2281 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2284 tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
2286 cris_prepare_dyn_jmp(dc);
2290 static unsigned int dec_jas_im(DisasContext *dc)
2294 imm = ldl_code(dc->pc + 2);
2296 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2297 cris_cc_mask(dc, 0);
2298 /* Stor the return address in Pd. */
2299 tcg_gen_movi_tl(env_btarget, imm);
2300 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2301 cris_prepare_dyn_jmp(dc);
2305 static unsigned int dec_jasc_im(DisasContext *dc)
2309 imm = ldl_code(dc->pc + 2);
2311 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2312 cris_cc_mask(dc, 0);
2313 /* Stor the return address in Pd. */
2314 tcg_gen_movi_tl(cpu_T[0], imm);
2315 t_gen_mov_env_TN(btarget, cpu_T[0]);
2316 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2317 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2318 cris_prepare_dyn_jmp(dc);
2322 static unsigned int dec_jasc_r(DisasContext *dc)
2324 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2325 cris_cc_mask(dc, 0);
2326 /* Stor the return address in Pd. */
2327 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2328 t_gen_mov_env_TN(btarget, cpu_T[0]);
2329 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2330 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2331 cris_prepare_dyn_jmp(dc);
2335 static unsigned int dec_bcc_im(DisasContext *dc)
2338 uint32_t cond = dc->op2;
2340 offset = ldl_code(dc->pc + 2);
2341 offset = sign_extend(offset, 15);
2343 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2344 cc_name(cond), offset,
2345 dc->pc, dc->pc + offset));
2347 cris_cc_mask(dc, 0);
2348 /* op2 holds the condition-code. */
2349 cris_prepare_cc_branch (dc, offset, cond);
2353 static unsigned int dec_bas_im(DisasContext *dc)
2358 simm = ldl_code(dc->pc + 2);
2360 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2361 cris_cc_mask(dc, 0);
2362 /* Stor the return address in Pd. */
2363 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2364 t_gen_mov_env_TN(btarget, cpu_T[0]);
2365 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2366 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2367 cris_prepare_dyn_jmp(dc);
2371 static unsigned int dec_basc_im(DisasContext *dc)
2374 simm = ldl_code(dc->pc + 2);
2376 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2377 cris_cc_mask(dc, 0);
2378 /* Stor the return address in Pd. */
2379 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2380 t_gen_mov_env_TN(btarget, cpu_T[0]);
2381 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2382 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2383 cris_prepare_dyn_jmp(dc);
2387 static unsigned int dec_rfe_etc(DisasContext *dc)
2389 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2390 dc->opcode, dc->pc, dc->op1, dc->op2));
2392 cris_cc_mask(dc, 0);
2394 if (dc->op2 == 15) /* ignore halt. */
2397 switch (dc->op2 & 7) {
2400 cris_evaluate_flags(dc);
2401 gen_op_ccs_rshift();
2402 /* FIXME: don't set the P-FLAG if R is set. */
2403 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
2405 tcg_gen_helper_0_0(helper_rfe);
2406 dc->is_jmp = DISAS_UPDATE;
2414 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2415 t_gen_mov_env_TN(pc, cpu_T[0]);
2416 /* Breaks start at 16 in the exception vector. */
2417 gen_op_break_im(dc->op1 + 16);
2418 dc->is_jmp = DISAS_UPDATE;
2421 printf ("op2=%x\n", dc->op2);
2429 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2431 /* Ignore D-cache flushes. */
2435 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2437 /* Ignore I-cache flushes. */
2441 static unsigned int dec_null(DisasContext *dc)
2443 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2444 dc->pc, dc->opcode, dc->op1, dc->op2);
2450 struct decoder_info {
2455 unsigned int (*dec)(DisasContext *dc);
2457 /* Order matters here. */
2458 {DEC_MOVEQ, dec_moveq},
2459 {DEC_BTSTQ, dec_btstq},
2460 {DEC_CMPQ, dec_cmpq},
2461 {DEC_ADDOQ, dec_addoq},
2462 {DEC_ADDQ, dec_addq},
2463 {DEC_SUBQ, dec_subq},
2464 {DEC_ANDQ, dec_andq},
2466 {DEC_ASRQ, dec_asrq},
2467 {DEC_LSLQ, dec_lslq},
2468 {DEC_LSRQ, dec_lsrq},
2469 {DEC_BCCQ, dec_bccq},
2471 {DEC_BCC_IM, dec_bcc_im},
2472 {DEC_JAS_IM, dec_jas_im},
2473 {DEC_JAS_R, dec_jas_r},
2474 {DEC_JASC_IM, dec_jasc_im},
2475 {DEC_JASC_R, dec_jasc_r},
2476 {DEC_BAS_IM, dec_bas_im},
2477 {DEC_BASC_IM, dec_basc_im},
2478 {DEC_JUMP_P, dec_jump_p},
2479 {DEC_LAPC_IM, dec_lapc_im},
2480 {DEC_LAPCQ, dec_lapcq},
2482 {DEC_RFE_ETC, dec_rfe_etc},
2483 {DEC_ADDC_MR, dec_addc_mr},
2485 {DEC_MOVE_MP, dec_move_mp},
2486 {DEC_MOVE_PM, dec_move_pm},
2487 {DEC_MOVEM_MR, dec_movem_mr},
2488 {DEC_MOVEM_RM, dec_movem_rm},
2489 {DEC_MOVE_PR, dec_move_pr},
2490 {DEC_SCC_R, dec_scc_r},
2491 {DEC_SETF, dec_setclrf},
2492 {DEC_CLEARF, dec_setclrf},
2494 {DEC_MOVE_SR, dec_move_sr},
2495 {DEC_MOVE_RP, dec_move_rp},
2496 {DEC_SWAP_R, dec_swap_r},
2497 {DEC_ABS_R, dec_abs_r},
2498 {DEC_LZ_R, dec_lz_r},
2499 {DEC_MOVE_RS, dec_move_rs},
2500 {DEC_BTST_R, dec_btst_r},
2501 {DEC_ADDC_R, dec_addc_r},
2503 {DEC_DSTEP_R, dec_dstep_r},
2504 {DEC_XOR_R, dec_xor_r},
2505 {DEC_MCP_R, dec_mcp_r},
2506 {DEC_CMP_R, dec_cmp_r},
2508 {DEC_ADDI_R, dec_addi_r},
2509 {DEC_ADDI_ACR, dec_addi_acr},
2511 {DEC_ADD_R, dec_add_r},
2512 {DEC_SUB_R, dec_sub_r},
2514 {DEC_ADDU_R, dec_addu_r},
2515 {DEC_ADDS_R, dec_adds_r},
2516 {DEC_SUBU_R, dec_subu_r},
2517 {DEC_SUBS_R, dec_subs_r},
2518 {DEC_LSL_R, dec_lsl_r},
2520 {DEC_AND_R, dec_and_r},
2521 {DEC_OR_R, dec_or_r},
2522 {DEC_BOUND_R, dec_bound_r},
2523 {DEC_ASR_R, dec_asr_r},
2524 {DEC_LSR_R, dec_lsr_r},
2526 {DEC_MOVU_R, dec_movu_r},
2527 {DEC_MOVS_R, dec_movs_r},
2528 {DEC_NEG_R, dec_neg_r},
2529 {DEC_MOVE_R, dec_move_r},
2531 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2532 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2534 {DEC_MULS_R, dec_muls_r},
2535 {DEC_MULU_R, dec_mulu_r},
2537 {DEC_ADDU_M, dec_addu_m},
2538 {DEC_ADDS_M, dec_adds_m},
2539 {DEC_SUBU_M, dec_subu_m},
2540 {DEC_SUBS_M, dec_subs_m},
2542 {DEC_CMPU_M, dec_cmpu_m},
2543 {DEC_CMPS_M, dec_cmps_m},
2544 {DEC_MOVU_M, dec_movu_m},
2545 {DEC_MOVS_M, dec_movs_m},
2547 {DEC_CMP_M, dec_cmp_m},
2548 {DEC_ADDO_M, dec_addo_m},
2549 {DEC_BOUND_M, dec_bound_m},
2550 {DEC_ADD_M, dec_add_m},
2551 {DEC_SUB_M, dec_sub_m},
2552 {DEC_AND_M, dec_and_m},
2553 {DEC_OR_M, dec_or_m},
2554 {DEC_MOVE_RM, dec_move_rm},
2555 {DEC_TEST_M, dec_test_m},
2556 {DEC_MOVE_MR, dec_move_mr},
2561 static inline unsigned int
2562 cris_decoder(DisasContext *dc)
2564 unsigned int insn_len = 2;
2568 /* Load a halfword onto the instruction register. */
2569 tmp = ldl_code(dc->pc);
2570 dc->ir = tmp & 0xffff;
2572 /* Now decode it. */
2573 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2574 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2575 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2576 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2577 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2578 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2580 /* Large switch for all insns. */
2581 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2582 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2584 insn_len = decinfo[i].dec(dc);
2592 static void check_breakpoint(CPUState *env, DisasContext *dc)
2595 if (env->nb_breakpoints > 0) {
2596 for(j = 0; j < env->nb_breakpoints; j++) {
2597 if (env->breakpoints[j] == dc->pc) {
2598 cris_evaluate_flags (dc);
2599 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2600 t_gen_mov_env_TN(pc, cpu_T[0]);
2602 dc->is_jmp = DISAS_UPDATE;
2608 /* generate intermediate code for basic block 'tb'. */
2609 struct DisasContext ctx;
2611 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2614 uint16_t *gen_opc_end;
2616 unsigned int insn_len;
2618 struct DisasContext *dc = &ctx;
2619 uint32_t next_page_start;
2625 cpu_abort(env, "unaligned pc=%x erp=%x\n",
2626 env->pc, env->pregs[PR_ERP]);
2631 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2633 dc->is_jmp = DISAS_NEXT;
2636 dc->singlestep_enabled = env->singlestep_enabled;
2641 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2643 dc->user = env->pregs[PR_CCS] & U_FLAG;
2644 dc->delayed_branch = 0;
2646 if (loglevel & CPU_LOG_TB_IN_ASM) {
2648 "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
2653 search_pc, env->pc, env->pregs[PR_CCS],
2654 env->pregs[PR_PID], env->pregs[PR_USP],
2655 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2656 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2657 env->regs[8], env->regs[9],
2658 env->regs[10], env->regs[11],
2659 env->regs[12], env->regs[13],
2660 env->regs[14], env->regs[15]);
2664 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2668 check_breakpoint(env, dc);
2669 if (dc->is_jmp == DISAS_JUMP
2670 || dc->is_jmp == DISAS_SWI)
2674 j = gen_opc_ptr - gen_opc_buf;
2678 gen_opc_instr_start[lj++] = 0;
2680 if (dc->delayed_branch == 1) {
2681 gen_opc_pc[lj] = dc->ppc | 1;
2682 gen_opc_instr_start[lj] = 0;
2685 gen_opc_pc[lj] = dc->pc;
2686 gen_opc_instr_start[lj] = 1;
2691 insn_len = cris_decoder(dc);
2692 STATS(gen_op_exec_insn());
2696 cris_clear_x_flag(dc);
2698 /* Check for delayed branches here. If we do it before
2699 actually genereating any host code, the simulator will just
2700 loop doing nothing for on this program location. */
2701 if (dc->delayed_branch) {
2702 dc->delayed_branch--;
2703 if (dc->delayed_branch == 0)
2705 if (dc->bcc == CC_A) {
2707 dc->is_jmp = DISAS_JUMP;
2710 /* Conditional jmp. */
2711 gen_op_cc_jmp (dc->delayed_pc, dc->pc);
2712 dc->is_jmp = DISAS_JUMP;
2717 if (env->singlestep_enabled)
2719 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2720 && ((dc->pc < next_page_start) || dc->delayed_branch));
2722 if (dc->delayed_branch == 1) {
2723 /* Reexecute the last insn. */
2728 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2729 dc->is_jmp, dc->delayed_branch));
2730 /* T0 and env_pc should hold the new pc. */
2731 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2732 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2735 cris_evaluate_flags (dc);
2737 if (__builtin_expect(env->singlestep_enabled, 0)) {
2740 switch(dc->is_jmp) {
2742 gen_goto_tb(dc, 1, dc->pc);
2747 /* indicate that the hash table must be used
2748 to find the next TB */
2753 /* nothing more to generate */
2757 *gen_opc_ptr = INDEX_op_end;
2759 j = gen_opc_ptr - gen_opc_buf;
2762 gen_opc_instr_start[lj++] = 0;
2764 tb->size = dc->pc - pc_start;
2768 if (loglevel & CPU_LOG_TB_IN_ASM) {
2769 fprintf(logfile, "--------------\n");
2770 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2771 target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
2772 fprintf(logfile, "\nisize=%d osize=%d\n",
2773 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2779 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2781 return gen_intermediate_code_internal(env, tb, 0);
2784 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2786 return gen_intermediate_code_internal(env, tb, 1);
2789 void cpu_dump_state (CPUState *env, FILE *f,
2790 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2799 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2800 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2802 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2804 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2805 env->debug1, env->debug2, env->debug3);
2807 for (i = 0; i < 16; i++) {
2808 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2809 if ((i + 1) % 4 == 0)
2810 cpu_fprintf(f, "\n");
2812 cpu_fprintf(f, "\nspecial regs:\n");
2813 for (i = 0; i < 16; i++) {
2814 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2815 if ((i + 1) % 4 == 0)
2816 cpu_fprintf(f, "\n");
2818 srs = env->pregs[PR_SRS];
2819 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
2821 for (i = 0; i < 16; i++) {
2822 cpu_fprintf(f, "s%2.2d=%8.8x ",
2823 i, env->sregs[srs][i]);
2824 if ((i + 1) % 4 == 0)
2825 cpu_fprintf(f, "\n");
2828 cpu_fprintf(f, "\n\n");
2832 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
2836 CPUCRISState *cpu_cris_init (const char *cpu_model)
2841 env = qemu_mallocz(sizeof(CPUCRISState));
2846 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
2847 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
2848 #if TARGET_LONG_BITS > HOST_LONG_BITS
2849 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
2850 TCG_AREG0, offsetof(CPUState, t0), "T0");
2851 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
2852 TCG_AREG0, offsetof(CPUState, t1), "T1");
2854 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
2855 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
2858 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2859 offsetof(CPUState, cc_src), "cc_src");
2860 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2861 offsetof(CPUState, cc_dest),
2863 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2864 offsetof(CPUState, cc_result),
2866 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2867 offsetof(CPUState, cc_op), "cc_op");
2868 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2869 offsetof(CPUState, cc_size),
2871 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2872 offsetof(CPUState, cc_mask),
2875 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2876 offsetof(CPUState, pc),
2878 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2879 offsetof(CPUState, btarget),
2882 for (i = 0; i < 16; i++) {
2883 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2884 offsetof(CPUState, regs[i]),
2887 for (i = 0; i < 16; i++) {
2888 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2889 offsetof(CPUState, pregs[i]),
2893 TCG_HELPER(helper_tlb_update);
2894 TCG_HELPER(helper_tlb_flush);
2895 TCG_HELPER(helper_rfe);
2896 TCG_HELPER(helper_store);
2897 TCG_HELPER(helper_dump);
2898 TCG_HELPER(helper_dummy);
2900 TCG_HELPER(helper_evaluate_flags_muls);
2901 TCG_HELPER(helper_evaluate_flags_mulu);
2902 TCG_HELPER(helper_evaluate_flags_mcp);
2903 TCG_HELPER(helper_evaluate_flags_alu_4);
2904 TCG_HELPER(helper_evaluate_flags_move_4);
2905 TCG_HELPER(helper_evaluate_flags_move_2);
2906 TCG_HELPER(helper_evaluate_flags);
2912 void cpu_reset (CPUCRISState *env)
2914 memset(env, 0, offsetof(CPUCRISState, breakpoints));
2917 #if defined(CONFIG_USER_ONLY)
2918 /* start in user mode with interrupts enabled. */
2919 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
2921 env->pregs[PR_CCS] = 0;
2925 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
2926 unsigned long searched_pc, int pc_pos, void *puc)
2928 env->pc = gen_opc_pc[pc_pos];