2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
47 # define LOG_DIS(...) do { \
48 if (loglevel & CPU_LOG_TB_IN_ASM) \
49 fprintf(logfile, ## __VA_ARGS__); \
52 # define LOG_DIS(...) do { } while (0)
56 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
57 #define BUG_ON(x) ({if (x) BUG();})
61 /* Used by the decoder. */
62 #define EXTRACT_FIELD(src, start, end) \
63 (((src) >> start) & ((1 << (end - start + 1)) - 1))
65 #define CC_MASK_NZ 0xc
66 #define CC_MASK_NZV 0xe
67 #define CC_MASK_NZVC 0xf
68 #define CC_MASK_RNZV 0x10e
70 static TCGv_ptr cpu_env;
71 static TCGv cpu_R[16];
72 static TCGv cpu_PR[16];
76 static TCGv cc_result;
81 static TCGv env_btaken;
82 static TCGv env_btarget;
85 #include "gen-icount.h"
87 /* This is the state at translation time. */
88 typedef struct DisasContext {
97 unsigned int zsize, zzsize;
106 int cc_size_uptodate; /* -1 invalid or last written value. */
108 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
109 int flags_uptodate; /* Wether or not $ccs is uptodate. */
110 int flagx_known; /* Wether or not flags_x has the x flag known at
114 int clear_x; /* Clear x after this insn? */
115 int cpustate_changed;
116 unsigned int tb_flags; /* tb dependent flags. */
121 #define JMP_INDIRECT 2
122 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
127 struct TranslationBlock *tb;
128 int singlestep_enabled;
131 static void gen_BUG(DisasContext *dc, const char *file, int line)
133 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
134 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
135 cpu_abort(dc->env, "%s:%d\n", file, line);
138 static const char *regnames[] =
140 "$r0", "$r1", "$r2", "$r3",
141 "$r4", "$r5", "$r6", "$r7",
142 "$r8", "$r9", "$r10", "$r11",
143 "$r12", "$r13", "$sp", "$acr",
145 static const char *pregnames[] =
147 "$bz", "$vr", "$pid", "$srs",
148 "$wz", "$exs", "$eda", "$mof",
149 "$dz", "$ebp", "$erp", "$srp",
150 "$nrp", "$ccs", "$usp", "$spc",
153 /* We need this table to handle preg-moves with implicit width. */
154 static int preg_sizes[] = {
165 #define t_gen_mov_TN_env(tn, member) \
166 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
167 #define t_gen_mov_env_TN(member, tn) \
168 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
170 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
173 fprintf(stderr, "wrong register read $r%d\n", r);
174 tcg_gen_mov_tl(tn, cpu_R[r]);
176 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
179 fprintf(stderr, "wrong register write $r%d\n", r);
180 tcg_gen_mov_tl(cpu_R[r], tn);
183 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
185 if (offset > sizeof (CPUState))
186 fprintf(stderr, "wrong load from env from off=%d\n", offset);
187 tcg_gen_ld_tl(tn, cpu_env, offset);
189 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
191 if (offset > sizeof (CPUState))
192 fprintf(stderr, "wrong store to env at off=%d\n", offset);
193 tcg_gen_st_tl(tn, cpu_env, offset);
196 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
199 fprintf(stderr, "wrong register read $p%d\n", r);
200 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
201 tcg_gen_mov_tl(tn, tcg_const_tl(0));
203 tcg_gen_mov_tl(tn, tcg_const_tl(32));
204 else if (r == PR_EDA) {
205 printf("read from EDA!\n");
206 tcg_gen_mov_tl(tn, cpu_PR[r]);
209 tcg_gen_mov_tl(tn, cpu_PR[r]);
211 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
214 fprintf(stderr, "wrong register write $p%d\n", r);
215 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
217 else if (r == PR_SRS)
218 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
221 gen_helper_tlb_flush_pid(tn);
222 if (dc->tb_flags & S_FLAG && r == PR_SPC)
223 gen_helper_spc_write(tn);
224 else if (r == PR_CCS)
225 dc->cpustate_changed = 1;
226 tcg_gen_mov_tl(cpu_PR[r], tn);
230 static inline void t_gen_raise_exception(uint32_t index)
232 TCGv_i32 tmp = tcg_const_i32(index);
233 gen_helper_raise_exception(tmp);
234 tcg_temp_free_i32(tmp);
237 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
242 t_31 = tcg_const_tl(31);
243 tcg_gen_shl_tl(d, a, b);
245 tcg_gen_sub_tl(t0, t_31, b);
246 tcg_gen_sar_tl(t0, t0, t_31);
247 tcg_gen_and_tl(t0, t0, d);
248 tcg_gen_xor_tl(d, d, t0);
253 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
258 t_31 = tcg_temp_new();
259 tcg_gen_shr_tl(d, a, b);
261 tcg_gen_movi_tl(t_31, 31);
262 tcg_gen_sub_tl(t0, t_31, b);
263 tcg_gen_sar_tl(t0, t0, t_31);
264 tcg_gen_and_tl(t0, t0, d);
265 tcg_gen_xor_tl(d, d, t0);
270 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
275 t_31 = tcg_temp_new();
276 tcg_gen_sar_tl(d, a, b);
278 tcg_gen_movi_tl(t_31, 31);
279 tcg_gen_sub_tl(t0, t_31, b);
280 tcg_gen_sar_tl(t0, t0, t_31);
281 tcg_gen_or_tl(d, d, t0);
286 /* 64-bit signed mul, lower result in d and upper in d2. */
287 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
291 t0 = tcg_temp_new_i64();
292 t1 = tcg_temp_new_i64();
294 tcg_gen_ext_i32_i64(t0, a);
295 tcg_gen_ext_i32_i64(t1, b);
296 tcg_gen_mul_i64(t0, t0, t1);
298 tcg_gen_trunc_i64_i32(d, t0);
299 tcg_gen_shri_i64(t0, t0, 32);
300 tcg_gen_trunc_i64_i32(d2, t0);
302 tcg_temp_free_i64(t0);
303 tcg_temp_free_i64(t1);
306 /* 64-bit unsigned muls, lower result in d and upper in d2. */
307 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
311 t0 = tcg_temp_new_i64();
312 t1 = tcg_temp_new_i64();
314 tcg_gen_extu_i32_i64(t0, a);
315 tcg_gen_extu_i32_i64(t1, b);
316 tcg_gen_mul_i64(t0, t0, t1);
318 tcg_gen_trunc_i64_i32(d, t0);
319 tcg_gen_shri_i64(t0, t0, 32);
320 tcg_gen_trunc_i64_i32(d2, t0);
322 tcg_temp_free_i64(t0);
323 tcg_temp_free_i64(t1);
326 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
330 l1 = gen_new_label();
337 tcg_gen_shli_tl(d, a, 1);
338 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
339 tcg_gen_sub_tl(d, d, b);
343 /* Extended arithmetics on CRIS. */
344 static inline void t_gen_add_flag(TCGv d, int flag)
349 t_gen_mov_TN_preg(c, PR_CCS);
350 /* Propagate carry into d. */
351 tcg_gen_andi_tl(c, c, 1 << flag);
353 tcg_gen_shri_tl(c, c, flag);
354 tcg_gen_add_tl(d, d, c);
358 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
360 if (dc->flagx_known) {
365 t_gen_mov_TN_preg(c, PR_CCS);
366 /* C flag is already at bit 0. */
367 tcg_gen_andi_tl(c, c, C_FLAG);
368 tcg_gen_add_tl(d, d, c);
376 t_gen_mov_TN_preg(x, PR_CCS);
377 tcg_gen_mov_tl(c, x);
379 /* Propagate carry into d if X is set. Branch free. */
380 tcg_gen_andi_tl(c, c, C_FLAG);
381 tcg_gen_andi_tl(x, x, X_FLAG);
382 tcg_gen_shri_tl(x, x, 4);
384 tcg_gen_and_tl(x, x, c);
385 tcg_gen_add_tl(d, d, x);
391 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
393 if (dc->flagx_known) {
398 t_gen_mov_TN_preg(c, PR_CCS);
399 /* C flag is already at bit 0. */
400 tcg_gen_andi_tl(c, c, C_FLAG);
401 tcg_gen_sub_tl(d, d, c);
409 t_gen_mov_TN_preg(x, PR_CCS);
410 tcg_gen_mov_tl(c, x);
412 /* Propagate carry into d if X is set. Branch free. */
413 tcg_gen_andi_tl(c, c, C_FLAG);
414 tcg_gen_andi_tl(x, x, X_FLAG);
415 tcg_gen_shri_tl(x, x, 4);
417 tcg_gen_and_tl(x, x, c);
418 tcg_gen_sub_tl(d, d, x);
424 /* Swap the two bytes within each half word of the s operand.
425 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
426 static inline void t_gen_swapb(TCGv d, TCGv s)
431 org_s = tcg_temp_new();
433 /* d and s may refer to the same object. */
434 tcg_gen_mov_tl(org_s, s);
435 tcg_gen_shli_tl(t, org_s, 8);
436 tcg_gen_andi_tl(d, t, 0xff00ff00);
437 tcg_gen_shri_tl(t, org_s, 8);
438 tcg_gen_andi_tl(t, t, 0x00ff00ff);
439 tcg_gen_or_tl(d, d, t);
441 tcg_temp_free(org_s);
444 /* Swap the halfwords of the s operand. */
445 static inline void t_gen_swapw(TCGv d, TCGv s)
448 /* d and s refer the same object. */
450 tcg_gen_mov_tl(t, s);
451 tcg_gen_shli_tl(d, t, 16);
452 tcg_gen_shri_tl(t, t, 16);
453 tcg_gen_or_tl(d, d, t);
457 /* Reverse the within each byte.
458 T0 = (((T0 << 7) & 0x80808080) |
459 ((T0 << 5) & 0x40404040) |
460 ((T0 << 3) & 0x20202020) |
461 ((T0 << 1) & 0x10101010) |
462 ((T0 >> 1) & 0x08080808) |
463 ((T0 >> 3) & 0x04040404) |
464 ((T0 >> 5) & 0x02020202) |
465 ((T0 >> 7) & 0x01010101));
467 static inline void t_gen_swapr(TCGv d, TCGv s)
470 int shift; /* LSL when positive, LSR when negative. */
485 /* d and s refer the same object. */
487 org_s = tcg_temp_new();
488 tcg_gen_mov_tl(org_s, s);
490 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
491 tcg_gen_andi_tl(d, t, bitrev[0].mask);
492 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
493 if (bitrev[i].shift >= 0) {
494 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
496 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
498 tcg_gen_andi_tl(t, t, bitrev[i].mask);
499 tcg_gen_or_tl(d, d, t);
502 tcg_temp_free(org_s);
505 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
510 l1 = gen_new_label();
511 btaken = tcg_temp_new();
513 /* Conditional jmp. */
514 tcg_gen_mov_tl(btaken, env_btaken);
515 tcg_gen_mov_tl(env_pc, pc_false);
516 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
517 tcg_gen_mov_tl(env_pc, pc_true);
520 tcg_temp_free(btaken);
523 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
525 TranslationBlock *tb;
527 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
529 tcg_gen_movi_tl(env_pc, dest);
530 tcg_gen_exit_tb((long)tb + n);
532 tcg_gen_movi_tl(env_pc, dest);
537 /* Sign extend at translation time. */
538 static int sign_extend(unsigned int val, unsigned int width)
550 static inline void cris_clear_x_flag(DisasContext *dc)
552 if (dc->flagx_known && dc->flags_x)
553 dc->flags_uptodate = 0;
559 static void cris_flush_cc_state(DisasContext *dc)
561 if (dc->cc_size_uptodate != dc->cc_size) {
562 tcg_gen_movi_tl(cc_size, dc->cc_size);
563 dc->cc_size_uptodate = dc->cc_size;
565 tcg_gen_movi_tl(cc_op, dc->cc_op);
566 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
569 static void cris_evaluate_flags(DisasContext *dc)
571 if (dc->flags_uptodate)
574 cris_flush_cc_state(dc);
579 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
580 cpu_PR[PR_CCS], cc_src,
584 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
585 cpu_PR[PR_CCS], cc_result,
589 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
590 cpu_PR[PR_CCS], cc_result,
603 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
604 cpu_PR[PR_CCS], cc_result);
607 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
608 cpu_PR[PR_CCS], cc_result);
611 gen_helper_evaluate_flags();
620 if (dc->cc_size == 4)
621 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
622 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
624 gen_helper_evaluate_flags();
631 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
632 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
635 gen_helper_evaluate_flags();
641 if (dc->flagx_known) {
643 tcg_gen_ori_tl(cpu_PR[PR_CCS],
644 cpu_PR[PR_CCS], X_FLAG);
646 tcg_gen_andi_tl(cpu_PR[PR_CCS],
647 cpu_PR[PR_CCS], ~X_FLAG);
649 dc->flags_uptodate = 1;
652 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
661 /* Check if we need to evaluate the condition codes due to
663 ovl = (dc->cc_mask ^ mask) & ~mask;
665 /* TODO: optimize this case. It trigs all the time. */
666 cris_evaluate_flags (dc);
672 static void cris_update_cc_op(DisasContext *dc, int op, int size)
676 dc->flags_uptodate = 0;
679 static inline void cris_update_cc_x(DisasContext *dc)
681 /* Save the x flag state at the time of the cc snapshot. */
682 if (dc->flagx_known) {
683 if (dc->cc_x_uptodate == (2 | dc->flags_x))
685 tcg_gen_movi_tl(cc_x, dc->flags_x);
686 dc->cc_x_uptodate = 2 | dc->flags_x;
689 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
690 dc->cc_x_uptodate = 1;
694 /* Update cc prior to executing ALU op. Needs source operands untouched. */
695 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
696 TCGv dst, TCGv src, int size)
699 cris_update_cc_op(dc, op, size);
700 tcg_gen_mov_tl(cc_src, src);
709 tcg_gen_mov_tl(cc_dest, dst);
711 cris_update_cc_x(dc);
715 /* Update cc after executing ALU op. needs the result. */
716 static inline void cris_update_result(DisasContext *dc, TCGv res)
719 tcg_gen_mov_tl(cc_result, res);
722 /* Returns one if the write back stage should execute. */
723 static void cris_alu_op_exec(DisasContext *dc, int op,
724 TCGv dst, TCGv a, TCGv b, int size)
726 /* Emit the ALU insns. */
730 tcg_gen_add_tl(dst, a, b);
731 /* Extended arithmetics. */
732 t_gen_addx_carry(dc, dst);
735 tcg_gen_add_tl(dst, a, b);
736 t_gen_add_flag(dst, 0); /* C_FLAG. */
739 tcg_gen_add_tl(dst, a, b);
740 t_gen_add_flag(dst, 8); /* R_FLAG. */
743 tcg_gen_sub_tl(dst, a, b);
744 /* Extended arithmetics. */
745 t_gen_subx_carry(dc, dst);
748 tcg_gen_mov_tl(dst, b);
751 tcg_gen_or_tl(dst, a, b);
754 tcg_gen_and_tl(dst, a, b);
757 tcg_gen_xor_tl(dst, a, b);
760 t_gen_lsl(dst, a, b);
763 t_gen_lsr(dst, a, b);
766 t_gen_asr(dst, a, b);
769 tcg_gen_neg_tl(dst, b);
770 /* Extended arithmetics. */
771 t_gen_subx_carry(dc, dst);
774 gen_helper_lz(dst, b);
777 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
780 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
783 t_gen_cris_dstep(dst, a, b);
788 l1 = gen_new_label();
789 tcg_gen_mov_tl(dst, a);
790 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
791 tcg_gen_mov_tl(dst, b);
796 tcg_gen_sub_tl(dst, a, b);
797 /* Extended arithmetics. */
798 t_gen_subx_carry(dc, dst);
801 fprintf (logfile, "illegal ALU op.\n");
807 tcg_gen_andi_tl(dst, dst, 0xff);
809 tcg_gen_andi_tl(dst, dst, 0xffff);
812 static void cris_alu(DisasContext *dc, int op,
813 TCGv d, TCGv op_a, TCGv op_b, int size)
820 if (op == CC_OP_CMP) {
821 tmp = tcg_temp_new();
823 } else if (size == 4) {
827 tmp = tcg_temp_new();
830 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
831 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
832 cris_update_result(dc, tmp);
837 tcg_gen_andi_tl(d, d, ~0xff);
839 tcg_gen_andi_tl(d, d, ~0xffff);
840 tcg_gen_or_tl(d, d, tmp);
842 if (!TCGV_EQUAL(tmp, d))
846 static int arith_cc(DisasContext *dc)
850 case CC_OP_ADDC: return 1;
851 case CC_OP_ADD: return 1;
852 case CC_OP_SUB: return 1;
853 case CC_OP_DSTEP: return 1;
854 case CC_OP_LSL: return 1;
855 case CC_OP_LSR: return 1;
856 case CC_OP_ASR: return 1;
857 case CC_OP_CMP: return 1;
858 case CC_OP_NEG: return 1;
859 case CC_OP_OR: return 1;
860 case CC_OP_AND: return 1;
861 case CC_OP_XOR: return 1;
862 case CC_OP_MULU: return 1;
863 case CC_OP_MULS: return 1;
871 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
873 int arith_opt, move_opt;
875 /* TODO: optimize more condition codes. */
878 * If the flags are live, we've gotta look into the bits of CCS.
879 * Otherwise, if we just did an arithmetic operation we try to
880 * evaluate the condition code faster.
882 * When this function is done, T0 should be non-zero if the condition
885 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
886 move_opt = (dc->cc_op == CC_OP_MOVE);
889 if (arith_opt || move_opt) {
890 /* If cc_result is zero, T0 should be
891 non-zero otherwise T0 should be zero. */
893 l1 = gen_new_label();
894 tcg_gen_movi_tl(cc, 0);
895 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
897 tcg_gen_movi_tl(cc, 1);
901 cris_evaluate_flags(dc);
903 cpu_PR[PR_CCS], Z_FLAG);
907 if (arith_opt || move_opt)
908 tcg_gen_mov_tl(cc, cc_result);
910 cris_evaluate_flags(dc);
911 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
913 tcg_gen_andi_tl(cc, cc, Z_FLAG);
917 cris_evaluate_flags(dc);
918 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
921 cris_evaluate_flags(dc);
922 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
923 tcg_gen_andi_tl(cc, cc, C_FLAG);
926 cris_evaluate_flags(dc);
927 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
930 cris_evaluate_flags(dc);
931 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
933 tcg_gen_andi_tl(cc, cc, V_FLAG);
936 if (arith_opt || move_opt) {
939 if (dc->cc_size == 1)
941 else if (dc->cc_size == 2)
944 tcg_gen_shri_tl(cc, cc_result, bits);
945 tcg_gen_xori_tl(cc, cc, 1);
947 cris_evaluate_flags(dc);
948 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
950 tcg_gen_andi_tl(cc, cc, N_FLAG);
954 if (arith_opt || move_opt) {
957 if (dc->cc_size == 1)
959 else if (dc->cc_size == 2)
962 tcg_gen_shri_tl(cc, cc_result, 31);
965 cris_evaluate_flags(dc);
966 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
971 cris_evaluate_flags(dc);
972 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
976 cris_evaluate_flags(dc);
980 tmp = tcg_temp_new();
981 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
983 /* Overlay the C flag on top of the Z. */
984 tcg_gen_shli_tl(cc, tmp, 2);
985 tcg_gen_and_tl(cc, tmp, cc);
986 tcg_gen_andi_tl(cc, cc, Z_FLAG);
992 cris_evaluate_flags(dc);
993 /* Overlay the V flag on top of the N. */
994 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
997 tcg_gen_andi_tl(cc, cc, N_FLAG);
998 tcg_gen_xori_tl(cc, cc, N_FLAG);
1001 cris_evaluate_flags(dc);
1002 /* Overlay the V flag on top of the N. */
1003 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1005 cpu_PR[PR_CCS], cc);
1006 tcg_gen_andi_tl(cc, cc, N_FLAG);
1009 cris_evaluate_flags(dc);
1016 /* To avoid a shift we overlay everything on
1018 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1019 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1021 tcg_gen_xori_tl(z, z, 2);
1023 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1024 tcg_gen_xori_tl(n, n, 2);
1025 tcg_gen_and_tl(cc, z, n);
1026 tcg_gen_andi_tl(cc, cc, 2);
1033 cris_evaluate_flags(dc);
1040 /* To avoid a shift we overlay everything on
1042 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1043 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1045 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1046 tcg_gen_or_tl(cc, z, n);
1047 tcg_gen_andi_tl(cc, cc, 2);
1054 cris_evaluate_flags(dc);
1055 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1058 tcg_gen_movi_tl(cc, 1);
1066 static void cris_store_direct_jmp(DisasContext *dc)
1068 /* Store the direct jmp state into the cpu-state. */
1069 if (dc->jmp == JMP_DIRECT) {
1070 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1071 tcg_gen_movi_tl(env_btaken, 1);
1075 static void cris_prepare_cc_branch (DisasContext *dc,
1076 int offset, int cond)
1078 /* This helps us re-schedule the micro-code to insns in delay-slots
1079 before the actual jump. */
1080 dc->delayed_branch = 2;
1081 dc->jmp_pc = dc->pc + offset;
1085 dc->jmp = JMP_INDIRECT;
1086 gen_tst_cc (dc, env_btaken, cond);
1087 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1089 /* Allow chaining. */
1090 dc->jmp = JMP_DIRECT;
1095 /* jumps, when the dest is in a live reg for example. Direct should be set
1096 when the dest addr is constant to allow tb chaining. */
1097 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1099 /* This helps us re-schedule the micro-code to insns in delay-slots
1100 before the actual jump. */
1101 dc->delayed_branch = 2;
1103 if (type == JMP_INDIRECT)
1104 tcg_gen_movi_tl(env_btaken, 1);
1107 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1109 int mem_index = cpu_mmu_index(dc->env);
1111 /* If we get a fault on a delayslot we must keep the jmp state in
1112 the cpu-state to be able to re-execute the jmp. */
1113 if (dc->delayed_branch == 1)
1114 cris_store_direct_jmp(dc);
1116 tcg_gen_qemu_ld64(dst, addr, mem_index);
1119 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1120 unsigned int size, int sign)
1122 int mem_index = cpu_mmu_index(dc->env);
1124 /* If we get a fault on a delayslot we must keep the jmp state in
1125 the cpu-state to be able to re-execute the jmp. */
1126 if (dc->delayed_branch == 1)
1127 cris_store_direct_jmp(dc);
1131 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1133 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1135 else if (size == 2) {
1137 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1139 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1141 else if (size == 4) {
1142 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1149 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1152 int mem_index = cpu_mmu_index(dc->env);
1154 /* If we get a fault on a delayslot we must keep the jmp state in
1155 the cpu-state to be able to re-execute the jmp. */
1156 if (dc->delayed_branch == 1)
1157 cris_store_direct_jmp(dc);
1160 /* Conditional writes. We only support the kind were X and P are known
1161 at translation time. */
1162 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1164 cris_evaluate_flags(dc);
1165 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1170 tcg_gen_qemu_st8(val, addr, mem_index);
1172 tcg_gen_qemu_st16(val, addr, mem_index);
1174 tcg_gen_qemu_st32(val, addr, mem_index);
1176 if (dc->flagx_known && dc->flags_x) {
1177 cris_evaluate_flags(dc);
1178 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1182 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1185 tcg_gen_ext8s_i32(d, s);
1187 tcg_gen_ext16s_i32(d, s);
1188 else if(!TCGV_EQUAL(d, s))
1189 tcg_gen_mov_tl(d, s);
1192 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1195 tcg_gen_ext8u_i32(d, s);
1197 tcg_gen_ext16u_i32(d, s);
1198 else if (!TCGV_EQUAL(d, s))
1199 tcg_gen_mov_tl(d, s);
1203 static char memsize_char(int size)
1207 case 1: return 'b'; break;
1208 case 2: return 'w'; break;
1209 case 4: return 'd'; break;
1217 static inline unsigned int memsize_z(DisasContext *dc)
1219 return dc->zsize + 1;
1222 static inline unsigned int memsize_zz(DisasContext *dc)
1233 static inline void do_postinc (DisasContext *dc, int size)
1236 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1239 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1240 int size, int s_ext, TCGv dst)
1243 t_gen_sext(dst, cpu_R[rs], size);
1245 t_gen_zext(dst, cpu_R[rs], size);
1248 /* Prepare T0 and T1 for a register alu operation.
1249 s_ext decides if the operand1 should be sign-extended or zero-extended when
1251 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1252 int size, int s_ext, TCGv dst, TCGv src)
1254 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1257 t_gen_sext(dst, cpu_R[rd], size);
1259 t_gen_zext(dst, cpu_R[rd], size);
1262 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1265 unsigned int rs, rd;
1272 is_imm = rs == 15 && dc->postinc;
1274 /* Load [$rs] onto T1. */
1276 insn_len = 2 + memsize;
1283 imm = ldsb_code(dc->pc + 2);
1285 imm = ldsw_code(dc->pc + 2);
1288 imm = ldub_code(dc->pc + 2);
1290 imm = lduw_code(dc->pc + 2);
1293 imm = ldl_code(dc->pc + 2);
1295 tcg_gen_movi_tl(dst, imm);
1298 cris_flush_cc_state(dc);
1299 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1301 t_gen_sext(dst, dst, memsize);
1303 t_gen_zext(dst, dst, memsize);
1308 /* Prepare T0 and T1 for a memory + alu operation.
1309 s_ext decides if the operand1 should be sign-extended or zero-extended when
1311 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1316 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1317 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1322 static const char *cc_name(int cc)
1324 static const char *cc_names[16] = {
1325 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1326 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1329 return cc_names[cc];
1333 /* Start of insn decoders. */
1335 static unsigned int dec_bccq(DisasContext *dc)
1339 uint32_t cond = dc->op2;
1342 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1343 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1346 offset |= sign << 8;
1348 offset = sign_extend(offset, 8);
1350 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1352 /* op2 holds the condition-code. */
1353 cris_cc_mask(dc, 0);
1354 cris_prepare_cc_branch (dc, offset, cond);
1357 static unsigned int dec_addoq(DisasContext *dc)
1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1362 imm = sign_extend(dc->op1, 7);
1364 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1365 cris_cc_mask(dc, 0);
1366 /* Fetch register operand, */
1367 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1371 static unsigned int dec_addq(DisasContext *dc)
1373 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1375 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1377 cris_cc_mask(dc, CC_MASK_NZVC);
1379 cris_alu(dc, CC_OP_ADD,
1380 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1383 static unsigned int dec_moveq(DisasContext *dc)
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1389 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1391 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1394 static unsigned int dec_subq(DisasContext *dc)
1396 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1398 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1400 cris_cc_mask(dc, CC_MASK_NZVC);
1401 cris_alu(dc, CC_OP_SUB,
1402 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1405 static unsigned int dec_cmpq(DisasContext *dc)
1408 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1409 imm = sign_extend(dc->op1, 5);
1411 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1412 cris_cc_mask(dc, CC_MASK_NZVC);
1414 cris_alu(dc, CC_OP_CMP,
1415 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1418 static unsigned int dec_andq(DisasContext *dc)
1421 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1422 imm = sign_extend(dc->op1, 5);
1424 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1425 cris_cc_mask(dc, CC_MASK_NZ);
1427 cris_alu(dc, CC_OP_AND,
1428 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1431 static unsigned int dec_orq(DisasContext *dc)
1434 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1435 imm = sign_extend(dc->op1, 5);
1436 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1437 cris_cc_mask(dc, CC_MASK_NZ);
1439 cris_alu(dc, CC_OP_OR,
1440 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1443 static unsigned int dec_btstq(DisasContext *dc)
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1446 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1448 cris_cc_mask(dc, CC_MASK_NZ);
1449 cris_evaluate_flags(dc);
1450 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1451 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1452 cris_alu(dc, CC_OP_MOVE,
1453 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1454 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1455 dc->flags_uptodate = 1;
1458 static unsigned int dec_asrq(DisasContext *dc)
1460 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1461 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1462 cris_cc_mask(dc, CC_MASK_NZ);
1464 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1465 cris_alu(dc, CC_OP_MOVE,
1467 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1470 static unsigned int dec_lslq(DisasContext *dc)
1472 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1473 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1475 cris_cc_mask(dc, CC_MASK_NZ);
1477 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1479 cris_alu(dc, CC_OP_MOVE,
1481 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1484 static unsigned int dec_lsrq(DisasContext *dc)
1486 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1487 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1489 cris_cc_mask(dc, CC_MASK_NZ);
1491 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1492 cris_alu(dc, CC_OP_MOVE,
1494 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1498 static unsigned int dec_move_r(DisasContext *dc)
1500 int size = memsize_zz(dc);
1502 LOG_DIS("move.%c $r%u, $r%u\n",
1503 memsize_char(size), dc->op1, dc->op2);
1505 cris_cc_mask(dc, CC_MASK_NZ);
1507 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1508 cris_cc_mask(dc, CC_MASK_NZ);
1509 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1510 cris_update_cc_x(dc);
1511 cris_update_result(dc, cpu_R[dc->op2]);
1516 t0 = tcg_temp_new();
1517 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1518 cris_alu(dc, CC_OP_MOVE,
1520 cpu_R[dc->op2], t0, size);
1526 static unsigned int dec_scc_r(DisasContext *dc)
1530 LOG_DIS("s%s $r%u\n",
1531 cc_name(cond), dc->op1);
1537 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1538 l1 = gen_new_label();
1539 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1540 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1544 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1546 cris_cc_mask(dc, 0);
1550 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1553 t[0] = cpu_R[dc->op2];
1554 t[1] = cpu_R[dc->op1];
1556 t[0] = tcg_temp_new();
1557 t[1] = tcg_temp_new();
1561 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1564 tcg_temp_free(t[0]);
1565 tcg_temp_free(t[1]);
1569 static unsigned int dec_and_r(DisasContext *dc)
1572 int size = memsize_zz(dc);
1574 LOG_DIS("and.%c $r%u, $r%u\n",
1575 memsize_char(size), dc->op1, dc->op2);
1577 cris_cc_mask(dc, CC_MASK_NZ);
1579 cris_alu_alloc_temps(dc, size, t);
1580 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1581 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1582 cris_alu_free_temps(dc, size, t);
1586 static unsigned int dec_lz_r(DisasContext *dc)
1589 LOG_DIS("lz $r%u, $r%u\n",
1591 cris_cc_mask(dc, CC_MASK_NZ);
1592 t0 = tcg_temp_new();
1593 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1594 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1599 static unsigned int dec_lsl_r(DisasContext *dc)
1602 int size = memsize_zz(dc);
1604 LOG_DIS("lsl.%c $r%u, $r%u\n",
1605 memsize_char(size), dc->op1, dc->op2);
1607 cris_cc_mask(dc, CC_MASK_NZ);
1608 cris_alu_alloc_temps(dc, size, t);
1609 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1610 tcg_gen_andi_tl(t[1], t[1], 63);
1611 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1612 cris_alu_alloc_temps(dc, size, t);
1616 static unsigned int dec_lsr_r(DisasContext *dc)
1619 int size = memsize_zz(dc);
1621 LOG_DIS("lsr.%c $r%u, $r%u\n",
1622 memsize_char(size), dc->op1, dc->op2);
1624 cris_cc_mask(dc, CC_MASK_NZ);
1625 cris_alu_alloc_temps(dc, size, t);
1626 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1627 tcg_gen_andi_tl(t[1], t[1], 63);
1628 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1629 cris_alu_free_temps(dc, size, t);
1633 static unsigned int dec_asr_r(DisasContext *dc)
1636 int size = memsize_zz(dc);
1638 LOG_DIS("asr.%c $r%u, $r%u\n",
1639 memsize_char(size), dc->op1, dc->op2);
1641 cris_cc_mask(dc, CC_MASK_NZ);
1642 cris_alu_alloc_temps(dc, size, t);
1643 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1644 tcg_gen_andi_tl(t[1], t[1], 63);
1645 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1646 cris_alu_free_temps(dc, size, t);
1650 static unsigned int dec_muls_r(DisasContext *dc)
1653 int size = memsize_zz(dc);
1655 LOG_DIS("muls.%c $r%u, $r%u\n",
1656 memsize_char(size), dc->op1, dc->op2);
1657 cris_cc_mask(dc, CC_MASK_NZV);
1658 cris_alu_alloc_temps(dc, size, t);
1659 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1661 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1662 cris_alu_free_temps(dc, size, t);
1666 static unsigned int dec_mulu_r(DisasContext *dc)
1669 int size = memsize_zz(dc);
1671 LOG_DIS("mulu.%c $r%u, $r%u\n",
1672 memsize_char(size), dc->op1, dc->op2);
1673 cris_cc_mask(dc, CC_MASK_NZV);
1674 cris_alu_alloc_temps(dc, size, t);
1675 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1677 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1678 cris_alu_alloc_temps(dc, size, t);
1683 static unsigned int dec_dstep_r(DisasContext *dc)
1685 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1686 cris_cc_mask(dc, CC_MASK_NZ);
1687 cris_alu(dc, CC_OP_DSTEP,
1688 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1692 static unsigned int dec_xor_r(DisasContext *dc)
1695 int size = memsize_zz(dc);
1696 LOG_DIS("xor.%c $r%u, $r%u\n",
1697 memsize_char(size), dc->op1, dc->op2);
1698 BUG_ON(size != 4); /* xor is dword. */
1699 cris_cc_mask(dc, CC_MASK_NZ);
1700 cris_alu_alloc_temps(dc, size, t);
1701 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1703 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1704 cris_alu_free_temps(dc, size, t);
1708 static unsigned int dec_bound_r(DisasContext *dc)
1711 int size = memsize_zz(dc);
1712 LOG_DIS("bound.%c $r%u, $r%u\n",
1713 memsize_char(size), dc->op1, dc->op2);
1714 cris_cc_mask(dc, CC_MASK_NZ);
1715 l0 = tcg_temp_local_new();
1716 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1717 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1722 static unsigned int dec_cmp_r(DisasContext *dc)
1725 int size = memsize_zz(dc);
1726 LOG_DIS("cmp.%c $r%u, $r%u\n",
1727 memsize_char(size), dc->op1, dc->op2);
1728 cris_cc_mask(dc, CC_MASK_NZVC);
1729 cris_alu_alloc_temps(dc, size, t);
1730 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1732 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1733 cris_alu_free_temps(dc, size, t);
1737 static unsigned int dec_abs_r(DisasContext *dc)
1741 LOG_DIS("abs $r%u, $r%u\n",
1743 cris_cc_mask(dc, CC_MASK_NZ);
1745 t0 = tcg_temp_new();
1746 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1747 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1748 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1751 cris_alu(dc, CC_OP_MOVE,
1752 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1756 static unsigned int dec_add_r(DisasContext *dc)
1759 int size = memsize_zz(dc);
1760 LOG_DIS("add.%c $r%u, $r%u\n",
1761 memsize_char(size), dc->op1, dc->op2);
1762 cris_cc_mask(dc, CC_MASK_NZVC);
1763 cris_alu_alloc_temps(dc, size, t);
1764 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1766 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1767 cris_alu_free_temps(dc, size, t);
1771 static unsigned int dec_addc_r(DisasContext *dc)
1773 LOG_DIS("addc $r%u, $r%u\n",
1775 cris_evaluate_flags(dc);
1776 /* Set for this insn. */
1777 dc->flagx_known = 1;
1778 dc->flags_x = X_FLAG;
1780 cris_cc_mask(dc, CC_MASK_NZVC);
1781 cris_alu(dc, CC_OP_ADDC,
1782 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1786 static unsigned int dec_mcp_r(DisasContext *dc)
1788 LOG_DIS("mcp $p%u, $r%u\n",
1790 cris_evaluate_flags(dc);
1791 cris_cc_mask(dc, CC_MASK_RNZV);
1792 cris_alu(dc, CC_OP_MCP,
1793 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1798 static char * swapmode_name(int mode, char *modename) {
1801 modename[i++] = 'n';
1803 modename[i++] = 'w';
1805 modename[i++] = 'b';
1807 modename[i++] = 'r';
1813 static unsigned int dec_swap_r(DisasContext *dc)
1819 LOG_DIS("swap%s $r%u\n",
1820 swapmode_name(dc->op2, modename), dc->op1);
1822 cris_cc_mask(dc, CC_MASK_NZ);
1823 t0 = tcg_temp_new();
1824 t_gen_mov_TN_reg(t0, dc->op1);
1826 tcg_gen_not_tl(t0, t0);
1828 t_gen_swapw(t0, t0);
1830 t_gen_swapb(t0, t0);
1832 t_gen_swapr(t0, t0);
1833 cris_alu(dc, CC_OP_MOVE,
1834 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1839 static unsigned int dec_or_r(DisasContext *dc)
1842 int size = memsize_zz(dc);
1843 LOG_DIS("or.%c $r%u, $r%u\n",
1844 memsize_char(size), dc->op1, dc->op2);
1845 cris_cc_mask(dc, CC_MASK_NZ);
1846 cris_alu_alloc_temps(dc, size, t);
1847 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1848 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1849 cris_alu_free_temps(dc, size, t);
1853 static unsigned int dec_addi_r(DisasContext *dc)
1856 LOG_DIS("addi.%c $r%u, $r%u\n",
1857 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1858 cris_cc_mask(dc, 0);
1859 t0 = tcg_temp_new();
1860 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1861 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1866 static unsigned int dec_addi_acr(DisasContext *dc)
1869 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1870 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1871 cris_cc_mask(dc, 0);
1872 t0 = tcg_temp_new();
1873 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1874 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1879 static unsigned int dec_neg_r(DisasContext *dc)
1882 int size = memsize_zz(dc);
1883 LOG_DIS("neg.%c $r%u, $r%u\n",
1884 memsize_char(size), dc->op1, dc->op2);
1885 cris_cc_mask(dc, CC_MASK_NZVC);
1886 cris_alu_alloc_temps(dc, size, t);
1887 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1889 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1890 cris_alu_free_temps(dc, size, t);
1894 static unsigned int dec_btst_r(DisasContext *dc)
1896 LOG_DIS("btst $r%u, $r%u\n",
1898 cris_cc_mask(dc, CC_MASK_NZ);
1899 cris_evaluate_flags(dc);
1900 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1901 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1902 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1903 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1904 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1905 dc->flags_uptodate = 1;
1909 static unsigned int dec_sub_r(DisasContext *dc)
1912 int size = memsize_zz(dc);
1913 LOG_DIS("sub.%c $r%u, $r%u\n",
1914 memsize_char(size), dc->op1, dc->op2);
1915 cris_cc_mask(dc, CC_MASK_NZVC);
1916 cris_alu_alloc_temps(dc, size, t);
1917 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1918 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1919 cris_alu_free_temps(dc, size, t);
1923 /* Zero extension. From size to dword. */
1924 static unsigned int dec_movu_r(DisasContext *dc)
1927 int size = memsize_z(dc);
1928 LOG_DIS("movu.%c $r%u, $r%u\n",
1932 cris_cc_mask(dc, CC_MASK_NZ);
1933 t0 = tcg_temp_new();
1934 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1935 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1940 /* Sign extension. From size to dword. */
1941 static unsigned int dec_movs_r(DisasContext *dc)
1944 int size = memsize_z(dc);
1945 LOG_DIS("movs.%c $r%u, $r%u\n",
1949 cris_cc_mask(dc, CC_MASK_NZ);
1950 t0 = tcg_temp_new();
1951 /* Size can only be qi or hi. */
1952 t_gen_sext(t0, cpu_R[dc->op1], size);
1953 cris_alu(dc, CC_OP_MOVE,
1954 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1959 /* zero extension. From size to dword. */
1960 static unsigned int dec_addu_r(DisasContext *dc)
1963 int size = memsize_z(dc);
1964 LOG_DIS("addu.%c $r%u, $r%u\n",
1968 cris_cc_mask(dc, CC_MASK_NZVC);
1969 t0 = tcg_temp_new();
1970 /* Size can only be qi or hi. */
1971 t_gen_zext(t0, cpu_R[dc->op1], size);
1972 cris_alu(dc, CC_OP_ADD,
1973 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1978 /* Sign extension. From size to dword. */
1979 static unsigned int dec_adds_r(DisasContext *dc)
1982 int size = memsize_z(dc);
1983 LOG_DIS("adds.%c $r%u, $r%u\n",
1987 cris_cc_mask(dc, CC_MASK_NZVC);
1988 t0 = tcg_temp_new();
1989 /* Size can only be qi or hi. */
1990 t_gen_sext(t0, cpu_R[dc->op1], size);
1991 cris_alu(dc, CC_OP_ADD,
1992 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1997 /* Zero extension. From size to dword. */
1998 static unsigned int dec_subu_r(DisasContext *dc)
2001 int size = memsize_z(dc);
2002 LOG_DIS("subu.%c $r%u, $r%u\n",
2006 cris_cc_mask(dc, CC_MASK_NZVC);
2007 t0 = tcg_temp_new();
2008 /* Size can only be qi or hi. */
2009 t_gen_zext(t0, cpu_R[dc->op1], size);
2010 cris_alu(dc, CC_OP_SUB,
2011 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2016 /* Sign extension. From size to dword. */
2017 static unsigned int dec_subs_r(DisasContext *dc)
2020 int size = memsize_z(dc);
2021 LOG_DIS("subs.%c $r%u, $r%u\n",
2025 cris_cc_mask(dc, CC_MASK_NZVC);
2026 t0 = tcg_temp_new();
2027 /* Size can only be qi or hi. */
2028 t_gen_sext(t0, cpu_R[dc->op1], size);
2029 cris_alu(dc, CC_OP_SUB,
2030 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2035 static unsigned int dec_setclrf(DisasContext *dc)
2038 int set = (~dc->opcode >> 2) & 1;
2041 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2042 | EXTRACT_FIELD(dc->ir, 0, 3);
2043 if (set && flags == 0) {
2046 } else if (!set && (flags & 0x20)) {
2051 set ? "set" : "clr",
2055 /* User space is not allowed to touch these. Silently ignore. */
2056 if (dc->tb_flags & U_FLAG) {
2057 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2060 if (flags & X_FLAG) {
2061 dc->flagx_known = 1;
2063 dc->flags_x = X_FLAG;
2068 /* Break the TB if the P flag changes. */
2069 if (flags & P_FLAG) {
2070 if ((set && !(dc->tb_flags & P_FLAG))
2071 || (!set && (dc->tb_flags & P_FLAG))) {
2072 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2073 dc->is_jmp = DISAS_UPDATE;
2074 dc->cpustate_changed = 1;
2077 if (flags & S_FLAG) {
2078 dc->cpustate_changed = 1;
2082 /* Simply decode the flags. */
2083 cris_evaluate_flags (dc);
2084 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2085 cris_update_cc_x(dc);
2086 tcg_gen_movi_tl(cc_op, dc->cc_op);
2089 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2090 /* Enter user mode. */
2091 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2092 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2093 dc->cpustate_changed = 1;
2095 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2098 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2100 dc->flags_uptodate = 1;
2105 static unsigned int dec_move_rs(DisasContext *dc)
2107 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2108 cris_cc_mask(dc, 0);
2109 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2112 static unsigned int dec_move_sr(DisasContext *dc)
2114 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2115 cris_cc_mask(dc, 0);
2116 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2120 static unsigned int dec_move_rp(DisasContext *dc)
2123 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2124 cris_cc_mask(dc, 0);
2126 t[0] = tcg_temp_new();
2127 if (dc->op2 == PR_CCS) {
2128 cris_evaluate_flags(dc);
2129 t_gen_mov_TN_reg(t[0], dc->op1);
2130 if (dc->tb_flags & U_FLAG) {
2131 t[1] = tcg_temp_new();
2132 /* User space is not allowed to touch all flags. */
2133 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2134 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2135 tcg_gen_or_tl(t[0], t[1], t[0]);
2136 tcg_temp_free(t[1]);
2140 t_gen_mov_TN_reg(t[0], dc->op1);
2142 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2143 if (dc->op2 == PR_CCS) {
2144 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2145 dc->flags_uptodate = 1;
2147 tcg_temp_free(t[0]);
2150 static unsigned int dec_move_pr(DisasContext *dc)
2153 LOG_DIS("move $p%u, $r%u\n", dc->op1, dc->op2);
2154 cris_cc_mask(dc, 0);
2156 if (dc->op2 == PR_CCS)
2157 cris_evaluate_flags(dc);
2159 t0 = tcg_temp_new();
2160 t_gen_mov_TN_preg(t0, dc->op2);
2161 cris_alu(dc, CC_OP_MOVE,
2162 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2167 static unsigned int dec_move_mr(DisasContext *dc)
2169 int memsize = memsize_zz(dc);
2171 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2172 memsize_char(memsize),
2173 dc->op1, dc->postinc ? "+]" : "]",
2177 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2178 cris_cc_mask(dc, CC_MASK_NZ);
2179 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2180 cris_update_cc_x(dc);
2181 cris_update_result(dc, cpu_R[dc->op2]);
2186 t0 = tcg_temp_new();
2187 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2188 cris_cc_mask(dc, CC_MASK_NZ);
2189 cris_alu(dc, CC_OP_MOVE,
2190 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2193 do_postinc(dc, memsize);
2197 static inline void cris_alu_m_alloc_temps(TCGv *t)
2199 t[0] = tcg_temp_new();
2200 t[1] = tcg_temp_new();
2203 static inline void cris_alu_m_free_temps(TCGv *t)
2205 tcg_temp_free(t[0]);
2206 tcg_temp_free(t[1]);
2209 static unsigned int dec_movs_m(DisasContext *dc)
2212 int memsize = memsize_z(dc);
2214 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2215 memsize_char(memsize),
2216 dc->op1, dc->postinc ? "+]" : "]",
2219 cris_alu_m_alloc_temps(t);
2221 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2222 cris_cc_mask(dc, CC_MASK_NZ);
2223 cris_alu(dc, CC_OP_MOVE,
2224 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2225 do_postinc(dc, memsize);
2226 cris_alu_m_free_temps(t);
2230 static unsigned int dec_addu_m(DisasContext *dc)
2233 int memsize = memsize_z(dc);
2235 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2236 memsize_char(memsize),
2237 dc->op1, dc->postinc ? "+]" : "]",
2240 cris_alu_m_alloc_temps(t);
2242 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2243 cris_cc_mask(dc, CC_MASK_NZVC);
2244 cris_alu(dc, CC_OP_ADD,
2245 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2246 do_postinc(dc, memsize);
2247 cris_alu_m_free_temps(t);
2251 static unsigned int dec_adds_m(DisasContext *dc)
2254 int memsize = memsize_z(dc);
2256 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2257 memsize_char(memsize),
2258 dc->op1, dc->postinc ? "+]" : "]",
2261 cris_alu_m_alloc_temps(t);
2263 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2264 cris_cc_mask(dc, CC_MASK_NZVC);
2265 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2266 do_postinc(dc, memsize);
2267 cris_alu_m_free_temps(t);
2271 static unsigned int dec_subu_m(DisasContext *dc)
2274 int memsize = memsize_z(dc);
2276 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2277 memsize_char(memsize),
2278 dc->op1, dc->postinc ? "+]" : "]",
2281 cris_alu_m_alloc_temps(t);
2283 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2284 cris_cc_mask(dc, CC_MASK_NZVC);
2285 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2286 do_postinc(dc, memsize);
2287 cris_alu_m_free_temps(t);
2291 static unsigned int dec_subs_m(DisasContext *dc)
2294 int memsize = memsize_z(dc);
2296 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2297 memsize_char(memsize),
2298 dc->op1, dc->postinc ? "+]" : "]",
2301 cris_alu_m_alloc_temps(t);
2303 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2304 cris_cc_mask(dc, CC_MASK_NZVC);
2305 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2306 do_postinc(dc, memsize);
2307 cris_alu_m_free_temps(t);
2311 static unsigned int dec_movu_m(DisasContext *dc)
2314 int memsize = memsize_z(dc);
2317 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2318 memsize_char(memsize),
2319 dc->op1, dc->postinc ? "+]" : "]",
2322 cris_alu_m_alloc_temps(t);
2323 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2324 cris_cc_mask(dc, CC_MASK_NZ);
2325 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2326 do_postinc(dc, memsize);
2327 cris_alu_m_free_temps(t);
2331 static unsigned int dec_cmpu_m(DisasContext *dc)
2334 int memsize = memsize_z(dc);
2336 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2337 memsize_char(memsize),
2338 dc->op1, dc->postinc ? "+]" : "]",
2341 cris_alu_m_alloc_temps(t);
2342 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2343 cris_cc_mask(dc, CC_MASK_NZVC);
2344 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2345 do_postinc(dc, memsize);
2346 cris_alu_m_free_temps(t);
2350 static unsigned int dec_cmps_m(DisasContext *dc)
2353 int memsize = memsize_z(dc);
2355 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2356 memsize_char(memsize),
2357 dc->op1, dc->postinc ? "+]" : "]",
2360 cris_alu_m_alloc_temps(t);
2361 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2362 cris_cc_mask(dc, CC_MASK_NZVC);
2363 cris_alu(dc, CC_OP_CMP,
2364 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2366 do_postinc(dc, memsize);
2367 cris_alu_m_free_temps(t);
2371 static unsigned int dec_cmp_m(DisasContext *dc)
2374 int memsize = memsize_zz(dc);
2376 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2377 memsize_char(memsize),
2378 dc->op1, dc->postinc ? "+]" : "]",
2381 cris_alu_m_alloc_temps(t);
2382 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2383 cris_cc_mask(dc, CC_MASK_NZVC);
2384 cris_alu(dc, CC_OP_CMP,
2385 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2387 do_postinc(dc, memsize);
2388 cris_alu_m_free_temps(t);
2392 static unsigned int dec_test_m(DisasContext *dc)
2395 int memsize = memsize_zz(dc);
2397 LOG_DIS("test.%d [$r%u%s] op2=%x\n",
2398 memsize_char(memsize),
2399 dc->op1, dc->postinc ? "+]" : "]",
2402 cris_evaluate_flags(dc);
2404 cris_alu_m_alloc_temps(t);
2405 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2406 cris_cc_mask(dc, CC_MASK_NZ);
2407 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2409 cris_alu(dc, CC_OP_CMP,
2410 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2411 do_postinc(dc, memsize);
2412 cris_alu_m_free_temps(t);
2416 static unsigned int dec_and_m(DisasContext *dc)
2419 int memsize = memsize_zz(dc);
2421 LOG_DIS("and.%d [$r%u%s, $r%u\n",
2422 memsize_char(memsize),
2423 dc->op1, dc->postinc ? "+]" : "]",
2426 cris_alu_m_alloc_temps(t);
2427 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2428 cris_cc_mask(dc, CC_MASK_NZ);
2429 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2430 do_postinc(dc, memsize);
2431 cris_alu_m_free_temps(t);
2435 static unsigned int dec_add_m(DisasContext *dc)
2438 int memsize = memsize_zz(dc);
2440 LOG_DIS("add.%d [$r%u%s, $r%u\n",
2441 memsize_char(memsize),
2442 dc->op1, dc->postinc ? "+]" : "]",
2445 cris_alu_m_alloc_temps(t);
2446 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2447 cris_cc_mask(dc, CC_MASK_NZVC);
2448 cris_alu(dc, CC_OP_ADD,
2449 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2450 do_postinc(dc, memsize);
2451 cris_alu_m_free_temps(t);
2455 static unsigned int dec_addo_m(DisasContext *dc)
2458 int memsize = memsize_zz(dc);
2460 LOG_DIS("add.%d [$r%u%s, $r%u\n",
2461 memsize_char(memsize),
2462 dc->op1, dc->postinc ? "+]" : "]",
2465 cris_alu_m_alloc_temps(t);
2466 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2467 cris_cc_mask(dc, 0);
2468 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2469 do_postinc(dc, memsize);
2470 cris_alu_m_free_temps(t);
2474 static unsigned int dec_bound_m(DisasContext *dc)
2477 int memsize = memsize_zz(dc);
2479 LOG_DIS("bound.%d [$r%u%s, $r%u\n",
2480 memsize_char(memsize),
2481 dc->op1, dc->postinc ? "+]" : "]",
2484 l[0] = tcg_temp_local_new();
2485 l[1] = tcg_temp_local_new();
2486 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2487 cris_cc_mask(dc, CC_MASK_NZ);
2488 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2489 do_postinc(dc, memsize);
2490 tcg_temp_free(l[0]);
2491 tcg_temp_free(l[1]);
2495 static unsigned int dec_addc_mr(DisasContext *dc)
2499 LOG_DIS("addc [$r%u%s, $r%u\n",
2500 dc->op1, dc->postinc ? "+]" : "]",
2503 cris_evaluate_flags(dc);
2505 /* Set for this insn. */
2506 dc->flagx_known = 1;
2507 dc->flags_x = X_FLAG;
2509 cris_alu_m_alloc_temps(t);
2510 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2511 cris_cc_mask(dc, CC_MASK_NZVC);
2512 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2514 cris_alu_m_free_temps(t);
2518 static unsigned int dec_sub_m(DisasContext *dc)
2521 int memsize = memsize_zz(dc);
2523 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2524 memsize_char(memsize),
2525 dc->op1, dc->postinc ? "+]" : "]",
2526 dc->op2, dc->ir, dc->zzsize);
2528 cris_alu_m_alloc_temps(t);
2529 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2530 cris_cc_mask(dc, CC_MASK_NZVC);
2531 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2532 do_postinc(dc, memsize);
2533 cris_alu_m_free_temps(t);
2537 static unsigned int dec_or_m(DisasContext *dc)
2540 int memsize = memsize_zz(dc);
2542 LOG_DIS("or.%d [$r%u%s, $r%u pc=%x\n",
2543 memsize_char(memsize),
2544 dc->op1, dc->postinc ? "+]" : "]",
2547 cris_alu_m_alloc_temps(t);
2548 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2549 cris_cc_mask(dc, CC_MASK_NZ);
2550 cris_alu(dc, CC_OP_OR,
2551 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2552 do_postinc(dc, memsize);
2553 cris_alu_m_free_temps(t);
2557 static unsigned int dec_move_mp(DisasContext *dc)
2560 int memsize = memsize_zz(dc);
2563 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2564 memsize_char(memsize),
2566 dc->postinc ? "+]" : "]",
2569 cris_alu_m_alloc_temps(t);
2570 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2571 cris_cc_mask(dc, 0);
2572 if (dc->op2 == PR_CCS) {
2573 cris_evaluate_flags(dc);
2574 if (dc->tb_flags & U_FLAG) {
2575 /* User space is not allowed to touch all flags. */
2576 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2577 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2578 tcg_gen_or_tl(t[1], t[0], t[1]);
2582 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2584 do_postinc(dc, memsize);
2585 cris_alu_m_free_temps(t);
2589 static unsigned int dec_move_pm(DisasContext *dc)
2594 memsize = preg_sizes[dc->op2];
2596 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2597 memsize_char(memsize),
2598 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2600 /* prepare store. Address in T0, value in T1. */
2601 if (dc->op2 == PR_CCS)
2602 cris_evaluate_flags(dc);
2603 t0 = tcg_temp_new();
2604 t_gen_mov_TN_preg(t0, dc->op2);
2605 cris_flush_cc_state(dc);
2606 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2609 cris_cc_mask(dc, 0);
2611 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2615 static unsigned int dec_movem_mr(DisasContext *dc)
2621 int nr = dc->op2 + 1;
2623 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2624 dc->postinc ? "+]" : "]", dc->op2);
2626 addr = tcg_temp_new();
2627 /* There are probably better ways of doing this. */
2628 cris_flush_cc_state(dc);
2629 for (i = 0; i < (nr >> 1); i++) {
2630 tmp[i] = tcg_temp_new_i64();
2631 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2632 gen_load64(dc, tmp[i], addr);
2635 tmp32 = tcg_temp_new_i32();
2636 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2637 gen_load(dc, tmp32, addr, 4, 0);
2639 tcg_temp_free(addr);
2641 for (i = 0; i < (nr >> 1); i++) {
2642 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2643 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2644 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2645 tcg_temp_free_i64(tmp[i]);
2648 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2649 tcg_temp_free(tmp32);
2652 /* writeback the updated pointer value. */
2654 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2656 /* gen_load might want to evaluate the previous insns flags. */
2657 cris_cc_mask(dc, 0);
2661 static unsigned int dec_movem_rm(DisasContext *dc)
2667 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2668 dc->postinc ? "+]" : "]");
2670 cris_flush_cc_state(dc);
2672 tmp = tcg_temp_new();
2673 addr = tcg_temp_new();
2674 tcg_gen_movi_tl(tmp, 4);
2675 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2676 for (i = 0; i <= dc->op2; i++) {
2677 /* Displace addr. */
2678 /* Perform the store. */
2679 gen_store(dc, addr, cpu_R[i], 4);
2680 tcg_gen_add_tl(addr, addr, tmp);
2683 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2684 cris_cc_mask(dc, 0);
2686 tcg_temp_free(addr);
2690 static unsigned int dec_move_rm(DisasContext *dc)
2694 memsize = memsize_zz(dc);
2696 LOG_DIS("move.%d $r%u, [$r%u]\n",
2697 memsize, dc->op2, dc->op1);
2699 /* prepare store. */
2700 cris_flush_cc_state(dc);
2701 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2704 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2705 cris_cc_mask(dc, 0);
2709 static unsigned int dec_lapcq(DisasContext *dc)
2711 LOG_DIS("lapcq %x, $r%u\n",
2712 dc->pc + dc->op1*2, dc->op2);
2713 cris_cc_mask(dc, 0);
2714 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2718 static unsigned int dec_lapc_im(DisasContext *dc)
2726 cris_cc_mask(dc, 0);
2727 imm = ldl_code(dc->pc + 2);
2728 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2732 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2736 /* Jump to special reg. */
2737 static unsigned int dec_jump_p(DisasContext *dc)
2739 LOG_DIS("jump $p%u\n", dc->op2);
2741 if (dc->op2 == PR_CCS)
2742 cris_evaluate_flags(dc);
2743 t_gen_mov_TN_preg(env_btarget, dc->op2);
2744 /* rete will often have low bit set to indicate delayslot. */
2745 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2746 cris_cc_mask(dc, 0);
2747 cris_prepare_jmp(dc, JMP_INDIRECT);
2751 /* Jump and save. */
2752 static unsigned int dec_jas_r(DisasContext *dc)
2754 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2755 cris_cc_mask(dc, 0);
2756 /* Store the return address in Pd. */
2757 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2760 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2762 cris_prepare_jmp(dc, JMP_INDIRECT);
2766 static unsigned int dec_jas_im(DisasContext *dc)
2770 imm = ldl_code(dc->pc + 2);
2772 LOG_DIS("jas 0x%x\n", imm);
2773 cris_cc_mask(dc, 0);
2774 /* Store the return address in Pd. */
2775 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2778 cris_prepare_jmp(dc, JMP_DIRECT);
2782 static unsigned int dec_jasc_im(DisasContext *dc)
2786 imm = ldl_code(dc->pc + 2);
2788 LOG_DIS("jasc 0x%x\n", imm);
2789 cris_cc_mask(dc, 0);
2790 /* Store the return address in Pd. */
2791 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2794 cris_prepare_jmp(dc, JMP_DIRECT);
2798 static unsigned int dec_jasc_r(DisasContext *dc)
2800 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2801 cris_cc_mask(dc, 0);
2802 /* Store the return address in Pd. */
2803 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2804 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2805 cris_prepare_jmp(dc, JMP_INDIRECT);
2809 static unsigned int dec_bcc_im(DisasContext *dc)
2812 uint32_t cond = dc->op2;
2814 offset = ldsw_code(dc->pc + 2);
2816 LOG_DIS("b%s %d pc=%x dst=%x\n",
2817 cc_name(cond), offset,
2818 dc->pc, dc->pc + offset);
2820 cris_cc_mask(dc, 0);
2821 /* op2 holds the condition-code. */
2822 cris_prepare_cc_branch (dc, offset, cond);
2826 static unsigned int dec_bas_im(DisasContext *dc)
2831 simm = ldl_code(dc->pc + 2);
2833 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2834 cris_cc_mask(dc, 0);
2835 /* Store the return address in Pd. */
2836 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2838 dc->jmp_pc = dc->pc + simm;
2839 cris_prepare_jmp(dc, JMP_DIRECT);
2843 static unsigned int dec_basc_im(DisasContext *dc)
2846 simm = ldl_code(dc->pc + 2);
2848 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2849 cris_cc_mask(dc, 0);
2850 /* Store the return address in Pd. */
2851 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2853 dc->jmp_pc = dc->pc + simm;
2854 cris_prepare_jmp(dc, JMP_DIRECT);
2858 static unsigned int dec_rfe_etc(DisasContext *dc)
2860 cris_cc_mask(dc, 0);
2862 if (dc->op2 == 15) {
2863 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2864 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2865 t_gen_raise_exception(EXCP_HLT);
2869 switch (dc->op2 & 7) {
2873 cris_evaluate_flags(dc);
2875 dc->is_jmp = DISAS_UPDATE;
2880 cris_evaluate_flags(dc);
2882 dc->is_jmp = DISAS_UPDATE;
2885 LOG_DIS("break %d\n", dc->op1);
2886 cris_evaluate_flags (dc);
2888 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2890 /* Breaks start at 16 in the exception vector. */
2891 t_gen_mov_env_TN(trap_vector,
2892 tcg_const_tl(dc->op1 + 16));
2893 t_gen_raise_exception(EXCP_BREAK);
2894 dc->is_jmp = DISAS_UPDATE;
2897 printf ("op2=%x\n", dc->op2);
2905 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2910 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2915 static unsigned int dec_null(DisasContext *dc)
2917 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2918 dc->pc, dc->opcode, dc->op1, dc->op2);
2924 static struct decoder_info {
2929 unsigned int (*dec)(DisasContext *dc);
2931 /* Order matters here. */
2932 {DEC_MOVEQ, dec_moveq},
2933 {DEC_BTSTQ, dec_btstq},
2934 {DEC_CMPQ, dec_cmpq},
2935 {DEC_ADDOQ, dec_addoq},
2936 {DEC_ADDQ, dec_addq},
2937 {DEC_SUBQ, dec_subq},
2938 {DEC_ANDQ, dec_andq},
2940 {DEC_ASRQ, dec_asrq},
2941 {DEC_LSLQ, dec_lslq},
2942 {DEC_LSRQ, dec_lsrq},
2943 {DEC_BCCQ, dec_bccq},
2945 {DEC_BCC_IM, dec_bcc_im},
2946 {DEC_JAS_IM, dec_jas_im},
2947 {DEC_JAS_R, dec_jas_r},
2948 {DEC_JASC_IM, dec_jasc_im},
2949 {DEC_JASC_R, dec_jasc_r},
2950 {DEC_BAS_IM, dec_bas_im},
2951 {DEC_BASC_IM, dec_basc_im},
2952 {DEC_JUMP_P, dec_jump_p},
2953 {DEC_LAPC_IM, dec_lapc_im},
2954 {DEC_LAPCQ, dec_lapcq},
2956 {DEC_RFE_ETC, dec_rfe_etc},
2957 {DEC_ADDC_MR, dec_addc_mr},
2959 {DEC_MOVE_MP, dec_move_mp},
2960 {DEC_MOVE_PM, dec_move_pm},
2961 {DEC_MOVEM_MR, dec_movem_mr},
2962 {DEC_MOVEM_RM, dec_movem_rm},
2963 {DEC_MOVE_PR, dec_move_pr},
2964 {DEC_SCC_R, dec_scc_r},
2965 {DEC_SETF, dec_setclrf},
2966 {DEC_CLEARF, dec_setclrf},
2968 {DEC_MOVE_SR, dec_move_sr},
2969 {DEC_MOVE_RP, dec_move_rp},
2970 {DEC_SWAP_R, dec_swap_r},
2971 {DEC_ABS_R, dec_abs_r},
2972 {DEC_LZ_R, dec_lz_r},
2973 {DEC_MOVE_RS, dec_move_rs},
2974 {DEC_BTST_R, dec_btst_r},
2975 {DEC_ADDC_R, dec_addc_r},
2977 {DEC_DSTEP_R, dec_dstep_r},
2978 {DEC_XOR_R, dec_xor_r},
2979 {DEC_MCP_R, dec_mcp_r},
2980 {DEC_CMP_R, dec_cmp_r},
2982 {DEC_ADDI_R, dec_addi_r},
2983 {DEC_ADDI_ACR, dec_addi_acr},
2985 {DEC_ADD_R, dec_add_r},
2986 {DEC_SUB_R, dec_sub_r},
2988 {DEC_ADDU_R, dec_addu_r},
2989 {DEC_ADDS_R, dec_adds_r},
2990 {DEC_SUBU_R, dec_subu_r},
2991 {DEC_SUBS_R, dec_subs_r},
2992 {DEC_LSL_R, dec_lsl_r},
2994 {DEC_AND_R, dec_and_r},
2995 {DEC_OR_R, dec_or_r},
2996 {DEC_BOUND_R, dec_bound_r},
2997 {DEC_ASR_R, dec_asr_r},
2998 {DEC_LSR_R, dec_lsr_r},
3000 {DEC_MOVU_R, dec_movu_r},
3001 {DEC_MOVS_R, dec_movs_r},
3002 {DEC_NEG_R, dec_neg_r},
3003 {DEC_MOVE_R, dec_move_r},
3005 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3006 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3008 {DEC_MULS_R, dec_muls_r},
3009 {DEC_MULU_R, dec_mulu_r},
3011 {DEC_ADDU_M, dec_addu_m},
3012 {DEC_ADDS_M, dec_adds_m},
3013 {DEC_SUBU_M, dec_subu_m},
3014 {DEC_SUBS_M, dec_subs_m},
3016 {DEC_CMPU_M, dec_cmpu_m},
3017 {DEC_CMPS_M, dec_cmps_m},
3018 {DEC_MOVU_M, dec_movu_m},
3019 {DEC_MOVS_M, dec_movs_m},
3021 {DEC_CMP_M, dec_cmp_m},
3022 {DEC_ADDO_M, dec_addo_m},
3023 {DEC_BOUND_M, dec_bound_m},
3024 {DEC_ADD_M, dec_add_m},
3025 {DEC_SUB_M, dec_sub_m},
3026 {DEC_AND_M, dec_and_m},
3027 {DEC_OR_M, dec_or_m},
3028 {DEC_MOVE_RM, dec_move_rm},
3029 {DEC_TEST_M, dec_test_m},
3030 {DEC_MOVE_MR, dec_move_mr},
3035 static inline unsigned int
3036 cris_decoder(DisasContext *dc)
3038 unsigned int insn_len = 2;
3041 if (unlikely(loglevel & CPU_LOG_TB_OP))
3042 tcg_gen_debug_insn_start(dc->pc);
3044 /* Load a halfword onto the instruction register. */
3045 dc->ir = lduw_code(dc->pc);
3047 /* Now decode it. */
3048 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3049 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3050 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3051 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3052 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3053 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3055 /* Large switch for all insns. */
3056 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3057 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3059 insn_len = decinfo[i].dec(dc);
3064 #if !defined(CONFIG_USER_ONLY)
3065 /* Single-stepping ? */
3066 if (dc->tb_flags & S_FLAG) {
3069 l1 = gen_new_label();
3070 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3071 /* We treat SPC as a break with an odd trap vector. */
3072 cris_evaluate_flags (dc);
3073 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3074 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3075 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3076 t_gen_raise_exception(EXCP_BREAK);
3083 static void check_breakpoint(CPUState *env, DisasContext *dc)
3087 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
3088 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
3089 if (bp->pc == dc->pc) {
3090 cris_evaluate_flags (dc);
3091 tcg_gen_movi_tl(env_pc, dc->pc);
3092 t_gen_raise_exception(EXCP_DEBUG);
3093 dc->is_jmp = DISAS_UPDATE;
3101 * Delay slots on QEMU/CRIS.
3103 * If an exception hits on a delayslot, the core will let ERP (the Exception
3104 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3105 * to give SW a hint that the exception actually hit on the dslot.
3107 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3108 * the core and any jmp to an odd addresses will mask off that lsb. It is
3109 * simply there to let sw know there was an exception on a dslot.
3111 * When the software returns from an exception, the branch will re-execute.
3112 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3113 * and the branch and delayslot dont share pages.
3115 * The TB contaning the branch insn will set up env->btarget and evaluate
3116 * env->btaken. When the translation loop exits we will note that the branch
3117 * sequence is broken and let env->dslot be the size of the branch insn (those
3120 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3121 * set). It will also expect to have env->dslot setup with the size of the
3122 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3123 * will execute the dslot and take the branch, either to btarget or just one
3126 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3127 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3128 * branch and set lsb). Then env->dslot gets cleared so that the exception
3129 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3130 * masked off and we will reexecute the branch insn.
3134 /* generate intermediate code for basic block 'tb'. */
3136 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3139 uint16_t *gen_opc_end;
3141 unsigned int insn_len;
3143 struct DisasContext ctx;
3144 struct DisasContext *dc = &ctx;
3145 uint32_t next_page_start;
3153 /* Odd PC indicates that branch is rexecuting due to exception in the
3154 * delayslot, like in real hw.
3156 pc_start = tb->pc & ~1;
3160 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3162 dc->is_jmp = DISAS_NEXT;
3165 dc->singlestep_enabled = env->singlestep_enabled;
3166 dc->flags_uptodate = 1;
3167 dc->flagx_known = 1;
3168 dc->flags_x = tb->flags & X_FLAG;
3169 dc->cc_x_uptodate = 0;
3173 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3174 dc->cc_size_uptodate = -1;
3176 /* Decode TB flags. */
3177 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3178 dc->delayed_branch = !!(tb->flags & 7);
3179 if (dc->delayed_branch)
3180 dc->jmp = JMP_INDIRECT;
3182 dc->jmp = JMP_NOJMP;
3184 dc->cpustate_changed = 0;
3186 if (loglevel & CPU_LOG_TB_IN_ASM) {
3188 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3194 search_pc, dc->pc, dc->ppc,
3195 (unsigned long long)tb->flags,
3196 env->btarget, (unsigned)tb->flags & 7,
3198 env->pregs[PR_PID], env->pregs[PR_USP],
3199 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3200 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3201 env->regs[8], env->regs[9],
3202 env->regs[10], env->regs[11],
3203 env->regs[12], env->regs[13],
3204 env->regs[14], env->regs[15]);
3205 fprintf(logfile, "--------------\n");
3206 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3209 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3212 max_insns = tb->cflags & CF_COUNT_MASK;
3214 max_insns = CF_COUNT_MASK;
3219 check_breakpoint(env, dc);
3222 j = gen_opc_ptr - gen_opc_buf;
3226 gen_opc_instr_start[lj++] = 0;
3228 if (dc->delayed_branch == 1)
3229 gen_opc_pc[lj] = dc->ppc | 1;
3231 gen_opc_pc[lj] = dc->pc;
3232 gen_opc_instr_start[lj] = 1;
3233 gen_opc_icount[lj] = num_insns;
3237 LOG_DIS("%8.8x:\t", dc->pc);
3239 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3243 insn_len = cris_decoder(dc);
3247 cris_clear_x_flag(dc);
3250 /* Check for delayed branches here. If we do it before
3251 actually generating any host code, the simulator will just
3252 loop doing nothing for on this program location. */
3253 if (dc->delayed_branch) {
3254 dc->delayed_branch--;
3255 if (dc->delayed_branch == 0)
3258 t_gen_mov_env_TN(dslot,
3260 if (dc->jmp == JMP_DIRECT) {
3261 dc->is_jmp = DISAS_NEXT;
3263 t_gen_cc_jmp(env_btarget,
3264 tcg_const_tl(dc->pc));
3265 dc->is_jmp = DISAS_JUMP;
3271 /* If we are rexecuting a branch due to exceptions on
3272 delay slots dont break. */
3273 if (!(tb->pc & 1) && env->singlestep_enabled)
3275 } while (!dc->is_jmp && !dc->cpustate_changed
3276 && gen_opc_ptr < gen_opc_end
3277 && (dc->pc < next_page_start)
3278 && num_insns < max_insns);
3281 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3284 if (tb->cflags & CF_LAST_IO)
3286 /* Force an update if the per-tb cpu state has changed. */
3287 if (dc->is_jmp == DISAS_NEXT
3288 && (dc->cpustate_changed || !dc->flagx_known
3289 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3290 dc->is_jmp = DISAS_UPDATE;
3291 tcg_gen_movi_tl(env_pc, npc);
3293 /* Broken branch+delayslot sequence. */
3294 if (dc->delayed_branch == 1) {
3295 /* Set env->dslot to the size of the branch insn. */
3296 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3297 cris_store_direct_jmp(dc);
3300 cris_evaluate_flags (dc);
3302 if (unlikely(env->singlestep_enabled)) {
3303 if (dc->is_jmp == DISAS_NEXT)
3304 tcg_gen_movi_tl(env_pc, npc);
3305 t_gen_raise_exception(EXCP_DEBUG);
3307 switch(dc->is_jmp) {
3309 gen_goto_tb(dc, 1, npc);
3314 /* indicate that the hash table must be used
3315 to find the next TB */
3320 /* nothing more to generate */
3324 gen_icount_end(tb, num_insns);
3325 *gen_opc_ptr = INDEX_op_end;
3327 j = gen_opc_ptr - gen_opc_buf;
3330 gen_opc_instr_start[lj++] = 0;
3332 tb->size = dc->pc - pc_start;
3333 tb->icount = num_insns;
3338 if (loglevel & CPU_LOG_TB_IN_ASM) {
3339 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3340 fprintf(logfile, "\nisize=%d osize=%zd\n",
3341 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3347 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3349 gen_intermediate_code_internal(env, tb, 0);
3352 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3354 gen_intermediate_code_internal(env, tb, 1);
3357 void cpu_dump_state (CPUState *env, FILE *f,
3358 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3367 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3368 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3369 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3371 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3374 for (i = 0; i < 16; i++) {
3375 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3376 if ((i + 1) % 4 == 0)
3377 cpu_fprintf(f, "\n");
3379 cpu_fprintf(f, "\nspecial regs:\n");
3380 for (i = 0; i < 16; i++) {
3381 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3382 if ((i + 1) % 4 == 0)
3383 cpu_fprintf(f, "\n");
3385 srs = env->pregs[PR_SRS];
3386 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3388 for (i = 0; i < 16; i++) {
3389 cpu_fprintf(f, "s%2.2d=%8.8x ",
3390 i, env->sregs[srs][i]);
3391 if ((i + 1) % 4 == 0)
3392 cpu_fprintf(f, "\n");
3395 cpu_fprintf(f, "\n\n");
3399 CPUCRISState *cpu_cris_init (const char *cpu_model)
3402 static int tcg_initialized = 0;
3405 env = qemu_mallocz(sizeof(CPUCRISState));
3412 if (tcg_initialized)
3415 tcg_initialized = 1;
3417 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3418 cc_x = tcg_global_mem_new(TCG_AREG0,
3419 offsetof(CPUState, cc_x), "cc_x");
3420 cc_src = tcg_global_mem_new(TCG_AREG0,
3421 offsetof(CPUState, cc_src), "cc_src");
3422 cc_dest = tcg_global_mem_new(TCG_AREG0,
3423 offsetof(CPUState, cc_dest),
3425 cc_result = tcg_global_mem_new(TCG_AREG0,
3426 offsetof(CPUState, cc_result),
3428 cc_op = tcg_global_mem_new(TCG_AREG0,
3429 offsetof(CPUState, cc_op), "cc_op");
3430 cc_size = tcg_global_mem_new(TCG_AREG0,
3431 offsetof(CPUState, cc_size),
3433 cc_mask = tcg_global_mem_new(TCG_AREG0,
3434 offsetof(CPUState, cc_mask),
3437 env_pc = tcg_global_mem_new(TCG_AREG0,
3438 offsetof(CPUState, pc),
3440 env_btarget = tcg_global_mem_new(TCG_AREG0,
3441 offsetof(CPUState, btarget),
3443 env_btaken = tcg_global_mem_new(TCG_AREG0,
3444 offsetof(CPUState, btaken),
3446 for (i = 0; i < 16; i++) {
3447 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3448 offsetof(CPUState, regs[i]),
3451 for (i = 0; i < 16; i++) {
3452 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3453 offsetof(CPUState, pregs[i]),
3457 #define GEN_HELPER 2
3463 void cpu_reset (CPUCRISState *env)
3465 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3468 env->pregs[PR_VR] = 32;
3469 #if defined(CONFIG_USER_ONLY)
3470 /* start in user mode with interrupts enabled. */
3471 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3473 env->pregs[PR_CCS] = 0;
3477 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3478 unsigned long searched_pc, int pc_pos, void *puc)
3480 env->pc = gen_opc_pc[pc_pos];